From 1441b2a85957f1bf6e6952621e3047348ceaa3f9 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 22 Jun 2020 17:27:05 +1000 Subject: [PATCH 1/6] litedram: l2: Latency improvements This implements in the L2 cache the feature already in the L1s allowing a request to be completed before the end of a refill using partial line valid bits, and starting a refill from the row of the first miss on that line instead of the beginning of the line. Signed-off-by: Benjamin Herrenschmidt --- dram_tb.vhdl | 37 ++++ litedram/extras/litedram-wrapper-l2.vhdl | 208 ++++++++++++++--------- litedram/extras/wave_tb.gtkw | 15 +- 3 files changed, 173 insertions(+), 87 deletions(-) diff --git a/dram_tb.vhdl b/dram_tb.vhdl index f368e2f..11863c0 100644 --- a/dram_tb.vhdl +++ b/dram_tb.vhdl @@ -293,6 +293,43 @@ begin check_data(make_pattern(i)); end loop; + report "Pre-fill a line"; + a(11) := '1'; + clr_acks; + wb_write(add_off(a, 0), x"1111111100000000", x"ff"); + wb_write(add_off(a, 8), x"3333333322222222", x"ff"); + wb_write(add_off(a, 16), x"5555555544444444", x"ff"); + wb_write(add_off(a, 24), x"7777777766666666", x"ff"); + wb_write(add_off(a, 32), x"9999999988888888", x"ff"); + wb_write(add_off(a, 40), x"bbbbbbbbaaaaaaaa", x"ff"); + wb_write(add_off(a, 48), x"ddddddddcccccccc", x"ff"); + wb_write(add_off(a, 56), x"ffffffffeeeeeeee", x"ff"); + wb_write(add_off(a, 64), x"1111111100000000", x"ff"); + wb_write(add_off(a, 72), x"3333333322222222", x"ff"); + wb_write(add_off(a, 80), x"5555555544444444", x"ff"); + wb_write(add_off(a, 88), x"7777777766666666", x"ff"); + wb_write(add_off(a, 96), x"9999999988888888", x"ff"); + wb_write(add_off(a,104), x"bbbbbbbbaaaaaaaa", x"ff"); + wb_write(add_off(a,112), x"ddddddddcccccccc", x"ff"); + wb_write(add_off(a,120), x"ffffffffeeeeeeee", x"ff"); + wait_acks(16); + + report "Scattered from middle of line..."; + clr_acks; + wb_read(add_off(a,24)); + wb_read(add_off(a,32)); + wb_read(add_off(a, 0)); + wb_read(add_off(a,16)); + wait_acks(4); + read_data(d); + assert d = x"7777777766666666" report "bad data (24), got " & to_hstring(d) severity failure; + read_data(d); + assert d = x"9999999988888888" report "bad data (32), got " & to_hstring(d) severity failure; + read_data(d); + assert d = x"1111111100000000" report "bad data (0), got " & to_hstring(d) severity failure; + read_data(d); + assert d = x"5555555544444444" report "bad data (16), got " & to_hstring(d) severity failure; + std.env.finish; end process; end architecture; diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl index 61b4867..5c9eb07 100644 --- a/litedram/extras/litedram-wrapper-l2.vhdl +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -189,6 +189,7 @@ architecture behaviour of litedram_wrapper is subtype row_t is integer range 0 to BRAM_ROWS-1; subtype index_t is integer range 0 to NUM_LINES-1; subtype way_t is integer range 0 to NUM_WAYS-1; + subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0); -- The cache data BRAM organized as described above for each way subtype cache_row_t is std_ulogic_vector(DRAM_DBITS-1 downto 0); @@ -207,6 +208,9 @@ architecture behaviour of litedram_wrapper is subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0); type cache_valids_t is array(index_t) of cache_way_valids_t; + -- "Temporary" valid bits for the rows of the currently refilled line + type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic; + -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs signal cache_tags : cache_tags_array_t; signal cache_valids : cache_valids_t; @@ -233,7 +237,7 @@ architecture behaviour of litedram_wrapper is -- Cache management signals -- - -- Cache state machine + -- Cache state machine type state_t is (IDLE, -- Normal load hit processing REFILL_CLR_TAG, -- Cache refill clear tag REFILL_WAIT_ACK); -- Cache refill wait ack @@ -261,7 +265,8 @@ architecture behaviour of litedram_wrapper is OP_LOAD_HIT, OP_LOAD_MISS, OP_STORE_HIT, - OP_STORE_MISS); + OP_STORE_MISS, + OP_STORE_DELAYED); signal req_index : index_t; signal req_row : row_t; @@ -272,7 +277,6 @@ architecture behaviour of litedram_wrapper is signal req_ad3 : std_ulogic; signal req_we : std_ulogic_vector(DRAM_SBITS-1 downto 0); signal req_wdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); - signal accept_store : std_ulogic; signal stall : std_ulogic; -- Line refill command signals and latches @@ -281,6 +285,8 @@ architecture behaviour of litedram_wrapper is signal refill_way : way_t; signal refill_index : index_t; signal refill_row : row_t; + signal refill_end_row : row_in_line_t; + signal refill_rows_vlid : row_per_line_valid_t; -- Cache RAM interface type cache_ram_out_t is array(way_t) of cache_row_t; @@ -306,21 +312,25 @@ architecture behaviour of litedram_wrapper is return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS))); end; + -- Return the index of a row within a line + function get_row_of_line(row: row_t) return row_in_line_t is + variable row_v : unsigned(ROW_BITS-1 downto 0); + begin + row_v := to_unsigned(row, ROW_BITS); + return row_v(ROW_LINEBITS-1 downto 0); + end; -- Returns whether this is the last row of a line. It takes a DRAM address - function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS)) + function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS); + last: row_in_line_t) return boolean is - constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1'); begin - return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones; + return unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last; end; -- Returns whether this is the last row of a line - function is_last_row(row: row_t) return boolean is - variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0); - constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1'); + function is_last_row(row: row_t; last: row_in_line_t) return boolean is begin - row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS)); - return row_v(ROW_LINEBITS-1 downto 0) = ones; + return get_row_of_line(row) = last; end; -- Return the address of the next row in the current cache line. It takes a @@ -493,7 +503,7 @@ begin -- -- Write mux: cache refills from DRAM or writes from Wishbone -- - if state = IDLE then + if req_op = OP_STORE_HIT and req_hit_way = i then -- Write from wishbone wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS)); wr_data <= req_wdata; @@ -570,7 +580,7 @@ begin end generate; -- - -- Wishbone interface: + -- Wishbone request interface: -- -- - Incoming wishbone request latch (to help with timing) -- - Read response pipeline (to match BRAM output buffer delay) @@ -632,7 +642,6 @@ begin -- -- Read response pipeline -- - -- XXX Might have to put store acks in there too (see comment in wb_response) read_pipe: process(system_clk) begin if rising_edge(system_clk) then @@ -670,54 +679,46 @@ begin end if; end process; + -- + -- Wishbone response generation + -- + wb_reponse: process(all) - variable rdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); - variable store_done : std_ulogic; + variable rdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); + variable store_done : std_ulogic; + variable accept_store : std_ulogic; begin - -- Can we accept a store ? This is set when IDLE and the store - -- queue & command queue are not full. + -- Can we accept a store ? This is set when the store queue & command + -- queue are not full. -- - -- Note: This is only used to control the WB request latch, stall - -- and store "early complete". We don't want to use this to control - -- cmd_valid to DRAM as this would create a circular dependency inside - -- LiteDRAM as cmd_ready I think is driven from cmd_valid. + -- This does *not* mean that we will accept the store, there are other + -- reasons to delay them (see OP_STORE_DELAYED). -- - -- The state machine that controls the command queue must thus - -- reproduce this logic at least partially. + -- A store is fully accepted when *both* req_op is not OP_STORE_DELAYED + -- and accept_store is '1'. -- - -- Note also that user_port0_cmd_ready from LiteDRAM is combinational - -- from user_port0_cmd_valid. IE. we won't know that LiteDRAM cannot - -- accept a command until we try to send one. + -- The reason for this split is to avoid a circular dependency inside + -- LiteDRAM, since cmd_ready from litedram is driven from cmd_valid (*) + -- we don't want to generate cmd_valid from cmd_ready. So we generate + -- it instead from all the *other* conditions that make a store valid. -- - if state = IDLE then - accept_store <= user_port0_cmd_ready and storeq_wr_ready; - - -- Corner case !!! The read acks pipeline takes two extra cycles - -- which means a store ack can collide with a previous load hit - -- ack. Thus we stall stores if we have a load ack pending. - if read_ack_0 = '1' or read_ack_1 = '1' then - accept_store <= '0'; - end if; + -- (*) It's my understanding that user_port0_cmd_ready from LiteDRAM is + -- ombinational from user_port0_cmd_valid along with a bunch of other + -- internal signals. IE. we won't know that LiteDRAM cannot accept a + -- command until we try to send one. + -- + accept_store := user_port0_cmd_ready and storeq_wr_ready; + + -- Generate stalls. For stores we stall if we can't accept it. + -- For loads, we stall if we are going to take a load miss or + -- are in the middle of a refill and it isn't a partial hit. + if req_op = OP_STORE_MISS or req_op = OP_STORE_HIT then + stall <= not accept_store; + elsif req_op = OP_LOAD_MISS or req_op = OP_STORE_DELAYED then + stall <= '1'; else - accept_store <= '0'; + stall <= '0'; end if; - - -- Generate stalls. For loads, we stall if we are going to take a load - -- miss or are in the middle of a refill. For stores, if we can't - -- accept it. - case state is - when IDLE => - case req_op is - when OP_LOAD_MISS => - stall <= '1'; - when OP_STORE_MISS | OP_STORE_HIT => - stall <= not accept_store; - when others => - stall <= '0'; - end case; - when others => - stall <= '1'; - end case; -- Data out mux rdata := cache_out(read_way_1); @@ -736,7 +737,8 @@ begin -- Generate Wishbone ACKs on read hits and store complete -- -- This can happen on store right behind loads ! This is why - -- we don't accept a new store right behind a load ack above. + -- we delay a store when a load ack is in the pipeline in the + -- request decoder below. -- wb_out.ack <= read_ack_1 or store_ack_1; assert read_ack_1 = '0' or store_ack_1 = '0' report @@ -748,27 +750,24 @@ begin -- Cache request decode -- request_decode: process(all) - variable valid : std_ulogic; - variable is_hit : std_ulogic; - variable hit_way : way_t; + variable valid : boolean; + variable is_hit : boolean; + variable store_delay : boolean; + variable hit_way : way_t; begin -- Extract line, row and tag from request req_index <= get_index(wb_req.adr); req_row <= get_row(wb_req.adr(REAL_ADDR_BITS-1 downto 0)); req_tag <= get_tag(wb_req.adr); - -- Calculate address of beginning of cache line, will be + -- Calculate address of beginning of cache row, will be -- used for cache miss processing if needed - req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) & - (LINE_OFF_BITS-1 downto 0 => '0'); + req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) & + (ROW_OFF_BITS-1 downto 0 => '0'); -- Do we have a valid request in the WB latch ? - if state = IDLE then - valid := wb_req.cyc and wb_req.stb; - else - valid := '0'; - end if; + valid := wb_req.cyc = '1' and wb_req.stb = '1'; -- Store signals req_ad3 <= wb_req.adr(3); @@ -778,30 +777,67 @@ begin -- Test if pending request is a hit on any way hit_way := 0; - is_hit := '0'; + is_hit := false; for i in way_t loop - if valid = '1' and cache_valids(req_index)(i) = '1' then + if valid and + (cache_valids(req_index)(i) = '1' or + (state = REFILL_WAIT_ACK and + req_index = refill_index and i = refill_way and + refill_rows_vlid(req_row mod ROW_PER_LINE) = '1')) then if read_tag(i, cache_tags(req_index)) = req_tag then hit_way := i; - is_hit := '1'; + is_hit := true; end if; end if; end loop; + -- We need to delay stores under some circumstances to avoid + -- collisions with the refill machine. + -- + -- Corner case !!! The read acks pipeline takes two extra cycles + -- which means a store ack can collide with a previous load hit + -- ack. Thus we stall stores if we have a load ack pending. + -- + if read_ack_0 = '1' or read_ack_1 = '1' then + -- Clash with pending read acks, delay.. + store_delay := true; + elsif state /= IDLE then + -- If the reload machine is active, we cannot accept a store + -- for now. + -- + -- We could improve this a bit by allowing stores if we have sent + -- all the requests down to litedram (we are only waiting for the + -- responses) *and* either of those conditions is true: + -- + -- * It's a miss (doesn't require a write to BRAM) and isn't + -- for the line being reloaded (otherwise we might reload + -- stale data into the cache). + -- * It's a hit on a different way than the one being reloaded + -- in which case there is no conflict for BRAM access. + -- + -- Otherwise we delay it... + -- + store_delay := true; + else + store_delay := false; + end if; + -- Generate the req op. We only allow OP_LOAD_* when in the -- IDLE state as our PLRU and ACK generation rely on this, -- stores are allowed in IDLE state. -- req_op <= OP_NONE; - if valid = '1' then + if valid then if wb_req.we = '1' then - if is_hit = '1' then + if store_delay then + req_op <= OP_STORE_DELAYED; + elsif is_hit then req_op <= OP_STORE_HIT; else req_op <= OP_STORE_MISS; end if; else - if is_hit = '1' then + if is_hit then req_op <= OP_LOAD_HIT; else req_op <= OP_LOAD_MISS; @@ -837,7 +873,7 @@ begin begin storeq_wr_data <= wb_req.dat & req_we; - -- Only accept store if we can send a command + -- Only queue stores if we can also send a command if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then storeq_wr_valid <= user_port0_cmd_ready; else @@ -858,13 +894,13 @@ begin to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) & " data:" & to_hstring(req_wdata) & " we:" & to_hstring(req_we) & - " V:" & std_ulogic'image(accept_store); + " V:" & std_ulogic'image(user_port0_cmd_ready); else report "Store miss to:" & to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) & " data:" & to_hstring(req_wdata) & " we:" & to_hstring(req_we) & - " V:" & std_ulogic'image(accept_store); + " V:" & std_ulogic'image(user_port0_cmd_ready); end if; if storeq_wr_valid = '1' and storeq_wr_ready = '1' then report "storeq push " & to_hstring(storeq_wr_data); @@ -879,9 +915,9 @@ begin -- LiteDRAM command mux dram_commands: process(all) begin - if state = IDLE and (req_op = OP_STORE_HIT or req_op = OP_STORE_MISS) then + if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then -- For stores, forward signals directly. Only send command if - -- the FIFO can accept a store + -- the FIFO can accept a store. user_port0_cmd_addr <= wb_req.adr(DRAM_ABITS+3 downto 4); user_port0_cmd_we <= '1'; user_port0_cmd_valid <= storeq_wr_ready; @@ -918,6 +954,11 @@ begin assert refill_cmd_valid = '0' report "refill cmd valid in IDLE state !" severity failure; + -- Reset per-row valid flags, only used in WAIT_ACK + for i in 0 to ROW_PER_LINE - 1 loop + refill_rows_vlid(i) <= '0'; + end loop; + -- If NO_LS_OVERLAP is set, disallow a load miss if the store -- queue still has data in it. wait_qdrain := false; @@ -931,8 +972,9 @@ begin refill_way <= to_integer(unsigned(plru_victim(req_index))); -- Keep track of our index and way for subsequent stores - refill_index <= req_index; - refill_row <= get_row(req_laddr); + refill_index <= req_index; + refill_row <= get_row(req_laddr); + refill_end_row <= get_row_of_line(get_row(req_laddr)) - 1; -- Prep for first DRAM read -- @@ -982,7 +1024,7 @@ begin if TRACE then report "got refill cmd ack !"; end if; - if is_last_row_addr(refill_cmd_addr) then + if is_last_row_addr(refill_cmd_addr, refill_end_row) then refill_cmd_valid <= '0'; cmds_done := true; if TRACE then @@ -1003,8 +1045,12 @@ begin if TRACE then report "got refill data ack !"; end if; + + -- Mark partial line valid + refill_rows_vlid(refill_row mod ROW_PER_LINE) <= '1'; + -- Check for completion - if cmds_done and is_last_row(refill_row) then + if cmds_done and is_last_row(refill_row, refill_end_row) then if TRACE then report "all refill data done !"; end if; diff --git a/litedram/extras/wave_tb.gtkw b/litedram/extras/wave_tb.gtkw index fcdf6a9..c675d7b 100644 --- a/litedram/extras/wave_tb.gtkw +++ b/litedram/extras/wave_tb.gtkw @@ -1,17 +1,18 @@ [*] [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI -[*] Sun May 31 12:53:52 2020 +[*] Mon Jun 22 06:32:16 2020 [*] [dumpfile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/foo.ghw" -[dumpfile_mtime] "Sun May 31 12:50:15 2020" -[dumpfile_size] 1134118 +[dumpfile_mtime] "Mon Jun 22 06:28:35 2020" +[dumpfile_size] 1680014 [savefile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/litedram/extras/wave_tb.gtkw" -[timestart] 1312950000 +[timestart] 1920580000 [size] 2509 1371 [pos] -1 -1 -*-24.248457 1386890000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-24.248457 1935000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] top. [treeopen] top.dram_tb. +[treeopen] top.dram_tb.dram. [sst_width] 301 [signals_width] 433 [sst_expanded] 1 @@ -26,7 +27,6 @@ top.dram_tb.clk @22 #{top.dram_tb.wb_in.dat[63:0]} top.dram_tb.wb_in.dat[63] top.dram_tb.wb_in.dat[62] top.dram_tb.wb_in.dat[61] top.dram_tb.wb_in.dat[60] top.dram_tb.wb_in.dat[59] top.dram_tb.wb_in.dat[58] top.dram_tb.wb_in.dat[57] top.dram_tb.wb_in.dat[56] top.dram_tb.wb_in.dat[55] top.dram_tb.wb_in.dat[54] top.dram_tb.wb_in.dat[53] top.dram_tb.wb_in.dat[52] top.dram_tb.wb_in.dat[51] top.dram_tb.wb_in.dat[50] top.dram_tb.wb_in.dat[49] top.dram_tb.wb_in.dat[48] top.dram_tb.wb_in.dat[47] top.dram_tb.wb_in.dat[46] top.dram_tb.wb_in.dat[45] top.dram_tb.wb_in.dat[44] top.dram_tb.wb_in.dat[43] top.dram_tb.wb_in.dat[42] top.dram_tb.wb_in.dat[41] top.dram_tb.wb_in.dat[40] top.dram_tb.wb_in.dat[39] top.dram_tb.wb_in.dat[38] top.dram_tb.wb_in.dat[37] top.dram_tb.wb_in.dat[36] top.dram_tb.wb_in.dat[35] top.dram_tb.wb_in.dat[34] top.dram_tb.wb_in.dat[33] top.dram_tb.wb_in.dat[32] top.dram_tb.wb_in.dat[31] top.dram_tb.wb_in.dat[30] top.dram_tb.wb_in.dat[29] top.dram_tb.wb_in.dat[28] top.dram_tb.wb_in.dat[27] top.dram_tb.wb_in.dat[26] top.dram_tb.wb_in.dat[25] top.dram_tb.wb_in.dat[24] top.dram_tb.wb_in.dat[23] top.dram_tb.wb_in.dat[22] top.dram_tb.wb_in.dat[21] top.dram_tb.wb_in.dat[20] top.dram_tb.wb_in.dat[19] top.dram_tb.wb_in.dat[18] top.dram_tb.wb_in.dat[17] top.dram_tb.wb_in.dat[16] top.dram_tb.wb_in.dat[15] top.dram_tb.wb_in.dat[14] top.dram_tb.wb_in.dat[13] top.dram_tb.wb_in.dat[12] top.dram_tb.wb_in.dat[11] top.dram_tb.wb_in.dat[10] top.dram_tb.wb_in.dat[9] top.dram_tb.wb_in.dat[8] top.dram_tb.wb_in.dat[7] top.dram_tb.wb_in.dat[6] top.dram_tb.wb_in.dat[5] top.dram_tb.wb_in.dat[4] top.dram_tb.wb_in.dat[3] top.dram_tb.wb_in.dat[2] top.dram_tb.wb_in.dat[1] top.dram_tb.wb_in.dat[0] #{top.dram_tb.wb_in.adr[31:0]} top.dram_tb.wb_in.adr[31] top.dram_tb.wb_in.adr[30] top.dram_tb.wb_in.adr[29] top.dram_tb.wb_in.adr[28] top.dram_tb.wb_in.adr[27] top.dram_tb.wb_in.adr[26] top.dram_tb.wb_in.adr[25] top.dram_tb.wb_in.adr[24] top.dram_tb.wb_in.adr[23] top.dram_tb.wb_in.adr[22] top.dram_tb.wb_in.adr[21] top.dram_tb.wb_in.adr[20] top.dram_tb.wb_in.adr[19] top.dram_tb.wb_in.adr[18] top.dram_tb.wb_in.adr[17] top.dram_tb.wb_in.adr[16] top.dram_tb.wb_in.adr[15] top.dram_tb.wb_in.adr[14] top.dram_tb.wb_in.adr[13] top.dram_tb.wb_in.adr[12] top.dram_tb.wb_in.adr[11] top.dram_tb.wb_in.adr[10] top.dram_tb.wb_in.adr[9] top.dram_tb.wb_in.adr[8] top.dram_tb.wb_in.adr[7] top.dram_tb.wb_in.adr[6] top.dram_tb.wb_in.adr[5] top.dram_tb.wb_in.adr[4] top.dram_tb.wb_in.adr[3] top.dram_tb.wb_in.adr[2] top.dram_tb.wb_in.adr[1] top.dram_tb.wb_in.adr[0] -@23 #{top.dram_tb.wb_in.sel[7:0]} top.dram_tb.wb_in.sel[7] top.dram_tb.wb_in.sel[6] top.dram_tb.wb_in.sel[5] top.dram_tb.wb_in.sel[4] top.dram_tb.wb_in.sel[3] top.dram_tb.wb_in.sel[2] top.dram_tb.wb_in.sel[1] top.dram_tb.wb_in.sel[0] @28 top.dram_tb.wb_in.cyc @@ -67,6 +67,9 @@ top.dram_tb.dram.user_port0_cmd_valid top.dram_tb.dram.refill_cmd_valid @420 top.dram_tb.dram.req_index +@421 +top.dram_tb.dram.req_row +@420 top.dram_tb.dram.req_hit_way @28 top.dram_tb.dram.req_ad3 From 02abb135a89f2a2c6ebbcfbe2d9d7775c2e67f7b Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 24 Jun 2020 12:02:55 +1000 Subject: [PATCH 2/6] litedram: l2: Add support for more geometries Make the DRAM data lines and user port width configurable, also don't hard wire dependency on the wishbone data width. Signed-off-by: Benjamin Herrenschmidt --- core_dram_tb.vhdl | 2 + dram_tb.vhdl | 2 + fpga/top-arty.vhdl | 2 + fpga/top-nexys-video.vhdl | 2 + litedram/extras/litedram-wrapper-l2.vhdl | 120 ++++++++++++++--------- 5 files changed, 83 insertions(+), 45 deletions(-) diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl index d0890cb..7df3dfd 100644 --- a/core_dram_tb.vhdl +++ b/core_dram_tb.vhdl @@ -120,6 +120,8 @@ begin generic map( DRAM_ABITS => 24, DRAM_ALINES => 1, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => DRAM_INIT_FILE, PAYLOAD_SIZE => ROM_SIZE ) diff --git a/dram_tb.vhdl b/dram_tb.vhdl index 11863c0..571bd70 100644 --- a/dram_tb.vhdl +++ b/dram_tb.vhdl @@ -43,6 +43,8 @@ begin generic map( DRAM_ABITS => 24, DRAM_ALINES => 1, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => DRAM_INIT_FILE, PAYLOAD_SIZE => DRAM_INIT_SIZE ) diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 9dc476f..a4d253d 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -341,6 +341,8 @@ begin generic map( DRAM_ABITS => 24, DRAM_ALINES => 14, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => RAM_INIT_FILE, PAYLOAD_SIZE => PAYLOAD_SIZE ) diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 15fa176..745ef79 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -258,6 +258,8 @@ begin generic map( DRAM_ABITS => 25, DRAM_ALINES => 15, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => RAM_INIT_FILE, PAYLOAD_SIZE => PAYLOAD_SIZE ) diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl index 5c9eb07..669a23c 100644 --- a/litedram/extras/litedram-wrapper-l2.vhdl +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -10,8 +10,10 @@ use work.helpers.all; entity litedram_wrapper is generic ( - DRAM_ABITS : positive; - DRAM_ALINES : positive; + DRAM_ABITS : positive; + DRAM_ALINES : natural; + DRAM_DLINES : natural; + DRAM_PORT_WIDTH : positive; -- Pseudo-ROM payload PAYLOAD_SIZE : natural; @@ -63,10 +65,10 @@ entity litedram_wrapper is ddram_cas_n : out std_ulogic; ddram_we_n : out std_ulogic; ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_dm : out std_ulogic_vector(DRAM_DLINES/8-1 downto 0); + ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0); + ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); ddram_clk_p : out std_ulogic; ddram_clk_n : out std_ulogic; ddram_cke : out std_ulogic; @@ -87,10 +89,10 @@ architecture behaviour of litedram_wrapper is ddram_cas_n : out std_ulogic; ddram_we_n : out std_ulogic; ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_dm : out std_ulogic_vector(DRAM_DLINES/8-1 downto 0); + ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0); + ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); ddram_clk_p : out std_ulogic; ddram_clk_n : out std_ulogic; ddram_cke : out std_ulogic; @@ -117,11 +119,11 @@ architecture behaviour of litedram_wrapper is user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); user_port_native_0_wdata_valid : in std_ulogic; user_port_native_0_wdata_ready : out std_ulogic; - user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); - user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_wdata_we : in std_ulogic_vector(DRAM_PORT_WIDTH/8-1 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0); user_port_native_0_rdata_valid : out std_ulogic; user_port_native_0_rdata_ready : in std_ulogic; - user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) + user_port_native_0_rdata_data : out std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0) ); end component; @@ -131,11 +133,11 @@ architecture behaviour of litedram_wrapper is signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); signal user_port0_wdata_valid : std_ulogic; signal user_port0_wdata_ready : std_ulogic; - signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); - signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_wdata_we : std_ulogic_vector(DRAM_PORT_WIDTH/8-1 downto 0); + signal user_port0_wdata_data : std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0); signal user_port0_rdata_valid : std_ulogic; signal user_port0_rdata_ready : std_ulogic; - signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_rdata_data : std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0); signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); @@ -150,14 +152,24 @@ architecture behaviour of litedram_wrapper is signal wb_init_out : wb_io_slave_out; -- DRAM data port width - constant DRAM_DBITS : natural := 128; + constant DRAM_DBITS : natural := DRAM_PORT_WIDTH; + -- DRAM data port sel bits constant DRAM_SBITS : natural := (DRAM_DBITS / 8); + -- WB geometry (just a few shortcuts) + constant WBL : positive := wb_in.dat'length; + constant WBSL : positive := wb_in.sel'length; + + -- Select a WB word inside DRAM port width + constant WB_WORD_COUNT : positive := DRAM_DBITS/WBL; + constant WB_WSEL_BITS : positive := log2(WB_WORD_COUNT); + constant WB_WSEL_RIGHT : positive := log2(WBL/8); + -- BRAM organisation: We never access more than wishbone_data_bits at -- a time so to save resources we make the array only that wide, and -- use consecutive indices for to make a cache "line" -- - -- ROW_SIZE is the width in bytes of the BRAM (based on litedram, so 128-bits) + -- ROW_SIZE is the width in bytes of the BRAM, ie, litedram port width constant ROW_SIZE : natural := DRAM_DBITS / 8; -- ROW_PER_LINE is the number of row (litedram transactions) in a line constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE; @@ -184,7 +196,7 @@ architecture behaviour of litedram_wrapper is -- TAG_BITS is the number of bits of the tag part of the address constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS; -- WAY_BITS is the number of bits to select a way - constant WAY_BITS : natural := log2(NUM_WAYS); + constant WAY_BITS : natural := log2(NUM_WAYS); subtype row_t is integer range 0 to BRAM_ROWS-1; subtype index_t is integer range 0 to NUM_LINES-1; @@ -221,10 +233,10 @@ architecture behaviour of litedram_wrapper is -- -- Store queue signals -- - -- We store a single wishbone dword per entry (64-bit) but all - -- 16 sel bits for the DRAM. - -- XXX Investigate storing only AD3 and 8 sel bits if it's better - constant STOREQ_BITS : positive := wishbone_data_bits + DRAM_SBITS; + -- We store a single wishbone dword per entry (64-bit) + -- along with the wishbone sel bits and the necessary address + -- bits to select which part of DRAM port to write to. + constant STOREQ_BITS : positive := WBL + WBSL + WB_WSEL_BITS; signal storeq_rd_ready : std_ulogic; signal storeq_rd_valid : std_ulogic; @@ -251,8 +263,8 @@ architecture behaviour of litedram_wrapper is -- Read pipeline (to handle cache RAM latency) signal read_ack_0 : std_ulogic := '0'; signal read_ack_1 : std_ulogic := '0'; - signal read_ad3_0 : std_ulogic; - signal read_ad3_1 : std_ulogic; + signal read_wsl_0 : std_ulogic_vector(WB_WSEL_BITS-1 downto 0) := (others => '0'); + signal read_wsl_1 : std_ulogic_vector(WB_WSEL_BITS-1 downto 0) := (others => '0'); signal read_way_0 : way_t; signal read_way_1 : way_t; @@ -274,7 +286,7 @@ architecture behaviour of litedram_wrapper is signal req_tag : cache_tag_t; signal req_op : req_op_t; signal req_laddr : std_ulogic_vector(REAL_ADDR_BITS-1 downto 0); - signal req_ad3 : std_ulogic; + signal req_wsl : std_ulogic_vector(WB_WSEL_BITS-1 downto 0); signal req_we : std_ulogic_vector(DRAM_SBITS-1 downto 0); signal req_wdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); signal stall : std_ulogic; @@ -397,8 +409,6 @@ begin report "geometry bits don't add up" severity FAILURE; assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS) report "geometry bits don't add up" severity FAILURE; - assert (128 = DRAM_DBITS) - report "Can't yet handle a DRAM width that isn't 128-bits" severity FAILURE; -- alternate core reset address set when DRAM is not initialized. core_alt_reset <= not init_done; @@ -646,11 +656,11 @@ begin begin if rising_edge(system_clk) then read_ack_0 <= '1' when req_op = OP_LOAD_HIT else '0'; - read_ad3_0 <= req_ad3; + read_wsl_0 <= req_wsl; read_way_0 <= req_hit_way; read_ack_1 <= read_ack_0; - read_ad3_1 <= read_ad3_0; + read_wsl_1 <= read_wsl_0; read_way_1 <= read_way_0; if TRACE then @@ -683,10 +693,11 @@ begin -- Wishbone response generation -- - wb_reponse: process(all) + wb_rseponse: process(all) variable rdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); variable store_done : std_ulogic; variable accept_store : std_ulogic; + variable wsel : natural range 0 to WB_WORD_COUNT-1; begin -- Can we accept a store ? This is set when the store queue & command -- queue are not full. @@ -722,7 +733,10 @@ begin -- Data out mux rdata := cache_out(read_way_1); - wb_out.dat <= rdata(127 downto 64) when read_ad3_1 = '1' else rdata(63 downto 0); + + -- Hard wired for 64-bit wishbone + wsel := to_integer(unsigned(read_wsl_1)); + wb_out.dat <= rdata((wsel+1)*WBL-1 downto wsel*WBL); -- Early-complete stores on wishbone. if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then @@ -769,11 +783,16 @@ begin -- Do we have a valid request in the WB latch ? valid := wb_req.cyc = '1' and wb_req.stb = '1'; - -- Store signals - req_ad3 <= wb_req.adr(3); - req_wdata <= wb_req.dat & wb_req.dat; - req_we <= wb_req.sel & "00000000" when req_ad3 = '1' else - "00000000" & wb_req.sel; + -- Store signals (hard wired for 64-bit wishbone at the moment) + req_wsl <= wb_req.adr(WB_WSEL_RIGHT+WB_WSEL_BITS-1 downto WB_WSEL_RIGHT); + for i in 0 to WB_WORD_COUNT-1 loop + if to_integer(unsigned(req_wsl)) = i then + req_we(WBSL*(i+1)-1 downto WBSL*i) <= wb_req.sel; + else + req_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00"; + end if; + req_wdata(WBL*(i+1)-1 downto WBL*i) <= wb_req.dat; + end loop; -- Test if pending request is a hit on any way hit_way := 0; @@ -869,9 +888,11 @@ begin storeq_control : process(all) variable stq_data : wishbone_data_type; - variable stq_sel : std_ulogic_vector(DRAM_SBITS-1 downto 0); + variable stq_sel : wishbone_sel_type; + variable stq_wsl : std_ulogic_vector(WB_WSEL_BITS-1 downto 0); begin - storeq_wr_data <= wb_req.dat & req_we; + storeq_wr_data <= wb_req.dat & wb_req.sel & + wb_req.adr(WB_WSEL_RIGHT+WB_WSEL_BITS-1 downto WB_WSEL_RIGHT); -- Only queue stores if we can also send a command if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then @@ -880,10 +901,19 @@ begin storeq_wr_valid <= '0'; end if; - stq_data := storeq_rd_data(storeq_rd_data'left downto DRAM_SBITS); - stq_sel := storeq_rd_data(DRAM_SBITS-1 downto 0); - user_port0_wdata_data <= stq_data & stq_data; - user_port0_wdata_we <= stq_sel; + -- Store signals (hard wired for 64-bit wishbone at the moment) + stq_data := storeq_rd_data(storeq_rd_data'left downto WBSL+WB_WSEL_BITS); + stq_sel := storeq_rd_data(WBSL+WB_WSEL_BITS-1 downto WB_WSEL_BITS); + stq_wsl := storeq_rd_data(WB_WSEL_BITS-1 downto 0); + for i in 0 to WB_WORD_COUNT-1 loop + if to_integer(unsigned(stq_wsl)) = i then + user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= stq_sel; + else + user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00"; + end if; + user_port0_wdata_data(WBL*(i+1)-1 downto WBL*i) <= stq_data; + end loop; + user_port0_wdata_valid <= storeq_rd_valid; storeq_rd_ready <= user_port0_wdata_ready; @@ -918,7 +948,7 @@ begin if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then -- For stores, forward signals directly. Only send command if -- the FIFO can accept a store. - user_port0_cmd_addr <= wb_req.adr(DRAM_ABITS+3 downto 4); + user_port0_cmd_addr <= wb_req.adr(DRAM_ABITS+ROW_OFF_BITS-1 downto ROW_OFF_BITS); user_port0_cmd_we <= '1'; user_port0_cmd_valid <= storeq_wr_ready; else @@ -983,7 +1013,7 @@ begin -- "dram_commands". In fact, we could make refill_cmd_addr -- only contain the "counter" bits and wire it with the -- other bits from req_laddr. - refill_cmd_addr <= req_laddr(DRAM_ABITS+3 downto 4); + refill_cmd_addr <= req_laddr(DRAM_ABITS+ROW_OFF_BITS-1 downto ROW_OFF_BITS); refill_cmd_valid <= '1'; if TRACE then From bedc9c008559c2c0691aea0906eb60b5ae7d5f36 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 26 Jun 2020 14:52:06 +1000 Subject: [PATCH 3/6] litedram: l2: Add a few comments about litedram behaviour litedram ignores a couple of signals of his "pseudo-axi" port, this adds a bit of documentation around it. Signed-off-by: Benjamin Herrenschmidt --- litedram/extras/litedram-wrapper-l2.vhdl | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl index 669a23c..5823f19 100644 --- a/litedram/extras/litedram-wrapper-l2.vhdl +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -914,6 +914,12 @@ begin user_port0_wdata_data(WBL*(i+1)-1 downto WBL*i) <= stq_data; end loop; + -- Note: Current litedram ignores user_port0_wdata_valid. We + -- must make sure to always have the data available at the + -- output of the store queue when we send the write command. + -- + -- Thankfully this is always the case with this design. + -- user_port0_wdata_valid <= storeq_rd_valid; storeq_rd_ready <= user_port0_wdata_ready; @@ -957,6 +963,9 @@ begin user_port0_cmd_valid <= refill_cmd_valid; user_port0_cmd_we <= '0'; end if; + + -- Note: litedram ignores this signal and assumes we are + -- always ready to accept read data. user_port0_rdata_ready <= '1'; -- Always 1 end process; From cc35c499289d0a936517896627e0be209514c5ee Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 24 Jun 2020 13:43:29 +1000 Subject: [PATCH 4/6] litedram: Add generator for Genesys2 (Not yet generated) Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/generate.py | 2 +- litedram/gen-src/genesys2.yml | 41 +++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 litedram/gen-src/genesys2.yml diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 15cd846..cb6aab2 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -143,7 +143,7 @@ def generate_one(t): def main(): - targets = ['arty','nexys-video', 'sim'] + targets = ['arty','nexys-video', 'genesys2', 'sim'] for t in targets: generate_one(t) diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml new file mode 100644 index 0000000..9f2108b --- /dev/null +++ b/litedram/gen-src/genesys2.yml @@ -0,0 +1,41 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + +{ + # General ------------------------------------------------------------------ + "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) + "cpu_variant":"standard", + "speedgrade": -2, # FPGA speedgrade + "memtype": "DDR3", # DRAM type + + # PHY ---------------------------------------------------------------------- + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41J256M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 4, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": K7DDRPHY, # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance + + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 200e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + }, + }, + + # CSR Port ----------------------------------------------------------------- + "csr_alignment" : 32, + "csr_data_width" : 32, +} From 079af6443ef6d2ce1c51939033ce6a5e84c83234 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 8 Jul 2020 17:30:10 +1000 Subject: [PATCH 5/6] litedram: Update generator to work with latest LiteX Some changes in LiteX broke us. Adapt the build system and increase the init RAM size to 24KB. Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/dram-init-mem.vhdl | 2 +- litedram/gen-src/generate.py | 9 +++------ litedram/gen-src/sdram_init/Makefile | 16 +++++++++++++--- litedram/gen-src/sdram_init/head.S | 2 +- litedram/gen-src/sdram_init/include/system.h | 5 +++++ litedram/gen-src/sdram_init/main.c | 6 +++--- 6 files changed, 26 insertions(+), 14 deletions(-) diff --git a/litedram/gen-src/dram-init-mem.vhdl b/litedram/gen-src/dram-init-mem.vhdl index a1b87d3..395602b 100644 --- a/litedram/gen-src/dram-init-mem.vhdl +++ b/litedram/gen-src/dram-init-mem.vhdl @@ -21,7 +21,7 @@ end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; + constant INIT_RAM_SIZE : integer := 24576; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index cb6aab2..08d42fb 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -38,16 +38,14 @@ def build_init_code(build_dir, is_sim): sw_inc_dir = os.path.join(sw_dir, "include") gen_inc_dir = os.path.join(sw_inc_dir, "generated") src_dir = os.path.join(gen_src_dir, "sdram_init") - lxbios_src_dir = os.path.join(soc_directory, "software", "liblitedram") - lxbios_inc_dir = os.path.join(soc_directory, "software", "include") + lxbios_src_dir = os.path.join(soc_directory, "software") print(" sw dir:", sw_dir) print("gen_inc_dir:", gen_inc_dir) print(" src dir:", src_dir) print(" lx src dir:", lxbios_src_dir) - print(" lx inc dir:", lxbios_inc_dir) - # Generate mem.h - mem_h = "#define MAIN_RAM_BASE 0x40000000" + # Generate mem.h (hard wire size, it's not important) + mem_h = "#define MAIN_RAM_BASE 0x40000000\n#define MAIN_RAM_SIZE 0x10000000" write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h) # Environment @@ -61,7 +59,6 @@ def build_init_code(build_dir, is_sim): add_var("SRC_DIR", src_dir) add_var("GENINC_DIR", sw_inc_dir) add_var("LXSRC_DIR", lxbios_src_dir) - add_var("LXINC_DIR", lxbios_inc_dir) if is_sim: add_var("EXTRA_CFLAGS", "-D__SIM__") write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars)) diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index b28d7e4..2e622d4 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -3,8 +3,10 @@ include variables.mak OBJ = $(BUILD_DIR)/obj +LXINC_DIR=$(LXSRC_DIR)/include + PROGRAM = sdram_init -OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/console.o +OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/memtest.o $(OBJ)/console.o #### Compiler @@ -22,7 +24,13 @@ OBJCOPY = $(CROSS_COMPILE)objcopy #### Flags CPPFLAGS = -nostdinc -D__USE_LIBC $(EXTRA_CFLAGS) -CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include + +# These includes must be first ... +CPPFLAGS += -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include -I$(SRC_DIR)/libc/include + +# .. and these last, otherwise litex overrides some of our stuff +CPPFLAGS += -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(LXINC_DIR)/base -I$(LXSRC_DIR)/liblitedram + CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks ASFLAGS = $(CPPFLAGS) $(CFLAGS) @@ -48,7 +56,9 @@ endif all: objdir $(OBJ)/$(PROGRAM).hex -$(OBJ)/sdram.o: $(LXSRC_DIR)/sdram.c +$(OBJ)/sdram.o: $(LXSRC_DIR)/liblitedram/sdram.c + $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) +$(OBJ)/memtest.o: $(LXSRC_DIR)/libbase/memtest.c $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) $(OBJ)/console.o: $(SRC_DIR)/../../../lib/console.c $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) diff --git a/litedram/gen-src/sdram_init/head.S b/litedram/gen-src/sdram_init/head.S index e9d5173..2e9f053 100644 --- a/litedram/gen-src/sdram_init/head.S +++ b/litedram/gen-src/sdram_init/head.S @@ -14,7 +14,7 @@ * limitations under the License. */ -#define STACK_TOP 0xff004000 +#define STACK_TOP 0xff006000 #define FIXUP_ENDIAN \ tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h index 6d4068c..0151977 100644 --- a/litedram/gen-src/sdram_init/include/system.h +++ b/litedram/gen-src/sdram_init/include/system.h @@ -1,6 +1,8 @@ #ifndef __SYSTEM_H #define __SYSTEM_H +#include + #include "microwatt_soc.h" #include "io.h" @@ -32,6 +34,9 @@ static inline uint64_t timer0_value_read(void) return val; } +static inline void init_progression_bar(int max) { } +static inline void show_progress(int now) { } + static inline void csr_write_simple(unsigned long v, unsigned long a) { return writel(v, a); diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index 19cc2ad..9ba4fd1 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -7,10 +7,10 @@ #include +#include "console.h" #include "microwatt_soc.h" #include "io.h" #include "sdram.h" -#include "console.h" #include "elf64.h" #define FLASH_LOADER_USE_MAP @@ -225,9 +225,9 @@ dump: static void boot_sdram(void) { - void *s = (void *)(DRAM_INIT_BASE + 0x4000); + void *s = (void *)(DRAM_INIT_BASE + 0x6000); void *d = (void *)DRAM_BASE; - int sz = (0x10000 - 0x4000); + int sz = (0x10000 - 0x6000); printf("Copying payload to DRAM...\n"); memcpy(d, s, sz); printf("Booting from DRAM...\n"); From ac81bb17ac4e4ae3daa2be04def840b6ac8a9a00 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 8 Jul 2020 17:34:40 +1000 Subject: [PATCH 6/6] litedram: Regenerate This regenerate litedram for all targets (genesys2 is new in this build) using the latest LiteX. Signed-off-by: Benjamin Herrenschmidt --- litedram/generated/arty/litedram-initmem.vhdl | 2 +- litedram/generated/arty/litedram_core.init | 799 +- litedram/generated/arty/litedram_core.v | 2 +- .../generated/genesys2/litedram-initmem.vhdl | 123 + .../generated/genesys2/litedram_core.init | 2099 ++ litedram/generated/genesys2/litedram_core.v | 21234 ++++++++++++++++ .../nexys-video/litedram-initmem.vhdl | 2 +- .../generated/nexys-video/litedram_core.init | 799 +- .../generated/nexys-video/litedram_core.v | 2 +- litedram/generated/sim/litedram-initmem.vhdl | 2 +- litedram/generated/sim/litedram_core.init | 497 +- litedram/generated/sim/litedram_core.v | 2608 +- 12 files changed, 25936 insertions(+), 2233 deletions(-) create mode 100644 litedram/generated/genesys2/litedram-initmem.vhdl create mode 100644 litedram/generated/genesys2/litedram_core.init create mode 100644 litedram/generated/genesys2/litedram_core.v diff --git a/litedram/generated/arty/litedram-initmem.vhdl b/litedram/generated/arty/litedram-initmem.vhdl index a1b87d3..395602b 100644 --- a/litedram/generated/arty/litedram-initmem.vhdl +++ b/litedram/generated/arty/litedram-initmem.vhdl @@ -21,7 +21,7 @@ end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; + constant INIT_RAM_SIZE : integer := 24576; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 3604d59..0f92f5b 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -5,7 +5,7 @@ a64b5a7d14004a39 2402004ca64b7b7d 602100003c200000 6421ff00782107c6 -3d80000060213f00 +3d80000060215f00 798c07c6618c0000 618c10e0658cff00 4e8004217d8903a6 @@ -518,7 +518,7 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842a6c4 +7c0802a63842a9c4 fbe1fff8fbc1fff0 f821ff51f8010010 f88100d83be10020 @@ -527,67 +527,67 @@ f88100d83be10020 f8e100f038c100d8 f90100f87fe3fb78 f9410108f9210100 -6000000048001c19 +6000000048001e99 7fe3fb787c7e1b78 -6000000048001601 +6000000048001881 7fc3f378382100b0 -00000000480021d8 +0000000048002458 0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842a6203c4c0001 +3842a9203c4c0001 7d8000267c0802a6 -9181000848002115 -480015fdf821fed1 +9181000848002395 +4800187df821fed1 3c62ffff60000000 -4bffff3938637b98 +4bffff3938637b18 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637bb8 +63ff000838637b38 3c62ffff4bffff15 -38637bd87bff0020 +38637b587bff0020 7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffee938637bf0 +4bfffee938637b70 4e00000073e90002 3c62ffff41820010 -4bfffed138637bf8 +4bfffed138637b78 4d80000073e90004 3c62ffff41820010 -4bfffeb938637c00 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-38637cd03c62ffff +38637c503c62ffff 7c0004ac4bfffc9d 392000067f40f7aa 7d20ffaa7c0004ac @@ -644,7 +644,7 @@ f9410108f9210100 579c063e7f80feaa 738900014bfffbe1 3c62ffff4082ffdc -4bfffc1138637ce8 +4bfffc1138637c68 614a60083d40c000 7c0004ac794a0020 5529021e7d20562a @@ -652,62 +652,62 @@ f9410108f9210100 7d20572a7c0004ac 4bfffbe17f63db78 3c62ffff7bbd0020 -38637cf87fa4eb78 +38637c787fa4eb78 3be000014bfffbcd 4bfffbc17f63db78 3ca2ffff41920028 3c62ffff3c82ffff -38847d2838a57d18 -4bfffba138637d30 -6000000048000fbd +38847ca838a57c98 +4bfffba138637cb0 +6000000048000cd1 3c62ffff418e0024 -4bfffb8938637d60 +4bfffb8938637ce0 4800014438600000 3ba000003be00000 2fbf00004bffffb0 3c62ffff419e0084 -4bfffb6138637d78 +4bfffb6138637cf8 38a000403c9df000 3861007078840020 -6000000048001489 +6000000048001709 3d400002e9210070 794a83e4614a464c 614a457f79290600 419e00807fa95000 -38637d903c62ffff +38637d103c62ffff 886100774bfffb1d 8921007589410076 88e1007389010074 88a1007188c10072 f861006088810070 -38637e103c62ffff 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+000000000a2e2e2e +203a736574697257 +7370624d20646c25 +000000000000000a +20203a7364616552 +7370624d20646c25 +000000000000000a +20747365746d654d +2e70257830207461 +00000000000a2e2e +726520737562202d +2520203a73726f72 +00000a646c252f64 +652072646461202d +25203a73726f7272 +00000a646c252f64 +652061746164202d +25203a73726f7272 +00000a646c252f64 +20747365746d654d +00000000000a4f4b +20747365746d654d +00000000000a4b4f 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 460c63d..0f99197 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:02 +// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:20 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/litedram/generated/genesys2/litedram-initmem.vhdl b/litedram/generated/genesys2/litedram-initmem.vhdl new file mode 100644 index 0000000..395602b --- /dev/null +++ b/litedram/generated/genesys2/litedram-initmem.vhdl @@ -0,0 +1,123 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.utils.all; + +entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); + port ( + clk : in std_ulogic; + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out + ); +end entity dram_init_mem; + +architecture rtl of dram_init_mem is + + constant INIT_RAM_SIZE : integer := 24576; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); + constant INIT_RAM_FILE : string := "litedram_core.init"; + + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; + end function; + + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; +begin + + init_ram_0: process(clk) + variable adr : integer; + begin + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; + end process; + + wb_out.stall <= '0'; + +end architecture rtl; diff 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+00000a646c252f64 +652072646461202d +25203a73726f7272 +00000a646c252f64 +652061746164202d +25203a73726f7272 +00000a646c252f64 +20747365746d654d +00000000000a4f4b +20747365746d654d +00000000000a4b4f +0000000000000000 +00000000000000ff +000000000000ffff +0000000000ffffff +00000000ffffffff +000000ffffffffff +0000ffffffffffff +00ffffffffffffff +ffffffffffffffff +0000000000007830 +0000000000000001 diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v new file mode 100644 index 0000000..a0f6e8a --- /dev/null +++ b/litedram/generated/genesys2/litedram_core.v @@ -0,0 +1,21234 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:24 +//-------------------------------------------------------------------------------- +module litedram_core( + input wire clk, + input wire rst, + output wire pll_locked, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [3:0] ddram_dm, + inout wire [31:0] ddram_dq, + inout wire [3:0] ddram_dqs_p, + inout wire [3:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [31:0] user_port_native_0_wdata_we, + input wire [255:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [255:0] user_port_native_0_rdata_data +); + +reg [13:0] soc_litedramcore_adr = 14'd0; +reg soc_litedramcore_we = 1'd0; +wire [31:0] soc_litedramcore_dat_w; +wire [31:0] soc_litedramcore_dat_r; +wire [29:0] soc_litedramcore_wishbone_adr; +wire [31:0] soc_litedramcore_wishbone_dat_w; +wire [31:0] soc_litedramcore_wishbone_dat_r; +wire [3:0] soc_litedramcore_wishbone_sel; +wire soc_litedramcore_wishbone_cyc; +wire soc_litedramcore_wishbone_stb; +reg soc_litedramcore_wishbone_ack = 1'd0; +wire soc_litedramcore_wishbone_we; +wire [2:0] soc_litedramcore_wishbone_cti; +wire [1:0] soc_litedramcore_wishbone_bte; +reg soc_litedramcore_wishbone_err = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire soc_reset; +wire soc_locked; +wire soc_clkin; +wire soc_clkout0; +wire soc_clkout_buf0; +wire soc_clkout1; +wire soc_clkout_buf1; +wire soc_clkout2; +wire soc_clkout_buf2; +wire soc_clkout3; +wire soc_clkout_buf3; +reg [3:0] soc_reset_counter = 4'd15; +reg soc_ic_reset = 1'd1; +reg [4:0] soc_k7ddrphy_half_sys8x_taps_storage = 5'd8; +reg soc_k7ddrphy_half_sys8x_taps_re = 1'd0; +reg soc_k7ddrphy_wlevel_en_storage = 1'd0; +reg soc_k7ddrphy_wlevel_en_re = 1'd0; +wire soc_k7ddrphy_wlevel_strobe_re; +wire soc_k7ddrphy_wlevel_strobe_r; +wire soc_k7ddrphy_wlevel_strobe_we; +reg soc_k7ddrphy_wlevel_strobe_w = 1'd0; +wire soc_k7ddrphy_cdly_rst_re; +wire soc_k7ddrphy_cdly_rst_r; +wire soc_k7ddrphy_cdly_rst_we; +reg soc_k7ddrphy_cdly_rst_w = 1'd0; +wire soc_k7ddrphy_cdly_inc_re; +wire soc_k7ddrphy_cdly_inc_r; +wire soc_k7ddrphy_cdly_inc_we; +reg soc_k7ddrphy_cdly_inc_w = 1'd0; +reg [3:0] soc_k7ddrphy_dly_sel_storage = 4'd0; +reg soc_k7ddrphy_dly_sel_re = 1'd0; +wire soc_k7ddrphy_rdly_dq_rst_re; +wire soc_k7ddrphy_rdly_dq_rst_r; +wire soc_k7ddrphy_rdly_dq_rst_we; +reg soc_k7ddrphy_rdly_dq_rst_w = 1'd0; +wire soc_k7ddrphy_rdly_dq_inc_re; +wire soc_k7ddrphy_rdly_dq_inc_r; +wire soc_k7ddrphy_rdly_dq_inc_we; +reg soc_k7ddrphy_rdly_dq_inc_w = 1'd0; +wire soc_k7ddrphy_rdly_dq_bitslip_rst_re; +wire soc_k7ddrphy_rdly_dq_bitslip_rst_r; +wire soc_k7ddrphy_rdly_dq_bitslip_rst_we; +reg soc_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire soc_k7ddrphy_rdly_dq_bitslip_re; +wire soc_k7ddrphy_rdly_dq_bitslip_r; +wire soc_k7ddrphy_rdly_dq_bitslip_we; +reg soc_k7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire soc_k7ddrphy_wdly_dq_rst_re; +wire soc_k7ddrphy_wdly_dq_rst_r; +wire soc_k7ddrphy_wdly_dq_rst_we; +reg soc_k7ddrphy_wdly_dq_rst_w = 1'd0; +wire soc_k7ddrphy_wdly_dq_inc_re; +wire soc_k7ddrphy_wdly_dq_inc_r; +wire soc_k7ddrphy_wdly_dq_inc_we; +reg soc_k7ddrphy_wdly_dq_inc_w = 1'd0; +wire soc_k7ddrphy_wdly_dqs_rst_re; +wire soc_k7ddrphy_wdly_dqs_rst_r; +wire soc_k7ddrphy_wdly_dqs_rst_we; +reg soc_k7ddrphy_wdly_dqs_rst_w = 1'd0; +wire soc_k7ddrphy_wdly_dqs_inc_re; +wire soc_k7ddrphy_wdly_dqs_inc_r; +wire soc_k7ddrphy_wdly_dqs_inc_we; +reg soc_k7ddrphy_wdly_dqs_inc_w = 1'd0; +wire [14:0] soc_k7ddrphy_dfi_p0_address; +wire [2:0] soc_k7ddrphy_dfi_p0_bank; +wire soc_k7ddrphy_dfi_p0_cas_n; +wire soc_k7ddrphy_dfi_p0_cs_n; +wire soc_k7ddrphy_dfi_p0_ras_n; +wire soc_k7ddrphy_dfi_p0_we_n; +wire soc_k7ddrphy_dfi_p0_cke; +wire soc_k7ddrphy_dfi_p0_odt; +wire soc_k7ddrphy_dfi_p0_reset_n; +wire soc_k7ddrphy_dfi_p0_act_n; +wire [63:0] soc_k7ddrphy_dfi_p0_wrdata; +wire soc_k7ddrphy_dfi_p0_wrdata_en; +wire [7:0] soc_k7ddrphy_dfi_p0_wrdata_mask; +wire soc_k7ddrphy_dfi_p0_rddata_en; +reg [63:0] soc_k7ddrphy_dfi_p0_rddata = 64'd0; +reg soc_k7ddrphy_dfi_p0_rddata_valid = 1'd0; +wire [14:0] soc_k7ddrphy_dfi_p1_address; +wire [2:0] soc_k7ddrphy_dfi_p1_bank; +wire soc_k7ddrphy_dfi_p1_cas_n; +wire soc_k7ddrphy_dfi_p1_cs_n; +wire soc_k7ddrphy_dfi_p1_ras_n; +wire soc_k7ddrphy_dfi_p1_we_n; +wire soc_k7ddrphy_dfi_p1_cke; +wire soc_k7ddrphy_dfi_p1_odt; +wire soc_k7ddrphy_dfi_p1_reset_n; +wire soc_k7ddrphy_dfi_p1_act_n; +wire [63:0] soc_k7ddrphy_dfi_p1_wrdata; +wire soc_k7ddrphy_dfi_p1_wrdata_en; +wire [7:0] soc_k7ddrphy_dfi_p1_wrdata_mask; +wire soc_k7ddrphy_dfi_p1_rddata_en; +reg [63:0] soc_k7ddrphy_dfi_p1_rddata = 64'd0; +reg soc_k7ddrphy_dfi_p1_rddata_valid = 1'd0; +wire [14:0] soc_k7ddrphy_dfi_p2_address; +wire [2:0] soc_k7ddrphy_dfi_p2_bank; +wire soc_k7ddrphy_dfi_p2_cas_n; +wire soc_k7ddrphy_dfi_p2_cs_n; +wire soc_k7ddrphy_dfi_p2_ras_n; +wire soc_k7ddrphy_dfi_p2_we_n; +wire soc_k7ddrphy_dfi_p2_cke; +wire soc_k7ddrphy_dfi_p2_odt; +wire soc_k7ddrphy_dfi_p2_reset_n; +wire soc_k7ddrphy_dfi_p2_act_n; +wire [63:0] soc_k7ddrphy_dfi_p2_wrdata; +wire soc_k7ddrphy_dfi_p2_wrdata_en; +wire [7:0] soc_k7ddrphy_dfi_p2_wrdata_mask; +wire soc_k7ddrphy_dfi_p2_rddata_en; +reg [63:0] soc_k7ddrphy_dfi_p2_rddata = 64'd0; +reg soc_k7ddrphy_dfi_p2_rddata_valid = 1'd0; +wire [14:0] soc_k7ddrphy_dfi_p3_address; +wire [2:0] soc_k7ddrphy_dfi_p3_bank; +wire soc_k7ddrphy_dfi_p3_cas_n; +wire soc_k7ddrphy_dfi_p3_cs_n; +wire soc_k7ddrphy_dfi_p3_ras_n; +wire soc_k7ddrphy_dfi_p3_we_n; +wire soc_k7ddrphy_dfi_p3_cke; +wire soc_k7ddrphy_dfi_p3_odt; +wire soc_k7ddrphy_dfi_p3_reset_n; +wire soc_k7ddrphy_dfi_p3_act_n; +wire [63:0] soc_k7ddrphy_dfi_p3_wrdata; +wire soc_k7ddrphy_dfi_p3_wrdata_en; +wire [7:0] soc_k7ddrphy_dfi_p3_wrdata_mask; +wire soc_k7ddrphy_dfi_p3_rddata_en; +reg [63:0] soc_k7ddrphy_dfi_p3_rddata = 64'd0; +reg soc_k7ddrphy_dfi_p3_rddata_valid = 1'd0; +wire soc_k7ddrphy_sd_clk_se_nodelay; +wire soc_k7ddrphy_sd_clk_se_delayed; +wire soc_k7ddrphy_address0; +wire soc_k7ddrphy_address1; +wire soc_k7ddrphy_address2; +wire soc_k7ddrphy_address3; +wire soc_k7ddrphy_address4; +wire soc_k7ddrphy_address5; +wire soc_k7ddrphy_address6; +wire soc_k7ddrphy_address7; +wire soc_k7ddrphy_address8; +wire soc_k7ddrphy_address9; +wire soc_k7ddrphy_address10; +wire soc_k7ddrphy_address11; +wire soc_k7ddrphy_address12; +wire soc_k7ddrphy_address13; +wire soc_k7ddrphy_address14; +wire soc_k7ddrphy_bank0; +wire soc_k7ddrphy_bank1; +wire soc_k7ddrphy_bank2; +wire soc_k7ddrphy_cmd0; +wire soc_k7ddrphy_cmd1; +wire soc_k7ddrphy_cmd2; +wire soc_k7ddrphy_cmd3; +wire soc_k7ddrphy_cmd4; +wire soc_k7ddrphy_cmd5; +wire soc_k7ddrphy_cmd6; +reg soc_k7ddrphy_dqs_oe = 1'd0; +reg soc_k7ddrphy_dqs_oe_delayed = 1'd0; +wire soc_k7ddrphy_dqspattern0; +wire soc_k7ddrphy_dqspattern1; +reg [7:0] soc_k7ddrphy_dqspattern_o = 8'd0; +wire soc_k7ddrphy_dm_o_nodelay0; +wire soc_k7ddrphy_dm_o_nodelay1; +wire soc_k7ddrphy_dm_o_nodelay2; +wire soc_k7ddrphy_dm_o_nodelay3; +wire [3:0] soc_k7ddrphy_dqs_i; +wire [3:0] soc_k7ddrphy_dqs_i_delayed; +wire soc_k7ddrphy_dqs_o_no_delay0; +wire soc_k7ddrphy_dqs_o_delayed0; +wire soc_k7ddrphy_dqs_t0; +wire soc_k7ddrphy0; +wire soc_k7ddrphy_dqs_o_no_delay1; +wire soc_k7ddrphy_dqs_o_delayed1; +wire soc_k7ddrphy_dqs_t1; +wire soc_k7ddrphy1; +wire soc_k7ddrphy_dqs_o_no_delay2; +wire soc_k7ddrphy_dqs_o_delayed2; +wire soc_k7ddrphy_dqs_t2; +wire soc_k7ddrphy2; +wire soc_k7ddrphy_dqs_o_no_delay3; +wire soc_k7ddrphy_dqs_o_delayed3; +wire soc_k7ddrphy_dqs_t3; +wire soc_k7ddrphy3; +wire soc_k7ddrphy_dq_oe; +reg soc_k7ddrphy_dq_oe_delayed = 1'd0; +wire soc_k7ddrphy_dq_o_nodelay0; +wire soc_k7ddrphy_dq_o_delayed0; +wire soc_k7ddrphy_dq_i_nodelay0; +wire soc_k7ddrphy_dq_i_delayed0; +wire soc_k7ddrphy_dq_t0; +wire [7:0] soc_k7ddrphy_dq_i_data0; +wire [7:0] soc_k7ddrphy_bitslip0_i; +reg [7:0] soc_k7ddrphy_bitslip0_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip0_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip0_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay1; +wire soc_k7ddrphy_dq_o_delayed1; +wire soc_k7ddrphy_dq_i_nodelay1; +wire soc_k7ddrphy_dq_i_delayed1; +wire soc_k7ddrphy_dq_t1; +wire [7:0] soc_k7ddrphy_dq_i_data1; +wire [7:0] soc_k7ddrphy_bitslip1_i; +reg [7:0] soc_k7ddrphy_bitslip1_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip1_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip1_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay2; +wire soc_k7ddrphy_dq_o_delayed2; +wire soc_k7ddrphy_dq_i_nodelay2; +wire soc_k7ddrphy_dq_i_delayed2; +wire soc_k7ddrphy_dq_t2; +wire [7:0] soc_k7ddrphy_dq_i_data2; +wire [7:0] soc_k7ddrphy_bitslip2_i; +reg [7:0] soc_k7ddrphy_bitslip2_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip2_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip2_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay3; +wire soc_k7ddrphy_dq_o_delayed3; +wire soc_k7ddrphy_dq_i_nodelay3; +wire soc_k7ddrphy_dq_i_delayed3; +wire soc_k7ddrphy_dq_t3; +wire [7:0] soc_k7ddrphy_dq_i_data3; +wire [7:0] soc_k7ddrphy_bitslip3_i; +reg [7:0] soc_k7ddrphy_bitslip3_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip3_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip3_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay4; +wire soc_k7ddrphy_dq_o_delayed4; +wire soc_k7ddrphy_dq_i_nodelay4; +wire soc_k7ddrphy_dq_i_delayed4; +wire soc_k7ddrphy_dq_t4; +wire [7:0] soc_k7ddrphy_dq_i_data4; +wire [7:0] soc_k7ddrphy_bitslip4_i; +reg [7:0] soc_k7ddrphy_bitslip4_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip4_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip4_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay5; +wire soc_k7ddrphy_dq_o_delayed5; +wire soc_k7ddrphy_dq_i_nodelay5; +wire soc_k7ddrphy_dq_i_delayed5; +wire soc_k7ddrphy_dq_t5; +wire [7:0] soc_k7ddrphy_dq_i_data5; +wire [7:0] soc_k7ddrphy_bitslip5_i; +reg [7:0] soc_k7ddrphy_bitslip5_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip5_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip5_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay6; +wire soc_k7ddrphy_dq_o_delayed6; +wire soc_k7ddrphy_dq_i_nodelay6; +wire soc_k7ddrphy_dq_i_delayed6; +wire soc_k7ddrphy_dq_t6; +wire [7:0] soc_k7ddrphy_dq_i_data6; +wire [7:0] soc_k7ddrphy_bitslip6_i; +reg [7:0] soc_k7ddrphy_bitslip6_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip6_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip6_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay7; +wire soc_k7ddrphy_dq_o_delayed7; +wire soc_k7ddrphy_dq_i_nodelay7; +wire soc_k7ddrphy_dq_i_delayed7; +wire soc_k7ddrphy_dq_t7; +wire [7:0] soc_k7ddrphy_dq_i_data7; +wire [7:0] soc_k7ddrphy_bitslip7_i; +reg [7:0] soc_k7ddrphy_bitslip7_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip7_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip7_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay8; +wire soc_k7ddrphy_dq_o_delayed8; +wire soc_k7ddrphy_dq_i_nodelay8; +wire soc_k7ddrphy_dq_i_delayed8; +wire soc_k7ddrphy_dq_t8; +wire [7:0] soc_k7ddrphy_dq_i_data8; +wire [7:0] soc_k7ddrphy_bitslip8_i; +reg [7:0] soc_k7ddrphy_bitslip8_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip8_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip8_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay9; +wire soc_k7ddrphy_dq_o_delayed9; +wire soc_k7ddrphy_dq_i_nodelay9; +wire soc_k7ddrphy_dq_i_delayed9; +wire soc_k7ddrphy_dq_t9; +wire [7:0] soc_k7ddrphy_dq_i_data9; +wire [7:0] soc_k7ddrphy_bitslip9_i; +reg [7:0] soc_k7ddrphy_bitslip9_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip9_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip9_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay10; +wire soc_k7ddrphy_dq_o_delayed10; +wire soc_k7ddrphy_dq_i_nodelay10; +wire soc_k7ddrphy_dq_i_delayed10; +wire soc_k7ddrphy_dq_t10; +wire [7:0] soc_k7ddrphy_dq_i_data10; +wire [7:0] soc_k7ddrphy_bitslip10_i; +reg [7:0] soc_k7ddrphy_bitslip10_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip10_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip10_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay11; +wire soc_k7ddrphy_dq_o_delayed11; +wire soc_k7ddrphy_dq_i_nodelay11; +wire soc_k7ddrphy_dq_i_delayed11; +wire soc_k7ddrphy_dq_t11; +wire [7:0] soc_k7ddrphy_dq_i_data11; +wire [7:0] soc_k7ddrphy_bitslip11_i; +reg [7:0] soc_k7ddrphy_bitslip11_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip11_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip11_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay12; +wire soc_k7ddrphy_dq_o_delayed12; +wire soc_k7ddrphy_dq_i_nodelay12; +wire soc_k7ddrphy_dq_i_delayed12; +wire soc_k7ddrphy_dq_t12; +wire [7:0] soc_k7ddrphy_dq_i_data12; +wire [7:0] soc_k7ddrphy_bitslip12_i; +reg [7:0] soc_k7ddrphy_bitslip12_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip12_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip12_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay13; +wire soc_k7ddrphy_dq_o_delayed13; +wire soc_k7ddrphy_dq_i_nodelay13; +wire soc_k7ddrphy_dq_i_delayed13; +wire soc_k7ddrphy_dq_t13; +wire [7:0] soc_k7ddrphy_dq_i_data13; +wire [7:0] soc_k7ddrphy_bitslip13_i; +reg [7:0] soc_k7ddrphy_bitslip13_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip13_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip13_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay14; +wire soc_k7ddrphy_dq_o_delayed14; +wire soc_k7ddrphy_dq_i_nodelay14; +wire soc_k7ddrphy_dq_i_delayed14; +wire soc_k7ddrphy_dq_t14; +wire [7:0] soc_k7ddrphy_dq_i_data14; +wire [7:0] soc_k7ddrphy_bitslip14_i; +reg [7:0] soc_k7ddrphy_bitslip14_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip14_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip14_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay15; +wire soc_k7ddrphy_dq_o_delayed15; +wire soc_k7ddrphy_dq_i_nodelay15; +wire soc_k7ddrphy_dq_i_delayed15; +wire soc_k7ddrphy_dq_t15; +wire [7:0] soc_k7ddrphy_dq_i_data15; +wire [7:0] soc_k7ddrphy_bitslip15_i; +reg [7:0] soc_k7ddrphy_bitslip15_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip15_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip15_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay16; +wire soc_k7ddrphy_dq_o_delayed16; +wire soc_k7ddrphy_dq_i_nodelay16; +wire soc_k7ddrphy_dq_i_delayed16; +wire soc_k7ddrphy_dq_t16; +wire [7:0] soc_k7ddrphy_dq_i_data16; +wire [7:0] soc_k7ddrphy_bitslip16_i; +reg [7:0] soc_k7ddrphy_bitslip16_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip16_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip16_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay17; +wire soc_k7ddrphy_dq_o_delayed17; +wire soc_k7ddrphy_dq_i_nodelay17; +wire soc_k7ddrphy_dq_i_delayed17; +wire soc_k7ddrphy_dq_t17; +wire [7:0] soc_k7ddrphy_dq_i_data17; +wire [7:0] soc_k7ddrphy_bitslip17_i; +reg [7:0] soc_k7ddrphy_bitslip17_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip17_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip17_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay18; +wire soc_k7ddrphy_dq_o_delayed18; +wire soc_k7ddrphy_dq_i_nodelay18; +wire soc_k7ddrphy_dq_i_delayed18; +wire soc_k7ddrphy_dq_t18; +wire [7:0] soc_k7ddrphy_dq_i_data18; +wire [7:0] soc_k7ddrphy_bitslip18_i; +reg [7:0] soc_k7ddrphy_bitslip18_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip18_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip18_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay19; +wire soc_k7ddrphy_dq_o_delayed19; +wire soc_k7ddrphy_dq_i_nodelay19; +wire soc_k7ddrphy_dq_i_delayed19; +wire soc_k7ddrphy_dq_t19; +wire [7:0] soc_k7ddrphy_dq_i_data19; +wire [7:0] soc_k7ddrphy_bitslip19_i; +reg [7:0] soc_k7ddrphy_bitslip19_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip19_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip19_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay20; +wire soc_k7ddrphy_dq_o_delayed20; +wire soc_k7ddrphy_dq_i_nodelay20; +wire soc_k7ddrphy_dq_i_delayed20; +wire soc_k7ddrphy_dq_t20; +wire [7:0] soc_k7ddrphy_dq_i_data20; +wire [7:0] soc_k7ddrphy_bitslip20_i; +reg [7:0] soc_k7ddrphy_bitslip20_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip20_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip20_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay21; +wire soc_k7ddrphy_dq_o_delayed21; +wire soc_k7ddrphy_dq_i_nodelay21; +wire soc_k7ddrphy_dq_i_delayed21; +wire soc_k7ddrphy_dq_t21; +wire [7:0] soc_k7ddrphy_dq_i_data21; +wire [7:0] soc_k7ddrphy_bitslip21_i; +reg [7:0] soc_k7ddrphy_bitslip21_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip21_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip21_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay22; +wire soc_k7ddrphy_dq_o_delayed22; +wire soc_k7ddrphy_dq_i_nodelay22; +wire soc_k7ddrphy_dq_i_delayed22; +wire soc_k7ddrphy_dq_t22; +wire [7:0] soc_k7ddrphy_dq_i_data22; +wire [7:0] soc_k7ddrphy_bitslip22_i; +reg [7:0] soc_k7ddrphy_bitslip22_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip22_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip22_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay23; +wire soc_k7ddrphy_dq_o_delayed23; +wire soc_k7ddrphy_dq_i_nodelay23; +wire soc_k7ddrphy_dq_i_delayed23; +wire soc_k7ddrphy_dq_t23; +wire [7:0] soc_k7ddrphy_dq_i_data23; +wire [7:0] soc_k7ddrphy_bitslip23_i; +reg [7:0] soc_k7ddrphy_bitslip23_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip23_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip23_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay24; +wire soc_k7ddrphy_dq_o_delayed24; +wire soc_k7ddrphy_dq_i_nodelay24; +wire soc_k7ddrphy_dq_i_delayed24; +wire soc_k7ddrphy_dq_t24; +wire [7:0] soc_k7ddrphy_dq_i_data24; +wire [7:0] soc_k7ddrphy_bitslip24_i; +reg [7:0] soc_k7ddrphy_bitslip24_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip24_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip24_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay25; +wire soc_k7ddrphy_dq_o_delayed25; +wire soc_k7ddrphy_dq_i_nodelay25; +wire soc_k7ddrphy_dq_i_delayed25; +wire soc_k7ddrphy_dq_t25; +wire [7:0] soc_k7ddrphy_dq_i_data25; +wire [7:0] soc_k7ddrphy_bitslip25_i; +reg [7:0] soc_k7ddrphy_bitslip25_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip25_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip25_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay26; +wire soc_k7ddrphy_dq_o_delayed26; +wire soc_k7ddrphy_dq_i_nodelay26; +wire soc_k7ddrphy_dq_i_delayed26; +wire soc_k7ddrphy_dq_t26; +wire [7:0] soc_k7ddrphy_dq_i_data26; +wire [7:0] soc_k7ddrphy_bitslip26_i; +reg [7:0] soc_k7ddrphy_bitslip26_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip26_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip26_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay27; +wire soc_k7ddrphy_dq_o_delayed27; +wire soc_k7ddrphy_dq_i_nodelay27; +wire soc_k7ddrphy_dq_i_delayed27; +wire soc_k7ddrphy_dq_t27; +wire [7:0] soc_k7ddrphy_dq_i_data27; +wire [7:0] soc_k7ddrphy_bitslip27_i; +reg [7:0] soc_k7ddrphy_bitslip27_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip27_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip27_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay28; +wire soc_k7ddrphy_dq_o_delayed28; +wire soc_k7ddrphy_dq_i_nodelay28; +wire soc_k7ddrphy_dq_i_delayed28; +wire soc_k7ddrphy_dq_t28; +wire [7:0] soc_k7ddrphy_dq_i_data28; +wire [7:0] soc_k7ddrphy_bitslip28_i; +reg [7:0] soc_k7ddrphy_bitslip28_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip28_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip28_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay29; +wire soc_k7ddrphy_dq_o_delayed29; +wire soc_k7ddrphy_dq_i_nodelay29; +wire soc_k7ddrphy_dq_i_delayed29; +wire soc_k7ddrphy_dq_t29; +wire [7:0] soc_k7ddrphy_dq_i_data29; +wire [7:0] soc_k7ddrphy_bitslip29_i; +reg [7:0] soc_k7ddrphy_bitslip29_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip29_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip29_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay30; +wire soc_k7ddrphy_dq_o_delayed30; +wire soc_k7ddrphy_dq_i_nodelay30; +wire soc_k7ddrphy_dq_i_delayed30; +wire soc_k7ddrphy_dq_t30; +wire [7:0] soc_k7ddrphy_dq_i_data30; +wire [7:0] soc_k7ddrphy_bitslip30_i; +reg [7:0] soc_k7ddrphy_bitslip30_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip30_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip30_r = 24'd0; +wire soc_k7ddrphy_dq_o_nodelay31; +wire soc_k7ddrphy_dq_o_delayed31; +wire soc_k7ddrphy_dq_i_nodelay31; +wire soc_k7ddrphy_dq_i_delayed31; +wire soc_k7ddrphy_dq_t31; +wire [7:0] soc_k7ddrphy_dq_i_data31; +wire [7:0] soc_k7ddrphy_bitslip31_i; +reg [7:0] soc_k7ddrphy_bitslip31_o = 8'd0; +reg [3:0] soc_k7ddrphy_bitslip31_value = 4'd0; +reg [23:0] soc_k7ddrphy_bitslip31_r = 24'd0; +wire [7:0] soc_k7ddrphy_rddata_en; +reg [7:0] soc_k7ddrphy_rddata_en_last = 8'd0; +wire [3:0] soc_k7ddrphy_wrdata_en; +reg [3:0] soc_k7ddrphy_wrdata_en_last = 4'd0; +wire [14:0] soc_litedramcore_inti_p0_address; +wire [2:0] soc_litedramcore_inti_p0_bank; +reg soc_litedramcore_inti_p0_cas_n = 1'd1; +reg soc_litedramcore_inti_p0_cs_n = 1'd1; +reg soc_litedramcore_inti_p0_ras_n = 1'd1; +reg soc_litedramcore_inti_p0_we_n = 1'd1; +wire soc_litedramcore_inti_p0_cke; +wire soc_litedramcore_inti_p0_odt; +wire soc_litedramcore_inti_p0_reset_n; +reg soc_litedramcore_inti_p0_act_n = 1'd1; +wire [63:0] soc_litedramcore_inti_p0_wrdata; +wire soc_litedramcore_inti_p0_wrdata_en; +wire [7:0] soc_litedramcore_inti_p0_wrdata_mask; +wire soc_litedramcore_inti_p0_rddata_en; +reg [63:0] soc_litedramcore_inti_p0_rddata = 64'd0; +reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; +wire [14:0] soc_litedramcore_inti_p1_address; +wire [2:0] soc_litedramcore_inti_p1_bank; +reg soc_litedramcore_inti_p1_cas_n = 1'd1; +reg soc_litedramcore_inti_p1_cs_n = 1'd1; +reg soc_litedramcore_inti_p1_ras_n = 1'd1; +reg soc_litedramcore_inti_p1_we_n = 1'd1; +wire soc_litedramcore_inti_p1_cke; +wire soc_litedramcore_inti_p1_odt; +wire soc_litedramcore_inti_p1_reset_n; +reg soc_litedramcore_inti_p1_act_n = 1'd1; +wire [63:0] soc_litedramcore_inti_p1_wrdata; +wire soc_litedramcore_inti_p1_wrdata_en; +wire [7:0] soc_litedramcore_inti_p1_wrdata_mask; +wire soc_litedramcore_inti_p1_rddata_en; +reg [63:0] soc_litedramcore_inti_p1_rddata = 64'd0; +reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; +wire [14:0] soc_litedramcore_inti_p2_address; +wire [2:0] soc_litedramcore_inti_p2_bank; +reg soc_litedramcore_inti_p2_cas_n = 1'd1; +reg soc_litedramcore_inti_p2_cs_n = 1'd1; +reg soc_litedramcore_inti_p2_ras_n = 1'd1; +reg soc_litedramcore_inti_p2_we_n = 1'd1; +wire soc_litedramcore_inti_p2_cke; +wire soc_litedramcore_inti_p2_odt; +wire soc_litedramcore_inti_p2_reset_n; +reg soc_litedramcore_inti_p2_act_n = 1'd1; +wire [63:0] soc_litedramcore_inti_p2_wrdata; +wire soc_litedramcore_inti_p2_wrdata_en; +wire [7:0] soc_litedramcore_inti_p2_wrdata_mask; +wire soc_litedramcore_inti_p2_rddata_en; +reg [63:0] soc_litedramcore_inti_p2_rddata = 64'd0; +reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; +wire [14:0] soc_litedramcore_inti_p3_address; +wire [2:0] soc_litedramcore_inti_p3_bank; +reg soc_litedramcore_inti_p3_cas_n = 1'd1; +reg soc_litedramcore_inti_p3_cs_n = 1'd1; +reg soc_litedramcore_inti_p3_ras_n = 1'd1; +reg soc_litedramcore_inti_p3_we_n = 1'd1; +wire soc_litedramcore_inti_p3_cke; +wire soc_litedramcore_inti_p3_odt; +wire soc_litedramcore_inti_p3_reset_n; +reg soc_litedramcore_inti_p3_act_n = 1'd1; +wire [63:0] soc_litedramcore_inti_p3_wrdata; +wire soc_litedramcore_inti_p3_wrdata_en; +wire [7:0] soc_litedramcore_inti_p3_wrdata_mask; +wire soc_litedramcore_inti_p3_rddata_en; +reg [63:0] soc_litedramcore_inti_p3_rddata = 64'd0; +reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; +wire [14:0] soc_litedramcore_slave_p0_address; +wire [2:0] soc_litedramcore_slave_p0_bank; +wire soc_litedramcore_slave_p0_cas_n; +wire soc_litedramcore_slave_p0_cs_n; +wire soc_litedramcore_slave_p0_ras_n; +wire soc_litedramcore_slave_p0_we_n; +wire soc_litedramcore_slave_p0_cke; +wire soc_litedramcore_slave_p0_odt; +wire soc_litedramcore_slave_p0_reset_n; +wire soc_litedramcore_slave_p0_act_n; +wire [63:0] soc_litedramcore_slave_p0_wrdata; +wire soc_litedramcore_slave_p0_wrdata_en; +wire [7:0] soc_litedramcore_slave_p0_wrdata_mask; +wire soc_litedramcore_slave_p0_rddata_en; +reg [63:0] soc_litedramcore_slave_p0_rddata = 64'd0; +reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] soc_litedramcore_slave_p1_address; +wire [2:0] soc_litedramcore_slave_p1_bank; +wire soc_litedramcore_slave_p1_cas_n; +wire soc_litedramcore_slave_p1_cs_n; +wire soc_litedramcore_slave_p1_ras_n; +wire soc_litedramcore_slave_p1_we_n; +wire soc_litedramcore_slave_p1_cke; +wire soc_litedramcore_slave_p1_odt; +wire soc_litedramcore_slave_p1_reset_n; +wire soc_litedramcore_slave_p1_act_n; +wire [63:0] soc_litedramcore_slave_p1_wrdata; +wire soc_litedramcore_slave_p1_wrdata_en; +wire [7:0] soc_litedramcore_slave_p1_wrdata_mask; +wire soc_litedramcore_slave_p1_rddata_en; +reg [63:0] soc_litedramcore_slave_p1_rddata = 64'd0; +reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [14:0] soc_litedramcore_slave_p2_address; +wire [2:0] soc_litedramcore_slave_p2_bank; +wire soc_litedramcore_slave_p2_cas_n; +wire soc_litedramcore_slave_p2_cs_n; +wire soc_litedramcore_slave_p2_ras_n; +wire soc_litedramcore_slave_p2_we_n; +wire soc_litedramcore_slave_p2_cke; +wire soc_litedramcore_slave_p2_odt; +wire soc_litedramcore_slave_p2_reset_n; +wire soc_litedramcore_slave_p2_act_n; +wire [63:0] soc_litedramcore_slave_p2_wrdata; +wire soc_litedramcore_slave_p2_wrdata_en; +wire [7:0] soc_litedramcore_slave_p2_wrdata_mask; +wire soc_litedramcore_slave_p2_rddata_en; +reg [63:0] soc_litedramcore_slave_p2_rddata = 64'd0; +reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [14:0] soc_litedramcore_slave_p3_address; +wire [2:0] soc_litedramcore_slave_p3_bank; +wire soc_litedramcore_slave_p3_cas_n; +wire soc_litedramcore_slave_p3_cs_n; +wire soc_litedramcore_slave_p3_ras_n; +wire soc_litedramcore_slave_p3_we_n; +wire soc_litedramcore_slave_p3_cke; +wire soc_litedramcore_slave_p3_odt; +wire soc_litedramcore_slave_p3_reset_n; +wire soc_litedramcore_slave_p3_act_n; +wire [63:0] soc_litedramcore_slave_p3_wrdata; +wire soc_litedramcore_slave_p3_wrdata_en; +wire [7:0] soc_litedramcore_slave_p3_wrdata_mask; +wire soc_litedramcore_slave_p3_rddata_en; +reg [63:0] soc_litedramcore_slave_p3_rddata = 64'd0; +reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] soc_litedramcore_master_p0_address = 15'd0; +reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; +reg soc_litedramcore_master_p0_cas_n = 1'd1; +reg soc_litedramcore_master_p0_cs_n = 1'd1; +reg soc_litedramcore_master_p0_ras_n = 1'd1; +reg soc_litedramcore_master_p0_we_n = 1'd1; +reg soc_litedramcore_master_p0_cke = 1'd0; +reg soc_litedramcore_master_p0_odt = 1'd0; +reg soc_litedramcore_master_p0_reset_n = 1'd0; +reg soc_litedramcore_master_p0_act_n = 1'd1; +reg [63:0] soc_litedramcore_master_p0_wrdata = 64'd0; +reg soc_litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] soc_litedramcore_master_p0_wrdata_mask = 8'd0; +reg soc_litedramcore_master_p0_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_master_p0_rddata; +wire soc_litedramcore_master_p0_rddata_valid; +reg [14:0] soc_litedramcore_master_p1_address = 15'd0; +reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; +reg soc_litedramcore_master_p1_cas_n = 1'd1; +reg soc_litedramcore_master_p1_cs_n = 1'd1; +reg soc_litedramcore_master_p1_ras_n = 1'd1; +reg soc_litedramcore_master_p1_we_n = 1'd1; +reg soc_litedramcore_master_p1_cke = 1'd0; +reg soc_litedramcore_master_p1_odt = 1'd0; +reg soc_litedramcore_master_p1_reset_n = 1'd0; +reg soc_litedramcore_master_p1_act_n = 1'd1; +reg [63:0] soc_litedramcore_master_p1_wrdata = 64'd0; +reg soc_litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] soc_litedramcore_master_p1_wrdata_mask = 8'd0; +reg soc_litedramcore_master_p1_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_master_p1_rddata; +wire soc_litedramcore_master_p1_rddata_valid; +reg [14:0] soc_litedramcore_master_p2_address = 15'd0; +reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; +reg soc_litedramcore_master_p2_cas_n = 1'd1; +reg soc_litedramcore_master_p2_cs_n = 1'd1; +reg soc_litedramcore_master_p2_ras_n = 1'd1; +reg soc_litedramcore_master_p2_we_n = 1'd1; +reg soc_litedramcore_master_p2_cke = 1'd0; +reg soc_litedramcore_master_p2_odt = 1'd0; +reg soc_litedramcore_master_p2_reset_n = 1'd0; +reg soc_litedramcore_master_p2_act_n = 1'd1; +reg [63:0] soc_litedramcore_master_p2_wrdata = 64'd0; +reg soc_litedramcore_master_p2_wrdata_en = 1'd0; +reg [7:0] soc_litedramcore_master_p2_wrdata_mask = 8'd0; +reg soc_litedramcore_master_p2_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_master_p2_rddata; +wire soc_litedramcore_master_p2_rddata_valid; +reg [14:0] soc_litedramcore_master_p3_address = 15'd0; +reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; +reg soc_litedramcore_master_p3_cas_n = 1'd1; +reg soc_litedramcore_master_p3_cs_n = 1'd1; +reg soc_litedramcore_master_p3_ras_n = 1'd1; +reg soc_litedramcore_master_p3_we_n = 1'd1; +reg soc_litedramcore_master_p3_cke = 1'd0; +reg soc_litedramcore_master_p3_odt = 1'd0; +reg soc_litedramcore_master_p3_reset_n = 1'd0; +reg soc_litedramcore_master_p3_act_n = 1'd1; +reg [63:0] soc_litedramcore_master_p3_wrdata = 64'd0; +reg soc_litedramcore_master_p3_wrdata_en = 1'd0; +reg [7:0] soc_litedramcore_master_p3_wrdata_mask = 8'd0; +reg soc_litedramcore_master_p3_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_master_p3_rddata; +wire soc_litedramcore_master_p3_rddata_valid; +wire soc_litedramcore_sel; +wire soc_litedramcore_cke; +wire soc_litedramcore_odt; +wire soc_litedramcore_reset_n; +reg [3:0] soc_litedramcore_storage = 4'd1; +reg soc_litedramcore_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector0_command_re = 1'd0; +wire soc_litedramcore_phaseinjector0_command_issue_re; +wire soc_litedramcore_phaseinjector0_command_issue_r; +wire soc_litedramcore_phaseinjector0_command_issue_we; +reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] soc_litedramcore_phaseinjector0_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector0_status = 64'd0; +wire soc_litedramcore_phaseinjector0_we; +reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector1_command_re = 1'd0; +wire soc_litedramcore_phaseinjector1_command_issue_re; +wire soc_litedramcore_phaseinjector1_command_issue_r; +wire soc_litedramcore_phaseinjector1_command_issue_we; +reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] soc_litedramcore_phaseinjector1_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector1_status = 64'd0; +wire soc_litedramcore_phaseinjector1_we; +reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector2_command_re = 1'd0; +wire soc_litedramcore_phaseinjector2_command_issue_re; +wire soc_litedramcore_phaseinjector2_command_issue_r; +wire soc_litedramcore_phaseinjector2_command_issue_we; +reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] soc_litedramcore_phaseinjector2_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector2_wrdata_storage = 64'd0; +reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector2_status = 64'd0; +wire soc_litedramcore_phaseinjector2_we; +reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector3_command_re = 1'd0; +wire soc_litedramcore_phaseinjector3_command_issue_re; +wire soc_litedramcore_phaseinjector3_command_issue_r; +wire soc_litedramcore_phaseinjector3_command_issue_we; +reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] soc_litedramcore_phaseinjector3_address_storage = 15'd0; +reg soc_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector3_wrdata_storage = 64'd0; +reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [63:0] soc_litedramcore_phaseinjector3_status = 64'd0; +wire soc_litedramcore_phaseinjector3_we; +wire soc_litedramcore_interface_bank0_valid; +wire soc_litedramcore_interface_bank0_ready; +wire soc_litedramcore_interface_bank0_we; +wire [21:0] soc_litedramcore_interface_bank0_addr; +wire soc_litedramcore_interface_bank0_lock; +wire soc_litedramcore_interface_bank0_wdata_ready; +wire soc_litedramcore_interface_bank0_rdata_valid; +wire soc_litedramcore_interface_bank1_valid; +wire soc_litedramcore_interface_bank1_ready; +wire soc_litedramcore_interface_bank1_we; +wire [21:0] soc_litedramcore_interface_bank1_addr; +wire soc_litedramcore_interface_bank1_lock; +wire soc_litedramcore_interface_bank1_wdata_ready; +wire soc_litedramcore_interface_bank1_rdata_valid; +wire soc_litedramcore_interface_bank2_valid; +wire soc_litedramcore_interface_bank2_ready; +wire soc_litedramcore_interface_bank2_we; +wire [21:0] soc_litedramcore_interface_bank2_addr; +wire soc_litedramcore_interface_bank2_lock; +wire soc_litedramcore_interface_bank2_wdata_ready; +wire soc_litedramcore_interface_bank2_rdata_valid; +wire soc_litedramcore_interface_bank3_valid; +wire soc_litedramcore_interface_bank3_ready; +wire soc_litedramcore_interface_bank3_we; +wire [21:0] soc_litedramcore_interface_bank3_addr; +wire soc_litedramcore_interface_bank3_lock; +wire soc_litedramcore_interface_bank3_wdata_ready; +wire soc_litedramcore_interface_bank3_rdata_valid; +wire soc_litedramcore_interface_bank4_valid; +wire soc_litedramcore_interface_bank4_ready; +wire soc_litedramcore_interface_bank4_we; +wire [21:0] soc_litedramcore_interface_bank4_addr; +wire soc_litedramcore_interface_bank4_lock; +wire soc_litedramcore_interface_bank4_wdata_ready; +wire soc_litedramcore_interface_bank4_rdata_valid; +wire soc_litedramcore_interface_bank5_valid; +wire soc_litedramcore_interface_bank5_ready; +wire soc_litedramcore_interface_bank5_we; +wire [21:0] soc_litedramcore_interface_bank5_addr; +wire soc_litedramcore_interface_bank5_lock; +wire soc_litedramcore_interface_bank5_wdata_ready; +wire soc_litedramcore_interface_bank5_rdata_valid; +wire soc_litedramcore_interface_bank6_valid; +wire soc_litedramcore_interface_bank6_ready; +wire soc_litedramcore_interface_bank6_we; +wire [21:0] soc_litedramcore_interface_bank6_addr; +wire soc_litedramcore_interface_bank6_lock; +wire soc_litedramcore_interface_bank6_wdata_ready; +wire soc_litedramcore_interface_bank6_rdata_valid; +wire soc_litedramcore_interface_bank7_valid; +wire soc_litedramcore_interface_bank7_ready; +wire soc_litedramcore_interface_bank7_we; +wire [21:0] soc_litedramcore_interface_bank7_addr; +wire soc_litedramcore_interface_bank7_lock; +wire soc_litedramcore_interface_bank7_wdata_ready; +wire soc_litedramcore_interface_bank7_rdata_valid; +reg [255:0] soc_litedramcore_interface_wdata = 256'd0; +reg [31:0] soc_litedramcore_interface_wdata_we = 32'd0; +wire [255:0] soc_litedramcore_interface_rdata; +reg [14:0] soc_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; +reg soc_litedramcore_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_dfi_p0_ras_n = 1'd1; +reg soc_litedramcore_dfi_p0_we_n = 1'd1; +wire soc_litedramcore_dfi_p0_cke; +wire soc_litedramcore_dfi_p0_odt; +wire soc_litedramcore_dfi_p0_reset_n; +reg soc_litedramcore_dfi_p0_act_n = 1'd1; +wire [63:0] soc_litedramcore_dfi_p0_wrdata; +reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] soc_litedramcore_dfi_p0_wrdata_mask; +reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_dfi_p0_rddata; +wire soc_litedramcore_dfi_p0_rddata_valid; +reg [14:0] soc_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; +reg soc_litedramcore_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_dfi_p1_ras_n = 1'd1; +reg soc_litedramcore_dfi_p1_we_n = 1'd1; +wire soc_litedramcore_dfi_p1_cke; +wire soc_litedramcore_dfi_p1_odt; +wire soc_litedramcore_dfi_p1_reset_n; +reg soc_litedramcore_dfi_p1_act_n = 1'd1; +wire [63:0] soc_litedramcore_dfi_p1_wrdata; +reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] soc_litedramcore_dfi_p1_wrdata_mask; +reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_dfi_p1_rddata; +wire soc_litedramcore_dfi_p1_rddata_valid; +reg [14:0] soc_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; +reg soc_litedramcore_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_dfi_p2_ras_n = 1'd1; +reg soc_litedramcore_dfi_p2_we_n = 1'd1; +wire soc_litedramcore_dfi_p2_cke; +wire soc_litedramcore_dfi_p2_odt; +wire soc_litedramcore_dfi_p2_reset_n; +reg soc_litedramcore_dfi_p2_act_n = 1'd1; +wire [63:0] soc_litedramcore_dfi_p2_wrdata; +reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [7:0] soc_litedramcore_dfi_p2_wrdata_mask; +reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_dfi_p2_rddata; +wire soc_litedramcore_dfi_p2_rddata_valid; +reg [14:0] soc_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; +reg soc_litedramcore_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_dfi_p3_ras_n = 1'd1; +reg soc_litedramcore_dfi_p3_we_n = 1'd1; +wire soc_litedramcore_dfi_p3_cke; +wire soc_litedramcore_dfi_p3_odt; +wire soc_litedramcore_dfi_p3_reset_n; +reg soc_litedramcore_dfi_p3_act_n = 1'd1; +wire [63:0] soc_litedramcore_dfi_p3_wrdata; +reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [7:0] soc_litedramcore_dfi_p3_wrdata_mask; +reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [63:0] soc_litedramcore_dfi_p3_rddata; +wire soc_litedramcore_dfi_p3_rddata_valid; +reg soc_litedramcore_cmd_valid = 1'd0; +reg soc_litedramcore_cmd_ready = 1'd0; +reg soc_litedramcore_cmd_last = 1'd0; +reg [14:0] soc_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; +reg soc_litedramcore_cmd_payload_cas = 1'd0; +reg soc_litedramcore_cmd_payload_ras = 1'd0; +reg soc_litedramcore_cmd_payload_we = 1'd0; +reg soc_litedramcore_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_cmd_payload_is_write = 1'd0; +wire soc_litedramcore_wants_refresh; +wire soc_litedramcore_wants_zqcs; +wire soc_litedramcore_timer_wait; +wire soc_litedramcore_timer_done0; +wire [9:0] soc_litedramcore_timer_count0; +wire soc_litedramcore_timer_done1; +reg [9:0] soc_litedramcore_timer_count1 = 10'd781; +wire soc_litedramcore_postponer_req_i; +reg soc_litedramcore_postponer_req_o = 1'd0; +reg soc_litedramcore_postponer_count = 1'd0; +reg soc_litedramcore_sequencer_start0 = 1'd0; +wire soc_litedramcore_sequencer_done0; +wire soc_litedramcore_sequencer_start1; +reg soc_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; +reg soc_litedramcore_sequencer_count = 1'd0; +wire soc_litedramcore_zqcs_timer_wait; +wire soc_litedramcore_zqcs_timer_done0; +wire [26:0] soc_litedramcore_zqcs_timer_count0; +wire soc_litedramcore_zqcs_timer_done1; +reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg soc_litedramcore_zqcs_executer_start = 1'd0; +reg soc_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; +wire soc_litedramcore_bankmachine0_req_valid; +wire soc_litedramcore_bankmachine0_req_ready; +wire soc_litedramcore_bankmachine0_req_we; +wire [21:0] soc_litedramcore_bankmachine0_req_addr; +wire soc_litedramcore_bankmachine0_req_lock; +reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine0_refresh_req; +reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; +reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine0_row = 15'd0; +reg soc_litedramcore_bankmachine0_row_opened = 1'd0; +wire soc_litedramcore_bankmachine0_row_hit; +reg soc_litedramcore_bankmachine0_row_open = 1'd0; +reg soc_litedramcore_bankmachine0_row_close = 1'd0; +reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine1_req_valid; +wire soc_litedramcore_bankmachine1_req_ready; +wire soc_litedramcore_bankmachine1_req_we; +wire [21:0] soc_litedramcore_bankmachine1_req_addr; +wire soc_litedramcore_bankmachine1_req_lock; +reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine1_refresh_req; +reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; +reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine1_row = 15'd0; +reg soc_litedramcore_bankmachine1_row_opened = 1'd0; +wire soc_litedramcore_bankmachine1_row_hit; +reg soc_litedramcore_bankmachine1_row_open = 1'd0; +reg soc_litedramcore_bankmachine1_row_close = 1'd0; +reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine2_req_valid; +wire soc_litedramcore_bankmachine2_req_ready; +wire soc_litedramcore_bankmachine2_req_we; +wire [21:0] soc_litedramcore_bankmachine2_req_addr; +wire soc_litedramcore_bankmachine2_req_lock; +reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine2_refresh_req; +reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; +reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine2_row = 15'd0; +reg soc_litedramcore_bankmachine2_row_opened = 1'd0; +wire soc_litedramcore_bankmachine2_row_hit; +reg soc_litedramcore_bankmachine2_row_open = 1'd0; +reg soc_litedramcore_bankmachine2_row_close = 1'd0; +reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine3_req_valid; +wire soc_litedramcore_bankmachine3_req_ready; +wire soc_litedramcore_bankmachine3_req_we; +wire [21:0] soc_litedramcore_bankmachine3_req_addr; +wire soc_litedramcore_bankmachine3_req_lock; +reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine3_refresh_req; +reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; +reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine3_row = 15'd0; +reg soc_litedramcore_bankmachine3_row_opened = 1'd0; +wire soc_litedramcore_bankmachine3_row_hit; +reg soc_litedramcore_bankmachine3_row_open = 1'd0; +reg soc_litedramcore_bankmachine3_row_close = 1'd0; +reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine4_req_valid; +wire soc_litedramcore_bankmachine4_req_ready; +wire soc_litedramcore_bankmachine4_req_we; +wire [21:0] soc_litedramcore_bankmachine4_req_addr; +wire soc_litedramcore_bankmachine4_req_lock; +reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine4_refresh_req; +reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; +reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine4_row = 15'd0; +reg soc_litedramcore_bankmachine4_row_opened = 1'd0; +wire soc_litedramcore_bankmachine4_row_hit; +reg soc_litedramcore_bankmachine4_row_open = 1'd0; +reg soc_litedramcore_bankmachine4_row_close = 1'd0; +reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine5_req_valid; +wire soc_litedramcore_bankmachine5_req_ready; +wire soc_litedramcore_bankmachine5_req_we; +wire [21:0] soc_litedramcore_bankmachine5_req_addr; +wire soc_litedramcore_bankmachine5_req_lock; +reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine5_refresh_req; +reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; +reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine5_row = 15'd0; +reg soc_litedramcore_bankmachine5_row_opened = 1'd0; +wire soc_litedramcore_bankmachine5_row_hit; +reg soc_litedramcore_bankmachine5_row_open = 1'd0; +reg soc_litedramcore_bankmachine5_row_close = 1'd0; +reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine6_req_valid; +wire soc_litedramcore_bankmachine6_req_ready; +wire soc_litedramcore_bankmachine6_req_we; +wire [21:0] soc_litedramcore_bankmachine6_req_addr; +wire soc_litedramcore_bankmachine6_req_lock; +reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine6_refresh_req; +reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; +reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine6_row = 15'd0; +reg soc_litedramcore_bankmachine6_row_opened = 1'd0; +wire soc_litedramcore_bankmachine6_row_hit; +reg soc_litedramcore_bankmachine6_row_open = 1'd0; +reg soc_litedramcore_bankmachine6_row_close = 1'd0; +reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine7_req_valid; +wire soc_litedramcore_bankmachine7_req_ready; +wire soc_litedramcore_bankmachine7_req_we; +wire [21:0] soc_litedramcore_bankmachine7_req_addr; +wire soc_litedramcore_bankmachine7_req_lock; +reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine7_refresh_req; +reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] soc_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; +reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_litedramcore_bankmachine7_row = 15'd0; +reg soc_litedramcore_bankmachine7_row_opened = 1'd0; +wire soc_litedramcore_bankmachine7_row_hit; +reg soc_litedramcore_bankmachine7_row_open = 1'd0; +reg soc_litedramcore_bankmachine7_row_close = 1'd0; +reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; +wire soc_litedramcore_ras_allowed; +wire soc_litedramcore_cas_allowed; +reg soc_litedramcore_choose_cmd_want_reads = 1'd0; +reg soc_litedramcore_choose_cmd_want_writes = 1'd0; +reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; +reg soc_litedramcore_choose_cmd_want_activates = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_valid; +reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] soc_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; +reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire soc_litedramcore_choose_cmd_cmd_payload_is_read; +wire soc_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_cmd_request; +reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; +wire soc_litedramcore_choose_cmd_ce; +reg soc_litedramcore_choose_req_want_reads = 1'd0; +reg soc_litedramcore_choose_req_want_writes = 1'd0; +reg soc_litedramcore_choose_req_want_cmds = 1'd0; +reg soc_litedramcore_choose_req_want_activates = 1'd0; +wire soc_litedramcore_choose_req_cmd_valid; +reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] soc_litedramcore_choose_req_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; +reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_req_cmd_payload_is_cmd; +wire soc_litedramcore_choose_req_cmd_payload_is_read; +wire soc_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_req_request; +reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; +wire soc_litedramcore_choose_req_ce; +reg [14:0] soc_litedramcore_nop_a = 15'd0; +reg [2:0] soc_litedramcore_nop_ba = 3'd0; +reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; +reg soc_litedramcore_steerer0 = 1'd1; +reg soc_litedramcore_steerer1 = 1'd1; +reg soc_litedramcore_steerer2 = 1'd1; +reg soc_litedramcore_steerer3 = 1'd1; +reg soc_litedramcore_steerer4 = 1'd1; +reg soc_litedramcore_steerer5 = 1'd1; +reg soc_litedramcore_steerer6 = 1'd1; +reg soc_litedramcore_steerer7 = 1'd1; +wire soc_litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0; +reg soc_litedramcore_trrdcon_count = 1'd0; +wire soc_litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] soc_litedramcore_tfawcon_count; +reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; +wire soc_litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0; +reg soc_litedramcore_tccdcon_count = 1'd0; +wire soc_litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; +wire soc_litedramcore_read_available; +wire soc_litedramcore_write_available; +reg soc_litedramcore_en0 = 1'd0; +wire soc_litedramcore_max_time0; +reg [4:0] soc_litedramcore_time0 = 5'd0; +reg soc_litedramcore_en1 = 1'd0; +wire soc_litedramcore_max_time1; +reg [3:0] soc_litedramcore_time1 = 4'd0; +wire soc_litedramcore_go_to_refresh; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_re = 1'd0; +wire [29:0] soc_wb_bus_adr; +wire [31:0] soc_wb_bus_dat_w; +wire [31:0] soc_wb_bus_dat_r; +wire [3:0] soc_wb_bus_sel; +wire soc_wb_bus_cyc; +wire soc_wb_bus_stb; +wire soc_wb_bus_ack; +wire soc_wb_bus_we; +wire [2:0] soc_wb_bus_cti; +wire [1:0] soc_wb_bus_bte; +wire soc_wb_bus_err; +wire soc_user_port_cmd_valid; +wire soc_user_port_cmd_ready; +wire soc_user_port_cmd_payload_we; +wire [24:0] soc_user_port_cmd_payload_addr; +wire soc_user_port_wdata_valid; +wire soc_user_port_wdata_ready; +wire [255:0] soc_user_port_wdata_payload_data; +wire [31:0] soc_user_port_wdata_payload_we; +wire soc_user_port_rdata_valid; +wire soc_user_port_rdata_ready; +wire [255:0] soc_user_port_rdata_payload_data; +reg vns_state = 1'd0; +reg vns_next_state = 1'd0; +wire vns_pll_fb; +reg [1:0] vns_refresher_state = 2'd0; +reg [1:0] vns_refresher_next_state = 2'd0; +reg [3:0] vns_bankmachine0_state = 4'd0; +reg [3:0] vns_bankmachine0_next_state = 4'd0; +reg [3:0] vns_bankmachine1_state = 4'd0; +reg [3:0] vns_bankmachine1_next_state = 4'd0; +reg [3:0] vns_bankmachine2_state = 4'd0; +reg [3:0] vns_bankmachine2_next_state = 4'd0; +reg [3:0] vns_bankmachine3_state = 4'd0; +reg [3:0] vns_bankmachine3_next_state = 4'd0; +reg [3:0] vns_bankmachine4_state = 4'd0; +reg [3:0] vns_bankmachine4_next_state = 4'd0; +reg [3:0] vns_bankmachine5_state = 4'd0; +reg [3:0] vns_bankmachine5_next_state = 4'd0; +reg [3:0] vns_bankmachine6_state = 4'd0; +reg [3:0] vns_bankmachine6_next_state = 4'd0; +reg [3:0] vns_bankmachine7_state = 4'd0; +reg [3:0] vns_bankmachine7_next_state = 4'd0; +reg [3:0] vns_multiplexer_state = 4'd0; +reg [3:0] vns_multiplexer_next_state = 4'd0; +wire vns_roundrobin0_request; +wire vns_roundrobin0_grant; +wire vns_roundrobin0_ce; +wire vns_roundrobin1_request; +wire vns_roundrobin1_grant; +wire vns_roundrobin1_ce; +wire vns_roundrobin2_request; +wire vns_roundrobin2_grant; +wire vns_roundrobin2_ce; +wire vns_roundrobin3_request; +wire vns_roundrobin3_grant; +wire vns_roundrobin3_ce; +wire vns_roundrobin4_request; +wire vns_roundrobin4_grant; +wire vns_roundrobin4_ce; +wire vns_roundrobin5_request; +wire vns_roundrobin5_grant; +wire vns_roundrobin5_ce; +wire vns_roundrobin6_request; +wire vns_roundrobin6_grant; +wire vns_roundrobin6_ce; +wire vns_roundrobin7_request; +wire vns_roundrobin7_grant; +wire vns_roundrobin7_ce; +reg vns_locked0 = 1'd0; +reg vns_locked1 = 1'd0; +reg vns_locked2 = 1'd0; +reg vns_locked3 = 1'd0; +reg vns_locked4 = 1'd0; +reg vns_locked5 = 1'd0; +reg vns_locked6 = 1'd0; +reg vns_locked7 = 1'd0; +reg vns_new_master_wdata_ready0 = 1'd0; +reg vns_new_master_wdata_ready1 = 1'd0; +reg vns_new_master_wdata_ready2 = 1'd0; +reg vns_new_master_rdata_valid0 = 1'd0; +reg vns_new_master_rdata_valid1 = 1'd0; +reg vns_new_master_rdata_valid2 = 1'd0; +reg vns_new_master_rdata_valid3 = 1'd0; +reg vns_new_master_rdata_valid4 = 1'd0; +reg vns_new_master_rdata_valid5 = 1'd0; +reg vns_new_master_rdata_valid6 = 1'd0; +reg vns_new_master_rdata_valid7 = 1'd0; +reg vns_new_master_rdata_valid8 = 1'd0; +wire [13:0] vns_interface0_bank_bus_adr; +wire vns_interface0_bank_bus_we; +wire [31:0] vns_interface0_bank_bus_dat_w; +reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0; +wire vns_csrbank0_init_done0_re; +wire vns_csrbank0_init_done0_r; +wire vns_csrbank0_init_done0_we; +wire vns_csrbank0_init_done0_w; +wire vns_csrbank0_init_error0_re; +wire vns_csrbank0_init_error0_r; +wire vns_csrbank0_init_error0_we; +wire vns_csrbank0_init_error0_w; +wire vns_csrbank0_sel; +wire [13:0] vns_interface1_bank_bus_adr; +wire vns_interface1_bank_bus_we; +wire [31:0] vns_interface1_bank_bus_dat_w; +reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0; +wire vns_csrbank1_half_sys8x_taps0_re; +wire [4:0] vns_csrbank1_half_sys8x_taps0_r; +wire vns_csrbank1_half_sys8x_taps0_we; +wire [4:0] vns_csrbank1_half_sys8x_taps0_w; +wire vns_csrbank1_wlevel_en0_re; +wire vns_csrbank1_wlevel_en0_r; +wire vns_csrbank1_wlevel_en0_we; +wire vns_csrbank1_wlevel_en0_w; +wire vns_csrbank1_dly_sel0_re; +wire [3:0] vns_csrbank1_dly_sel0_r; +wire vns_csrbank1_dly_sel0_we; +wire [3:0] vns_csrbank1_dly_sel0_w; +wire vns_csrbank1_sel; +wire [13:0] vns_interface2_bank_bus_adr; +wire vns_interface2_bank_bus_we; +wire [31:0] vns_interface2_bank_bus_dat_w; +reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0; +wire vns_csrbank2_dfii_control0_re; +wire [3:0] vns_csrbank2_dfii_control0_r; +wire vns_csrbank2_dfii_control0_we; +wire [3:0] vns_csrbank2_dfii_control0_w; +wire vns_csrbank2_dfii_pi0_command0_re; +wire [5:0] vns_csrbank2_dfii_pi0_command0_r; +wire vns_csrbank2_dfii_pi0_command0_we; +wire [5:0] vns_csrbank2_dfii_pi0_command0_w; +wire vns_csrbank2_dfii_pi0_address0_re; +wire [14:0] vns_csrbank2_dfii_pi0_address0_r; +wire vns_csrbank2_dfii_pi0_address0_we; +wire [14:0] vns_csrbank2_dfii_pi0_address0_w; +wire vns_csrbank2_dfii_pi0_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r; +wire vns_csrbank2_dfii_pi0_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w; +wire vns_csrbank2_dfii_pi0_wrdata1_re; +wire [31:0] vns_csrbank2_dfii_pi0_wrdata1_r; +wire vns_csrbank2_dfii_pi0_wrdata1_we; +wire [31:0] vns_csrbank2_dfii_pi0_wrdata1_w; +wire vns_csrbank2_dfii_pi0_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r; +wire vns_csrbank2_dfii_pi0_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w; +wire vns_csrbank2_dfii_pi0_rddata1_re; +wire [31:0] vns_csrbank2_dfii_pi0_rddata1_r; +wire vns_csrbank2_dfii_pi0_rddata1_we; +wire [31:0] vns_csrbank2_dfii_pi0_rddata1_w; +wire vns_csrbank2_dfii_pi0_rddata0_re; +wire [31:0] vns_csrbank2_dfii_pi0_rddata0_r; +wire vns_csrbank2_dfii_pi0_rddata0_we; +wire [31:0] vns_csrbank2_dfii_pi0_rddata0_w; +wire vns_csrbank2_dfii_pi1_command0_re; +wire [5:0] vns_csrbank2_dfii_pi1_command0_r; +wire vns_csrbank2_dfii_pi1_command0_we; +wire [5:0] vns_csrbank2_dfii_pi1_command0_w; +wire vns_csrbank2_dfii_pi1_address0_re; +wire [14:0] vns_csrbank2_dfii_pi1_address0_r; +wire vns_csrbank2_dfii_pi1_address0_we; +wire [14:0] vns_csrbank2_dfii_pi1_address0_w; +wire vns_csrbank2_dfii_pi1_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r; +wire vns_csrbank2_dfii_pi1_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w; +wire vns_csrbank2_dfii_pi1_wrdata1_re; +wire [31:0] vns_csrbank2_dfii_pi1_wrdata1_r; +wire vns_csrbank2_dfii_pi1_wrdata1_we; +wire [31:0] vns_csrbank2_dfii_pi1_wrdata1_w; +wire vns_csrbank2_dfii_pi1_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r; +wire vns_csrbank2_dfii_pi1_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w; +wire vns_csrbank2_dfii_pi1_rddata1_re; +wire [31:0] vns_csrbank2_dfii_pi1_rddata1_r; +wire vns_csrbank2_dfii_pi1_rddata1_we; +wire [31:0] vns_csrbank2_dfii_pi1_rddata1_w; +wire vns_csrbank2_dfii_pi1_rddata0_re; +wire [31:0] vns_csrbank2_dfii_pi1_rddata0_r; +wire vns_csrbank2_dfii_pi1_rddata0_we; +wire [31:0] vns_csrbank2_dfii_pi1_rddata0_w; +wire vns_csrbank2_dfii_pi2_command0_re; +wire [5:0] vns_csrbank2_dfii_pi2_command0_r; +wire vns_csrbank2_dfii_pi2_command0_we; +wire [5:0] vns_csrbank2_dfii_pi2_command0_w; +wire vns_csrbank2_dfii_pi2_address0_re; +wire [14:0] vns_csrbank2_dfii_pi2_address0_r; +wire vns_csrbank2_dfii_pi2_address0_we; +wire [14:0] vns_csrbank2_dfii_pi2_address0_w; +wire vns_csrbank2_dfii_pi2_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r; +wire vns_csrbank2_dfii_pi2_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w; +wire vns_csrbank2_dfii_pi2_wrdata1_re; +wire [31:0] vns_csrbank2_dfii_pi2_wrdata1_r; +wire vns_csrbank2_dfii_pi2_wrdata1_we; +wire [31:0] vns_csrbank2_dfii_pi2_wrdata1_w; +wire vns_csrbank2_dfii_pi2_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r; +wire vns_csrbank2_dfii_pi2_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w; +wire vns_csrbank2_dfii_pi2_rddata1_re; +wire [31:0] vns_csrbank2_dfii_pi2_rddata1_r; +wire vns_csrbank2_dfii_pi2_rddata1_we; +wire [31:0] vns_csrbank2_dfii_pi2_rddata1_w; +wire vns_csrbank2_dfii_pi2_rddata0_re; +wire [31:0] vns_csrbank2_dfii_pi2_rddata0_r; +wire vns_csrbank2_dfii_pi2_rddata0_we; +wire [31:0] vns_csrbank2_dfii_pi2_rddata0_w; +wire vns_csrbank2_dfii_pi3_command0_re; +wire [5:0] vns_csrbank2_dfii_pi3_command0_r; +wire vns_csrbank2_dfii_pi3_command0_we; +wire [5:0] vns_csrbank2_dfii_pi3_command0_w; +wire vns_csrbank2_dfii_pi3_address0_re; +wire [14:0] vns_csrbank2_dfii_pi3_address0_r; +wire vns_csrbank2_dfii_pi3_address0_we; +wire [14:0] vns_csrbank2_dfii_pi3_address0_w; +wire vns_csrbank2_dfii_pi3_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r; +wire vns_csrbank2_dfii_pi3_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w; +wire vns_csrbank2_dfii_pi3_wrdata1_re; +wire [31:0] vns_csrbank2_dfii_pi3_wrdata1_r; +wire vns_csrbank2_dfii_pi3_wrdata1_we; +wire [31:0] vns_csrbank2_dfii_pi3_wrdata1_w; +wire vns_csrbank2_dfii_pi3_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r; +wire vns_csrbank2_dfii_pi3_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w; +wire vns_csrbank2_dfii_pi3_rddata1_re; +wire [31:0] vns_csrbank2_dfii_pi3_rddata1_r; +wire vns_csrbank2_dfii_pi3_rddata1_we; +wire [31:0] vns_csrbank2_dfii_pi3_rddata1_w; +wire vns_csrbank2_dfii_pi3_rddata0_re; +wire [31:0] vns_csrbank2_dfii_pi3_rddata0_r; +wire vns_csrbank2_dfii_pi3_rddata0_we; +wire [31:0] vns_csrbank2_dfii_pi3_rddata0_w; +wire vns_csrbank2_sel; +wire [13:0] vns_adr; +wire vns_we; +wire [31:0] vns_dat_w; +wire [31:0] vns_dat_r; +reg vns_rhs_array_muxed0 = 1'd0; +reg [14:0] vns_rhs_array_muxed1 = 15'd0; +reg [2:0] vns_rhs_array_muxed2 = 3'd0; +reg vns_rhs_array_muxed3 = 1'd0; +reg vns_rhs_array_muxed4 = 1'd0; +reg vns_rhs_array_muxed5 = 1'd0; +reg vns_t_array_muxed0 = 1'd0; +reg vns_t_array_muxed1 = 1'd0; +reg vns_t_array_muxed2 = 1'd0; +reg vns_rhs_array_muxed6 = 1'd0; +reg [14:0] vns_rhs_array_muxed7 = 15'd0; +reg [2:0] vns_rhs_array_muxed8 = 3'd0; +reg vns_rhs_array_muxed9 = 1'd0; +reg vns_rhs_array_muxed10 = 1'd0; +reg vns_rhs_array_muxed11 = 1'd0; +reg vns_t_array_muxed3 = 1'd0; +reg vns_t_array_muxed4 = 1'd0; +reg vns_t_array_muxed5 = 1'd0; +reg [21:0] vns_rhs_array_muxed12 = 22'd0; +reg vns_rhs_array_muxed13 = 1'd0; +reg vns_rhs_array_muxed14 = 1'd0; +reg [21:0] vns_rhs_array_muxed15 = 22'd0; +reg vns_rhs_array_muxed16 = 1'd0; +reg vns_rhs_array_muxed17 = 1'd0; +reg [21:0] vns_rhs_array_muxed18 = 22'd0; +reg vns_rhs_array_muxed19 = 1'd0; +reg vns_rhs_array_muxed20 = 1'd0; +reg [21:0] vns_rhs_array_muxed21 = 22'd0; +reg vns_rhs_array_muxed22 = 1'd0; +reg vns_rhs_array_muxed23 = 1'd0; +reg [21:0] vns_rhs_array_muxed24 = 22'd0; +reg vns_rhs_array_muxed25 = 1'd0; +reg vns_rhs_array_muxed26 = 1'd0; +reg [21:0] vns_rhs_array_muxed27 = 22'd0; +reg vns_rhs_array_muxed28 = 1'd0; +reg vns_rhs_array_muxed29 = 1'd0; +reg [21:0] vns_rhs_array_muxed30 = 22'd0; +reg vns_rhs_array_muxed31 = 1'd0; +reg vns_rhs_array_muxed32 = 1'd0; +reg [21:0] vns_rhs_array_muxed33 = 22'd0; +reg vns_rhs_array_muxed34 = 1'd0; +reg vns_rhs_array_muxed35 = 1'd0; +reg [2:0] vns_array_muxed0 = 3'd0; +reg [14:0] vns_array_muxed1 = 15'd0; +reg vns_array_muxed2 = 1'd0; +reg vns_array_muxed3 = 1'd0; +reg vns_array_muxed4 = 1'd0; +reg vns_array_muxed5 = 1'd0; +reg vns_array_muxed6 = 1'd0; +reg [2:0] vns_array_muxed7 = 3'd0; +reg [14:0] vns_array_muxed8 = 15'd0; +reg vns_array_muxed9 = 1'd0; +reg vns_array_muxed10 = 1'd0; +reg vns_array_muxed11 = 1'd0; +reg vns_array_muxed12 = 1'd0; +reg vns_array_muxed13 = 1'd0; +reg [2:0] vns_array_muxed14 = 3'd0; +reg [14:0] vns_array_muxed15 = 15'd0; +reg vns_array_muxed16 = 1'd0; +reg vns_array_muxed17 = 1'd0; +reg vns_array_muxed18 = 1'd0; +reg vns_array_muxed19 = 1'd0; +reg vns_array_muxed20 = 1'd0; +reg [2:0] vns_array_muxed21 = 3'd0; +reg [14:0] vns_array_muxed22 = 15'd0; +reg vns_array_muxed23 = 1'd0; +reg vns_array_muxed24 = 1'd0; +reg vns_array_muxed25 = 1'd0; +reg vns_array_muxed26 = 1'd0; +reg vns_array_muxed27 = 1'd0; +wire vns_xilinxasyncresetsynchronizerimpl0; +wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl1; +wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl2; +wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl2_expr; +wire vns_xilinxasyncresetsynchronizerimpl3; +wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl3_expr; + +// synthesis translate_off +reg dummy_s; +initial dummy_s <= 1'd0; +// synthesis translate_on +assign init_done = soc_init_done_storage; +assign init_error = soc_init_error_storage; +assign soc_wb_bus_adr = wb_ctrl_adr; +assign soc_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = soc_wb_bus_dat_r; +assign soc_wb_bus_sel = wb_ctrl_sel; +assign soc_wb_bus_cyc = wb_ctrl_cyc; +assign soc_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = soc_wb_bus_ack; +assign soc_wb_bus_we = wb_ctrl_we; +assign soc_wb_bus_cti = wb_ctrl_cti; +assign soc_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = soc_wb_bus_err; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; +assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; +assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; +assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; +assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w; +assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + vns_next_state <= 1'd0; + vns_next_state <= vns_state; + case (vns_state) + 1'd1: begin + vns_next_state <= 1'd0; + end + default: begin + if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin + vns_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + soc_litedramcore_adr <= 14'd0; + case (vns_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin + soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + soc_litedramcore_we <= 1'd0; + case (vns_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin + soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + soc_litedramcore_wishbone_ack <= 1'd0; + case (vns_state) + 1'd1: begin + soc_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end +assign soc_reset = rst; +assign pll_locked = soc_locked; +assign soc_clkin = clk; +assign iodelay_clk = soc_clkout_buf0; +assign sys_clk = soc_clkout_buf1; +assign sys4x_clk = soc_clkout_buf2; +assign sys4x_dqs_clk = soc_clkout_buf3; +assign soc_k7ddrphy_bitslip0_i = soc_k7ddrphy_dq_i_data0; + +// synthesis translate_off +reg dummy_d_4; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_dfi_p0_rddata <= 64'd0; + soc_k7ddrphy_dfi_p0_rddata[0] <= soc_k7ddrphy_bitslip0_o[0]; + soc_k7ddrphy_dfi_p0_rddata[32] <= soc_k7ddrphy_bitslip0_o[1]; + soc_k7ddrphy_dfi_p0_rddata[1] <= soc_k7ddrphy_bitslip1_o[0]; + soc_k7ddrphy_dfi_p0_rddata[33] <= soc_k7ddrphy_bitslip1_o[1]; + soc_k7ddrphy_dfi_p0_rddata[2] <= soc_k7ddrphy_bitslip2_o[0]; + soc_k7ddrphy_dfi_p0_rddata[34] <= soc_k7ddrphy_bitslip2_o[1]; + soc_k7ddrphy_dfi_p0_rddata[3] <= soc_k7ddrphy_bitslip3_o[0]; + soc_k7ddrphy_dfi_p0_rddata[35] <= soc_k7ddrphy_bitslip3_o[1]; + soc_k7ddrphy_dfi_p0_rddata[4] <= soc_k7ddrphy_bitslip4_o[0]; + soc_k7ddrphy_dfi_p0_rddata[36] <= soc_k7ddrphy_bitslip4_o[1]; + soc_k7ddrphy_dfi_p0_rddata[5] <= soc_k7ddrphy_bitslip5_o[0]; + soc_k7ddrphy_dfi_p0_rddata[37] <= soc_k7ddrphy_bitslip5_o[1]; + soc_k7ddrphy_dfi_p0_rddata[6] <= soc_k7ddrphy_bitslip6_o[0]; + soc_k7ddrphy_dfi_p0_rddata[38] <= soc_k7ddrphy_bitslip6_o[1]; + soc_k7ddrphy_dfi_p0_rddata[7] <= soc_k7ddrphy_bitslip7_o[0]; + soc_k7ddrphy_dfi_p0_rddata[39] <= soc_k7ddrphy_bitslip7_o[1]; + soc_k7ddrphy_dfi_p0_rddata[8] <= soc_k7ddrphy_bitslip8_o[0]; + soc_k7ddrphy_dfi_p0_rddata[40] <= soc_k7ddrphy_bitslip8_o[1]; + soc_k7ddrphy_dfi_p0_rddata[9] <= soc_k7ddrphy_bitslip9_o[0]; + soc_k7ddrphy_dfi_p0_rddata[41] <= soc_k7ddrphy_bitslip9_o[1]; + soc_k7ddrphy_dfi_p0_rddata[10] <= soc_k7ddrphy_bitslip10_o[0]; + soc_k7ddrphy_dfi_p0_rddata[42] <= soc_k7ddrphy_bitslip10_o[1]; + soc_k7ddrphy_dfi_p0_rddata[11] <= soc_k7ddrphy_bitslip11_o[0]; + soc_k7ddrphy_dfi_p0_rddata[43] <= soc_k7ddrphy_bitslip11_o[1]; + soc_k7ddrphy_dfi_p0_rddata[12] <= soc_k7ddrphy_bitslip12_o[0]; + soc_k7ddrphy_dfi_p0_rddata[44] <= soc_k7ddrphy_bitslip12_o[1]; + soc_k7ddrphy_dfi_p0_rddata[13] <= soc_k7ddrphy_bitslip13_o[0]; + soc_k7ddrphy_dfi_p0_rddata[45] <= soc_k7ddrphy_bitslip13_o[1]; + soc_k7ddrphy_dfi_p0_rddata[14] <= soc_k7ddrphy_bitslip14_o[0]; + soc_k7ddrphy_dfi_p0_rddata[46] <= soc_k7ddrphy_bitslip14_o[1]; + soc_k7ddrphy_dfi_p0_rddata[15] <= soc_k7ddrphy_bitslip15_o[0]; + soc_k7ddrphy_dfi_p0_rddata[47] <= soc_k7ddrphy_bitslip15_o[1]; + soc_k7ddrphy_dfi_p0_rddata[16] <= soc_k7ddrphy_bitslip16_o[0]; + soc_k7ddrphy_dfi_p0_rddata[48] <= soc_k7ddrphy_bitslip16_o[1]; + soc_k7ddrphy_dfi_p0_rddata[17] <= soc_k7ddrphy_bitslip17_o[0]; + soc_k7ddrphy_dfi_p0_rddata[49] <= soc_k7ddrphy_bitslip17_o[1]; + soc_k7ddrphy_dfi_p0_rddata[18] <= soc_k7ddrphy_bitslip18_o[0]; + soc_k7ddrphy_dfi_p0_rddata[50] <= soc_k7ddrphy_bitslip18_o[1]; + soc_k7ddrphy_dfi_p0_rddata[19] <= soc_k7ddrphy_bitslip19_o[0]; + soc_k7ddrphy_dfi_p0_rddata[51] <= soc_k7ddrphy_bitslip19_o[1]; + soc_k7ddrphy_dfi_p0_rddata[20] <= soc_k7ddrphy_bitslip20_o[0]; + soc_k7ddrphy_dfi_p0_rddata[52] <= soc_k7ddrphy_bitslip20_o[1]; + soc_k7ddrphy_dfi_p0_rddata[21] <= soc_k7ddrphy_bitslip21_o[0]; + soc_k7ddrphy_dfi_p0_rddata[53] <= soc_k7ddrphy_bitslip21_o[1]; + soc_k7ddrphy_dfi_p0_rddata[22] <= soc_k7ddrphy_bitslip22_o[0]; + soc_k7ddrphy_dfi_p0_rddata[54] <= soc_k7ddrphy_bitslip22_o[1]; + soc_k7ddrphy_dfi_p0_rddata[23] <= soc_k7ddrphy_bitslip23_o[0]; + soc_k7ddrphy_dfi_p0_rddata[55] <= soc_k7ddrphy_bitslip23_o[1]; + soc_k7ddrphy_dfi_p0_rddata[24] <= soc_k7ddrphy_bitslip24_o[0]; + soc_k7ddrphy_dfi_p0_rddata[56] <= soc_k7ddrphy_bitslip24_o[1]; + soc_k7ddrphy_dfi_p0_rddata[25] <= soc_k7ddrphy_bitslip25_o[0]; + soc_k7ddrphy_dfi_p0_rddata[57] <= soc_k7ddrphy_bitslip25_o[1]; + soc_k7ddrphy_dfi_p0_rddata[26] <= soc_k7ddrphy_bitslip26_o[0]; + soc_k7ddrphy_dfi_p0_rddata[58] <= soc_k7ddrphy_bitslip26_o[1]; + soc_k7ddrphy_dfi_p0_rddata[27] <= soc_k7ddrphy_bitslip27_o[0]; + soc_k7ddrphy_dfi_p0_rddata[59] <= soc_k7ddrphy_bitslip27_o[1]; + soc_k7ddrphy_dfi_p0_rddata[28] <= soc_k7ddrphy_bitslip28_o[0]; + soc_k7ddrphy_dfi_p0_rddata[60] <= soc_k7ddrphy_bitslip28_o[1]; + soc_k7ddrphy_dfi_p0_rddata[29] <= soc_k7ddrphy_bitslip29_o[0]; + soc_k7ddrphy_dfi_p0_rddata[61] <= soc_k7ddrphy_bitslip29_o[1]; + soc_k7ddrphy_dfi_p0_rddata[30] <= soc_k7ddrphy_bitslip30_o[0]; + soc_k7ddrphy_dfi_p0_rddata[62] <= soc_k7ddrphy_bitslip30_o[1]; + soc_k7ddrphy_dfi_p0_rddata[31] <= soc_k7ddrphy_bitslip31_o[0]; + soc_k7ddrphy_dfi_p0_rddata[63] <= soc_k7ddrphy_bitslip31_o[1]; +// synthesis translate_off + dummy_d_4 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_5; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_dfi_p1_rddata <= 64'd0; + soc_k7ddrphy_dfi_p1_rddata[0] <= soc_k7ddrphy_bitslip0_o[2]; + soc_k7ddrphy_dfi_p1_rddata[32] <= soc_k7ddrphy_bitslip0_o[3]; + soc_k7ddrphy_dfi_p1_rddata[1] <= soc_k7ddrphy_bitslip1_o[2]; + soc_k7ddrphy_dfi_p1_rddata[33] <= soc_k7ddrphy_bitslip1_o[3]; + soc_k7ddrphy_dfi_p1_rddata[2] <= soc_k7ddrphy_bitslip2_o[2]; + soc_k7ddrphy_dfi_p1_rddata[34] <= soc_k7ddrphy_bitslip2_o[3]; + soc_k7ddrphy_dfi_p1_rddata[3] <= soc_k7ddrphy_bitslip3_o[2]; + soc_k7ddrphy_dfi_p1_rddata[35] <= soc_k7ddrphy_bitslip3_o[3]; + soc_k7ddrphy_dfi_p1_rddata[4] <= soc_k7ddrphy_bitslip4_o[2]; + soc_k7ddrphy_dfi_p1_rddata[36] <= soc_k7ddrphy_bitslip4_o[3]; + soc_k7ddrphy_dfi_p1_rddata[5] <= soc_k7ddrphy_bitslip5_o[2]; + soc_k7ddrphy_dfi_p1_rddata[37] <= soc_k7ddrphy_bitslip5_o[3]; + soc_k7ddrphy_dfi_p1_rddata[6] <= soc_k7ddrphy_bitslip6_o[2]; + soc_k7ddrphy_dfi_p1_rddata[38] <= soc_k7ddrphy_bitslip6_o[3]; + soc_k7ddrphy_dfi_p1_rddata[7] <= soc_k7ddrphy_bitslip7_o[2]; + soc_k7ddrphy_dfi_p1_rddata[39] <= soc_k7ddrphy_bitslip7_o[3]; + soc_k7ddrphy_dfi_p1_rddata[8] <= soc_k7ddrphy_bitslip8_o[2]; + soc_k7ddrphy_dfi_p1_rddata[40] <= soc_k7ddrphy_bitslip8_o[3]; + soc_k7ddrphy_dfi_p1_rddata[9] <= soc_k7ddrphy_bitslip9_o[2]; + soc_k7ddrphy_dfi_p1_rddata[41] <= soc_k7ddrphy_bitslip9_o[3]; + soc_k7ddrphy_dfi_p1_rddata[10] <= soc_k7ddrphy_bitslip10_o[2]; + soc_k7ddrphy_dfi_p1_rddata[42] <= soc_k7ddrphy_bitslip10_o[3]; + soc_k7ddrphy_dfi_p1_rddata[11] <= soc_k7ddrphy_bitslip11_o[2]; + soc_k7ddrphy_dfi_p1_rddata[43] <= soc_k7ddrphy_bitslip11_o[3]; + soc_k7ddrphy_dfi_p1_rddata[12] <= soc_k7ddrphy_bitslip12_o[2]; + soc_k7ddrphy_dfi_p1_rddata[44] <= soc_k7ddrphy_bitslip12_o[3]; + soc_k7ddrphy_dfi_p1_rddata[13] <= soc_k7ddrphy_bitslip13_o[2]; + soc_k7ddrphy_dfi_p1_rddata[45] <= soc_k7ddrphy_bitslip13_o[3]; + soc_k7ddrphy_dfi_p1_rddata[14] <= soc_k7ddrphy_bitslip14_o[2]; + soc_k7ddrphy_dfi_p1_rddata[46] <= soc_k7ddrphy_bitslip14_o[3]; + soc_k7ddrphy_dfi_p1_rddata[15] <= soc_k7ddrphy_bitslip15_o[2]; + soc_k7ddrphy_dfi_p1_rddata[47] <= soc_k7ddrphy_bitslip15_o[3]; + soc_k7ddrphy_dfi_p1_rddata[16] <= soc_k7ddrphy_bitslip16_o[2]; + soc_k7ddrphy_dfi_p1_rddata[48] <= soc_k7ddrphy_bitslip16_o[3]; + soc_k7ddrphy_dfi_p1_rddata[17] <= soc_k7ddrphy_bitslip17_o[2]; + soc_k7ddrphy_dfi_p1_rddata[49] <= soc_k7ddrphy_bitslip17_o[3]; + soc_k7ddrphy_dfi_p1_rddata[18] <= soc_k7ddrphy_bitslip18_o[2]; + soc_k7ddrphy_dfi_p1_rddata[50] <= soc_k7ddrphy_bitslip18_o[3]; + soc_k7ddrphy_dfi_p1_rddata[19] <= soc_k7ddrphy_bitslip19_o[2]; + soc_k7ddrphy_dfi_p1_rddata[51] <= soc_k7ddrphy_bitslip19_o[3]; + soc_k7ddrphy_dfi_p1_rddata[20] <= soc_k7ddrphy_bitslip20_o[2]; + soc_k7ddrphy_dfi_p1_rddata[52] <= soc_k7ddrphy_bitslip20_o[3]; + soc_k7ddrphy_dfi_p1_rddata[21] <= soc_k7ddrphy_bitslip21_o[2]; + soc_k7ddrphy_dfi_p1_rddata[53] <= soc_k7ddrphy_bitslip21_o[3]; + soc_k7ddrphy_dfi_p1_rddata[22] <= soc_k7ddrphy_bitslip22_o[2]; + soc_k7ddrphy_dfi_p1_rddata[54] <= soc_k7ddrphy_bitslip22_o[3]; + soc_k7ddrphy_dfi_p1_rddata[23] <= soc_k7ddrphy_bitslip23_o[2]; + soc_k7ddrphy_dfi_p1_rddata[55] <= soc_k7ddrphy_bitslip23_o[3]; + soc_k7ddrphy_dfi_p1_rddata[24] <= soc_k7ddrphy_bitslip24_o[2]; + soc_k7ddrphy_dfi_p1_rddata[56] <= soc_k7ddrphy_bitslip24_o[3]; + soc_k7ddrphy_dfi_p1_rddata[25] <= soc_k7ddrphy_bitslip25_o[2]; + soc_k7ddrphy_dfi_p1_rddata[57] <= soc_k7ddrphy_bitslip25_o[3]; + soc_k7ddrphy_dfi_p1_rddata[26] <= soc_k7ddrphy_bitslip26_o[2]; + soc_k7ddrphy_dfi_p1_rddata[58] <= soc_k7ddrphy_bitslip26_o[3]; + soc_k7ddrphy_dfi_p1_rddata[27] <= soc_k7ddrphy_bitslip27_o[2]; + soc_k7ddrphy_dfi_p1_rddata[59] <= soc_k7ddrphy_bitslip27_o[3]; + soc_k7ddrphy_dfi_p1_rddata[28] <= soc_k7ddrphy_bitslip28_o[2]; + soc_k7ddrphy_dfi_p1_rddata[60] <= soc_k7ddrphy_bitslip28_o[3]; + soc_k7ddrphy_dfi_p1_rddata[29] <= soc_k7ddrphy_bitslip29_o[2]; + soc_k7ddrphy_dfi_p1_rddata[61] <= soc_k7ddrphy_bitslip29_o[3]; + soc_k7ddrphy_dfi_p1_rddata[30] <= soc_k7ddrphy_bitslip30_o[2]; + soc_k7ddrphy_dfi_p1_rddata[62] <= soc_k7ddrphy_bitslip30_o[3]; + soc_k7ddrphy_dfi_p1_rddata[31] <= soc_k7ddrphy_bitslip31_o[2]; + soc_k7ddrphy_dfi_p1_rddata[63] <= soc_k7ddrphy_bitslip31_o[3]; +// synthesis translate_off + dummy_d_5 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_6; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_dfi_p2_rddata <= 64'd0; + soc_k7ddrphy_dfi_p2_rddata[0] <= soc_k7ddrphy_bitslip0_o[4]; + soc_k7ddrphy_dfi_p2_rddata[32] <= soc_k7ddrphy_bitslip0_o[5]; + soc_k7ddrphy_dfi_p2_rddata[1] <= soc_k7ddrphy_bitslip1_o[4]; + soc_k7ddrphy_dfi_p2_rddata[33] <= soc_k7ddrphy_bitslip1_o[5]; + soc_k7ddrphy_dfi_p2_rddata[2] <= soc_k7ddrphy_bitslip2_o[4]; + soc_k7ddrphy_dfi_p2_rddata[34] <= soc_k7ddrphy_bitslip2_o[5]; + soc_k7ddrphy_dfi_p2_rddata[3] <= soc_k7ddrphy_bitslip3_o[4]; + soc_k7ddrphy_dfi_p2_rddata[35] <= soc_k7ddrphy_bitslip3_o[5]; + soc_k7ddrphy_dfi_p2_rddata[4] <= soc_k7ddrphy_bitslip4_o[4]; + soc_k7ddrphy_dfi_p2_rddata[36] <= soc_k7ddrphy_bitslip4_o[5]; + soc_k7ddrphy_dfi_p2_rddata[5] <= soc_k7ddrphy_bitslip5_o[4]; + soc_k7ddrphy_dfi_p2_rddata[37] <= soc_k7ddrphy_bitslip5_o[5]; + soc_k7ddrphy_dfi_p2_rddata[6] <= soc_k7ddrphy_bitslip6_o[4]; + soc_k7ddrphy_dfi_p2_rddata[38] <= soc_k7ddrphy_bitslip6_o[5]; + soc_k7ddrphy_dfi_p2_rddata[7] <= soc_k7ddrphy_bitslip7_o[4]; + soc_k7ddrphy_dfi_p2_rddata[39] <= soc_k7ddrphy_bitslip7_o[5]; + soc_k7ddrphy_dfi_p2_rddata[8] <= soc_k7ddrphy_bitslip8_o[4]; + soc_k7ddrphy_dfi_p2_rddata[40] <= soc_k7ddrphy_bitslip8_o[5]; + soc_k7ddrphy_dfi_p2_rddata[9] <= soc_k7ddrphy_bitslip9_o[4]; + soc_k7ddrphy_dfi_p2_rddata[41] <= soc_k7ddrphy_bitslip9_o[5]; + soc_k7ddrphy_dfi_p2_rddata[10] <= soc_k7ddrphy_bitslip10_o[4]; + soc_k7ddrphy_dfi_p2_rddata[42] <= soc_k7ddrphy_bitslip10_o[5]; + soc_k7ddrphy_dfi_p2_rddata[11] <= soc_k7ddrphy_bitslip11_o[4]; + soc_k7ddrphy_dfi_p2_rddata[43] <= soc_k7ddrphy_bitslip11_o[5]; + soc_k7ddrphy_dfi_p2_rddata[12] <= soc_k7ddrphy_bitslip12_o[4]; + soc_k7ddrphy_dfi_p2_rddata[44] <= soc_k7ddrphy_bitslip12_o[5]; + soc_k7ddrphy_dfi_p2_rddata[13] <= soc_k7ddrphy_bitslip13_o[4]; + soc_k7ddrphy_dfi_p2_rddata[45] <= soc_k7ddrphy_bitslip13_o[5]; + soc_k7ddrphy_dfi_p2_rddata[14] <= soc_k7ddrphy_bitslip14_o[4]; + soc_k7ddrphy_dfi_p2_rddata[46] <= soc_k7ddrphy_bitslip14_o[5]; + soc_k7ddrphy_dfi_p2_rddata[15] <= soc_k7ddrphy_bitslip15_o[4]; + soc_k7ddrphy_dfi_p2_rddata[47] <= soc_k7ddrphy_bitslip15_o[5]; + soc_k7ddrphy_dfi_p2_rddata[16] <= soc_k7ddrphy_bitslip16_o[4]; + soc_k7ddrphy_dfi_p2_rddata[48] <= soc_k7ddrphy_bitslip16_o[5]; + soc_k7ddrphy_dfi_p2_rddata[17] <= soc_k7ddrphy_bitslip17_o[4]; + soc_k7ddrphy_dfi_p2_rddata[49] <= soc_k7ddrphy_bitslip17_o[5]; + soc_k7ddrphy_dfi_p2_rddata[18] <= soc_k7ddrphy_bitslip18_o[4]; + soc_k7ddrphy_dfi_p2_rddata[50] <= soc_k7ddrphy_bitslip18_o[5]; + soc_k7ddrphy_dfi_p2_rddata[19] <= soc_k7ddrphy_bitslip19_o[4]; + soc_k7ddrphy_dfi_p2_rddata[51] <= soc_k7ddrphy_bitslip19_o[5]; + soc_k7ddrphy_dfi_p2_rddata[20] <= soc_k7ddrphy_bitslip20_o[4]; + soc_k7ddrphy_dfi_p2_rddata[52] <= soc_k7ddrphy_bitslip20_o[5]; + soc_k7ddrphy_dfi_p2_rddata[21] <= soc_k7ddrphy_bitslip21_o[4]; + soc_k7ddrphy_dfi_p2_rddata[53] <= soc_k7ddrphy_bitslip21_o[5]; + soc_k7ddrphy_dfi_p2_rddata[22] <= soc_k7ddrphy_bitslip22_o[4]; + soc_k7ddrphy_dfi_p2_rddata[54] <= soc_k7ddrphy_bitslip22_o[5]; + soc_k7ddrphy_dfi_p2_rddata[23] <= soc_k7ddrphy_bitslip23_o[4]; + soc_k7ddrphy_dfi_p2_rddata[55] <= soc_k7ddrphy_bitslip23_o[5]; + soc_k7ddrphy_dfi_p2_rddata[24] <= soc_k7ddrphy_bitslip24_o[4]; + soc_k7ddrphy_dfi_p2_rddata[56] <= soc_k7ddrphy_bitslip24_o[5]; + soc_k7ddrphy_dfi_p2_rddata[25] <= soc_k7ddrphy_bitslip25_o[4]; + soc_k7ddrphy_dfi_p2_rddata[57] <= soc_k7ddrphy_bitslip25_o[5]; + soc_k7ddrphy_dfi_p2_rddata[26] <= soc_k7ddrphy_bitslip26_o[4]; + soc_k7ddrphy_dfi_p2_rddata[58] <= soc_k7ddrphy_bitslip26_o[5]; + soc_k7ddrphy_dfi_p2_rddata[27] <= soc_k7ddrphy_bitslip27_o[4]; + soc_k7ddrphy_dfi_p2_rddata[59] <= soc_k7ddrphy_bitslip27_o[5]; + soc_k7ddrphy_dfi_p2_rddata[28] <= soc_k7ddrphy_bitslip28_o[4]; + soc_k7ddrphy_dfi_p2_rddata[60] <= soc_k7ddrphy_bitslip28_o[5]; + soc_k7ddrphy_dfi_p2_rddata[29] <= soc_k7ddrphy_bitslip29_o[4]; + soc_k7ddrphy_dfi_p2_rddata[61] <= soc_k7ddrphy_bitslip29_o[5]; + soc_k7ddrphy_dfi_p2_rddata[30] <= soc_k7ddrphy_bitslip30_o[4]; + soc_k7ddrphy_dfi_p2_rddata[62] <= soc_k7ddrphy_bitslip30_o[5]; + soc_k7ddrphy_dfi_p2_rddata[31] <= soc_k7ddrphy_bitslip31_o[4]; + soc_k7ddrphy_dfi_p2_rddata[63] <= soc_k7ddrphy_bitslip31_o[5]; +// synthesis translate_off + dummy_d_6 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_7; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_dfi_p3_rddata <= 64'd0; + soc_k7ddrphy_dfi_p3_rddata[0] <= soc_k7ddrphy_bitslip0_o[6]; + soc_k7ddrphy_dfi_p3_rddata[32] <= soc_k7ddrphy_bitslip0_o[7]; + soc_k7ddrphy_dfi_p3_rddata[1] <= soc_k7ddrphy_bitslip1_o[6]; + soc_k7ddrphy_dfi_p3_rddata[33] <= soc_k7ddrphy_bitslip1_o[7]; + soc_k7ddrphy_dfi_p3_rddata[2] <= soc_k7ddrphy_bitslip2_o[6]; + soc_k7ddrphy_dfi_p3_rddata[34] <= soc_k7ddrphy_bitslip2_o[7]; + soc_k7ddrphy_dfi_p3_rddata[3] <= soc_k7ddrphy_bitslip3_o[6]; + soc_k7ddrphy_dfi_p3_rddata[35] <= soc_k7ddrphy_bitslip3_o[7]; + soc_k7ddrphy_dfi_p3_rddata[4] <= soc_k7ddrphy_bitslip4_o[6]; + soc_k7ddrphy_dfi_p3_rddata[36] <= soc_k7ddrphy_bitslip4_o[7]; + soc_k7ddrphy_dfi_p3_rddata[5] <= soc_k7ddrphy_bitslip5_o[6]; + soc_k7ddrphy_dfi_p3_rddata[37] <= soc_k7ddrphy_bitslip5_o[7]; + soc_k7ddrphy_dfi_p3_rddata[6] <= soc_k7ddrphy_bitslip6_o[6]; + soc_k7ddrphy_dfi_p3_rddata[38] <= soc_k7ddrphy_bitslip6_o[7]; + soc_k7ddrphy_dfi_p3_rddata[7] <= soc_k7ddrphy_bitslip7_o[6]; + soc_k7ddrphy_dfi_p3_rddata[39] <= soc_k7ddrphy_bitslip7_o[7]; + soc_k7ddrphy_dfi_p3_rddata[8] <= soc_k7ddrphy_bitslip8_o[6]; + soc_k7ddrphy_dfi_p3_rddata[40] <= soc_k7ddrphy_bitslip8_o[7]; + soc_k7ddrphy_dfi_p3_rddata[9] <= soc_k7ddrphy_bitslip9_o[6]; + soc_k7ddrphy_dfi_p3_rddata[41] <= soc_k7ddrphy_bitslip9_o[7]; + soc_k7ddrphy_dfi_p3_rddata[10] <= soc_k7ddrphy_bitslip10_o[6]; + soc_k7ddrphy_dfi_p3_rddata[42] <= soc_k7ddrphy_bitslip10_o[7]; + soc_k7ddrphy_dfi_p3_rddata[11] <= soc_k7ddrphy_bitslip11_o[6]; + soc_k7ddrphy_dfi_p3_rddata[43] <= soc_k7ddrphy_bitslip11_o[7]; + soc_k7ddrphy_dfi_p3_rddata[12] <= soc_k7ddrphy_bitslip12_o[6]; + soc_k7ddrphy_dfi_p3_rddata[44] <= soc_k7ddrphy_bitslip12_o[7]; + soc_k7ddrphy_dfi_p3_rddata[13] <= soc_k7ddrphy_bitslip13_o[6]; + soc_k7ddrphy_dfi_p3_rddata[45] <= soc_k7ddrphy_bitslip13_o[7]; + soc_k7ddrphy_dfi_p3_rddata[14] <= soc_k7ddrphy_bitslip14_o[6]; + soc_k7ddrphy_dfi_p3_rddata[46] <= soc_k7ddrphy_bitslip14_o[7]; + soc_k7ddrphy_dfi_p3_rddata[15] <= soc_k7ddrphy_bitslip15_o[6]; + soc_k7ddrphy_dfi_p3_rddata[47] <= soc_k7ddrphy_bitslip15_o[7]; + soc_k7ddrphy_dfi_p3_rddata[16] <= soc_k7ddrphy_bitslip16_o[6]; + soc_k7ddrphy_dfi_p3_rddata[48] <= soc_k7ddrphy_bitslip16_o[7]; + soc_k7ddrphy_dfi_p3_rddata[17] <= soc_k7ddrphy_bitslip17_o[6]; + soc_k7ddrphy_dfi_p3_rddata[49] <= soc_k7ddrphy_bitslip17_o[7]; + soc_k7ddrphy_dfi_p3_rddata[18] <= soc_k7ddrphy_bitslip18_o[6]; + soc_k7ddrphy_dfi_p3_rddata[50] <= soc_k7ddrphy_bitslip18_o[7]; + soc_k7ddrphy_dfi_p3_rddata[19] <= soc_k7ddrphy_bitslip19_o[6]; + soc_k7ddrphy_dfi_p3_rddata[51] <= soc_k7ddrphy_bitslip19_o[7]; + soc_k7ddrphy_dfi_p3_rddata[20] <= soc_k7ddrphy_bitslip20_o[6]; + soc_k7ddrphy_dfi_p3_rddata[52] <= soc_k7ddrphy_bitslip20_o[7]; + soc_k7ddrphy_dfi_p3_rddata[21] <= soc_k7ddrphy_bitslip21_o[6]; + soc_k7ddrphy_dfi_p3_rddata[53] <= soc_k7ddrphy_bitslip21_o[7]; + soc_k7ddrphy_dfi_p3_rddata[22] <= soc_k7ddrphy_bitslip22_o[6]; + soc_k7ddrphy_dfi_p3_rddata[54] <= soc_k7ddrphy_bitslip22_o[7]; + soc_k7ddrphy_dfi_p3_rddata[23] <= soc_k7ddrphy_bitslip23_o[6]; + soc_k7ddrphy_dfi_p3_rddata[55] <= soc_k7ddrphy_bitslip23_o[7]; + soc_k7ddrphy_dfi_p3_rddata[24] <= soc_k7ddrphy_bitslip24_o[6]; + soc_k7ddrphy_dfi_p3_rddata[56] <= soc_k7ddrphy_bitslip24_o[7]; + soc_k7ddrphy_dfi_p3_rddata[25] <= soc_k7ddrphy_bitslip25_o[6]; + soc_k7ddrphy_dfi_p3_rddata[57] <= soc_k7ddrphy_bitslip25_o[7]; + soc_k7ddrphy_dfi_p3_rddata[26] <= soc_k7ddrphy_bitslip26_o[6]; + soc_k7ddrphy_dfi_p3_rddata[58] <= soc_k7ddrphy_bitslip26_o[7]; + soc_k7ddrphy_dfi_p3_rddata[27] <= soc_k7ddrphy_bitslip27_o[6]; + soc_k7ddrphy_dfi_p3_rddata[59] <= soc_k7ddrphy_bitslip27_o[7]; + soc_k7ddrphy_dfi_p3_rddata[28] <= soc_k7ddrphy_bitslip28_o[6]; + soc_k7ddrphy_dfi_p3_rddata[60] <= soc_k7ddrphy_bitslip28_o[7]; + soc_k7ddrphy_dfi_p3_rddata[29] <= soc_k7ddrphy_bitslip29_o[6]; + soc_k7ddrphy_dfi_p3_rddata[61] <= soc_k7ddrphy_bitslip29_o[7]; + soc_k7ddrphy_dfi_p3_rddata[30] <= soc_k7ddrphy_bitslip30_o[6]; + soc_k7ddrphy_dfi_p3_rddata[62] <= soc_k7ddrphy_bitslip30_o[7]; + soc_k7ddrphy_dfi_p3_rddata[31] <= soc_k7ddrphy_bitslip31_o[6]; + soc_k7ddrphy_dfi_p3_rddata[63] <= soc_k7ddrphy_bitslip31_o[7]; +// synthesis translate_off + dummy_d_7 = dummy_s; +// synthesis translate_on +end +assign soc_k7ddrphy_bitslip1_i = soc_k7ddrphy_dq_i_data1; +assign soc_k7ddrphy_bitslip2_i = soc_k7ddrphy_dq_i_data2; +assign soc_k7ddrphy_bitslip3_i = soc_k7ddrphy_dq_i_data3; +assign soc_k7ddrphy_bitslip4_i = soc_k7ddrphy_dq_i_data4; +assign soc_k7ddrphy_bitslip5_i = soc_k7ddrphy_dq_i_data5; +assign soc_k7ddrphy_bitslip6_i = soc_k7ddrphy_dq_i_data6; +assign soc_k7ddrphy_bitslip7_i = soc_k7ddrphy_dq_i_data7; +assign soc_k7ddrphy_bitslip8_i = soc_k7ddrphy_dq_i_data8; +assign soc_k7ddrphy_bitslip9_i = soc_k7ddrphy_dq_i_data9; +assign soc_k7ddrphy_bitslip10_i = soc_k7ddrphy_dq_i_data10; +assign soc_k7ddrphy_bitslip11_i = soc_k7ddrphy_dq_i_data11; +assign soc_k7ddrphy_bitslip12_i = soc_k7ddrphy_dq_i_data12; +assign soc_k7ddrphy_bitslip13_i = soc_k7ddrphy_dq_i_data13; +assign soc_k7ddrphy_bitslip14_i = soc_k7ddrphy_dq_i_data14; +assign soc_k7ddrphy_bitslip15_i = soc_k7ddrphy_dq_i_data15; +assign soc_k7ddrphy_bitslip16_i = soc_k7ddrphy_dq_i_data16; +assign soc_k7ddrphy_bitslip17_i = soc_k7ddrphy_dq_i_data17; +assign soc_k7ddrphy_bitslip18_i = soc_k7ddrphy_dq_i_data18; +assign soc_k7ddrphy_bitslip19_i = soc_k7ddrphy_dq_i_data19; +assign soc_k7ddrphy_bitslip20_i = soc_k7ddrphy_dq_i_data20; +assign soc_k7ddrphy_bitslip21_i = soc_k7ddrphy_dq_i_data21; +assign soc_k7ddrphy_bitslip22_i = soc_k7ddrphy_dq_i_data22; +assign soc_k7ddrphy_bitslip23_i = soc_k7ddrphy_dq_i_data23; +assign soc_k7ddrphy_bitslip24_i = soc_k7ddrphy_dq_i_data24; +assign soc_k7ddrphy_bitslip25_i = soc_k7ddrphy_dq_i_data25; +assign soc_k7ddrphy_bitslip26_i = soc_k7ddrphy_dq_i_data26; +assign soc_k7ddrphy_bitslip27_i = soc_k7ddrphy_dq_i_data27; +assign soc_k7ddrphy_bitslip28_i = soc_k7ddrphy_dq_i_data28; +assign soc_k7ddrphy_bitslip29_i = soc_k7ddrphy_dq_i_data29; +assign soc_k7ddrphy_bitslip30_i = soc_k7ddrphy_dq_i_data30; +assign soc_k7ddrphy_bitslip31_i = soc_k7ddrphy_dq_i_data31; +assign soc_k7ddrphy_rddata_en = {soc_k7ddrphy_rddata_en_last, soc_k7ddrphy_dfi_p2_rddata_en}; +assign soc_k7ddrphy_wrdata_en = {soc_k7ddrphy_wrdata_en_last, soc_k7ddrphy_dfi_p3_wrdata_en}; +assign soc_k7ddrphy_dq_oe = soc_k7ddrphy_wrdata_en[2]; + +// synthesis translate_off +reg dummy_d_8; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_dqs_oe <= 1'd0; + if (soc_k7ddrphy_wlevel_en_storage) begin + soc_k7ddrphy_dqs_oe <= 1'd1; + end else begin + soc_k7ddrphy_dqs_oe <= soc_k7ddrphy_dq_oe; + end +// synthesis translate_off + dummy_d_8 = dummy_s; +// synthesis translate_on +end +assign soc_k7ddrphy_dqspattern0 = (soc_k7ddrphy_wrdata_en[1] & (~soc_k7ddrphy_wrdata_en[2])); +assign soc_k7ddrphy_dqspattern1 = (soc_k7ddrphy_wrdata_en[3] & (~soc_k7ddrphy_wrdata_en[2])); + +// synthesis translate_off +reg dummy_d_9; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_dqspattern_o <= 8'd0; + soc_k7ddrphy_dqspattern_o <= 7'd85; + if (soc_k7ddrphy_dqspattern0) begin + soc_k7ddrphy_dqspattern_o <= 5'd21; + end + if (soc_k7ddrphy_dqspattern1) begin + soc_k7ddrphy_dqspattern_o <= 7'd84; + end + if (soc_k7ddrphy_wlevel_en_storage) begin + soc_k7ddrphy_dqspattern_o <= 1'd0; + if (soc_k7ddrphy_wlevel_strobe_re) begin + soc_k7ddrphy_dqspattern_o <= 1'd1; + end + end +// synthesis translate_off + dummy_d_9 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_10; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip0_o <= 8'd0; + case (soc_k7ddrphy_bitslip0_value) + 1'd0: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip0_o <= soc_k7ddrphy_bitslip0_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_10 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_11; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip1_o <= 8'd0; + case (soc_k7ddrphy_bitslip1_value) + 1'd0: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip1_o <= soc_k7ddrphy_bitslip1_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_11 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_12; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip2_o <= 8'd0; + case (soc_k7ddrphy_bitslip2_value) + 1'd0: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip2_o <= soc_k7ddrphy_bitslip2_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_12 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_13; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip3_o <= 8'd0; + case (soc_k7ddrphy_bitslip3_value) + 1'd0: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip3_o <= soc_k7ddrphy_bitslip3_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_13 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_14; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip4_o <= 8'd0; + case (soc_k7ddrphy_bitslip4_value) + 1'd0: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip4_o <= soc_k7ddrphy_bitslip4_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_14 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_15; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip5_o <= 8'd0; + case (soc_k7ddrphy_bitslip5_value) + 1'd0: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip5_o <= soc_k7ddrphy_bitslip5_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_15 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_16; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip6_o <= 8'd0; + case (soc_k7ddrphy_bitslip6_value) + 1'd0: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip6_o <= soc_k7ddrphy_bitslip6_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_16 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_17; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip7_o <= 8'd0; + case (soc_k7ddrphy_bitslip7_value) + 1'd0: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip7_o <= soc_k7ddrphy_bitslip7_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_17 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_18; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip8_o <= 8'd0; + case (soc_k7ddrphy_bitslip8_value) + 1'd0: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip8_o <= soc_k7ddrphy_bitslip8_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_18 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_19; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip9_o <= 8'd0; + case (soc_k7ddrphy_bitslip9_value) + 1'd0: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip9_o <= soc_k7ddrphy_bitslip9_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_19 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_20; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip10_o <= 8'd0; + case (soc_k7ddrphy_bitslip10_value) + 1'd0: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip10_o <= soc_k7ddrphy_bitslip10_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_20 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_21; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip11_o <= 8'd0; + case (soc_k7ddrphy_bitslip11_value) + 1'd0: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip11_o <= soc_k7ddrphy_bitslip11_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip12_o <= 8'd0; + case (soc_k7ddrphy_bitslip12_value) + 1'd0: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip12_o <= soc_k7ddrphy_bitslip12_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_22 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_23; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip13_o <= 8'd0; + case (soc_k7ddrphy_bitslip13_value) + 1'd0: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip13_o <= soc_k7ddrphy_bitslip13_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_23 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_24; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip14_o <= 8'd0; + case (soc_k7ddrphy_bitslip14_value) + 1'd0: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip14_o <= soc_k7ddrphy_bitslip14_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_24 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_25; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip15_o <= 8'd0; + case (soc_k7ddrphy_bitslip15_value) + 1'd0: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip15_o <= soc_k7ddrphy_bitslip15_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_25 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_26; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip16_o <= 8'd0; + case (soc_k7ddrphy_bitslip16_value) + 1'd0: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip16_o <= soc_k7ddrphy_bitslip16_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_26 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_27; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip17_o <= 8'd0; + case (soc_k7ddrphy_bitslip17_value) + 1'd0: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip17_o <= soc_k7ddrphy_bitslip17_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_27 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_28; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip18_o <= 8'd0; + case (soc_k7ddrphy_bitslip18_value) + 1'd0: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip18_o <= soc_k7ddrphy_bitslip18_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_28 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_29; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip19_o <= 8'd0; + case (soc_k7ddrphy_bitslip19_value) + 1'd0: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip19_o <= soc_k7ddrphy_bitslip19_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_29 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_30; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip20_o <= 8'd0; + case (soc_k7ddrphy_bitslip20_value) + 1'd0: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip20_o <= soc_k7ddrphy_bitslip20_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_30 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_31; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip21_o <= 8'd0; + case (soc_k7ddrphy_bitslip21_value) + 1'd0: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip21_o <= soc_k7ddrphy_bitslip21_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_31 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_32; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip22_o <= 8'd0; + case (soc_k7ddrphy_bitslip22_value) + 1'd0: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip22_o <= soc_k7ddrphy_bitslip22_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_32 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_33; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip23_o <= 8'd0; + case (soc_k7ddrphy_bitslip23_value) + 1'd0: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip23_o <= soc_k7ddrphy_bitslip23_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_33 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_34; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip24_o <= 8'd0; + case (soc_k7ddrphy_bitslip24_value) + 1'd0: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip24_o <= soc_k7ddrphy_bitslip24_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_34 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_35; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip25_o <= 8'd0; + case (soc_k7ddrphy_bitslip25_value) + 1'd0: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip25_o <= soc_k7ddrphy_bitslip25_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_35 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_36; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip26_o <= 8'd0; + case (soc_k7ddrphy_bitslip26_value) + 1'd0: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip26_o <= soc_k7ddrphy_bitslip26_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_36 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_37; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip27_o <= 8'd0; + case (soc_k7ddrphy_bitslip27_value) + 1'd0: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip27_o <= soc_k7ddrphy_bitslip27_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_37 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_38; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip28_o <= 8'd0; + case (soc_k7ddrphy_bitslip28_value) + 1'd0: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip28_o <= soc_k7ddrphy_bitslip28_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_39; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip29_o <= 8'd0; + case (soc_k7ddrphy_bitslip29_value) + 1'd0: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip29_o <= soc_k7ddrphy_bitslip29_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_39 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_40; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip30_o <= 8'd0; + case (soc_k7ddrphy_bitslip30_value) + 1'd0: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip30_o <= soc_k7ddrphy_bitslip30_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_40 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_41; +// synthesis translate_on +always @(*) begin + soc_k7ddrphy_bitslip31_o <= 8'd0; + case (soc_k7ddrphy_bitslip31_value) + 1'd0: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[7:0]; + end + 1'd1: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[8:1]; + end + 2'd2: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[9:2]; + end + 2'd3: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[10:3]; + end + 3'd4: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[11:4]; + end + 3'd5: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[12:5]; + end + 3'd6: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[13:6]; + end + 3'd7: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[14:7]; + end + 4'd8: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[15:8]; + end + 4'd9: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[16:9]; + end + 4'd10: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[17:10]; + end + 4'd11: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[18:11]; + end + 4'd12: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[19:12]; + end + 4'd13: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[20:13]; + end + 4'd14: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[21:14]; + end + 4'd15: begin + soc_k7ddrphy_bitslip31_o <= soc_k7ddrphy_bitslip31_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_41 = dummy_s; +// synthesis translate_on +end +assign soc_k7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; +assign soc_k7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; +assign soc_k7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; +assign soc_k7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; +assign soc_k7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; +assign soc_k7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; +assign soc_k7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; +assign soc_k7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; +assign soc_k7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; +assign soc_k7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; +assign soc_k7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; +assign soc_k7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; +assign soc_k7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; +assign soc_k7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; +assign soc_litedramcore_master_p0_rddata = soc_k7ddrphy_dfi_p0_rddata; +assign soc_litedramcore_master_p0_rddata_valid = soc_k7ddrphy_dfi_p0_rddata_valid; +assign soc_k7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; +assign soc_k7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; +assign soc_k7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; +assign soc_k7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; +assign soc_k7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; +assign soc_k7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; +assign soc_k7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; +assign soc_k7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; +assign soc_k7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; +assign soc_k7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; +assign soc_k7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; +assign soc_k7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; +assign soc_k7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; +assign soc_k7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; +assign soc_litedramcore_master_p1_rddata = soc_k7ddrphy_dfi_p1_rddata; +assign soc_litedramcore_master_p1_rddata_valid = soc_k7ddrphy_dfi_p1_rddata_valid; +assign soc_k7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; +assign soc_k7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; +assign soc_k7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; +assign soc_k7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; +assign soc_k7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; +assign soc_k7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; +assign soc_k7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; +assign soc_k7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; +assign soc_k7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; +assign soc_k7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; +assign soc_k7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; +assign soc_k7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; +assign soc_k7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; +assign soc_k7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; +assign soc_litedramcore_master_p2_rddata = soc_k7ddrphy_dfi_p2_rddata; +assign soc_litedramcore_master_p2_rddata_valid = soc_k7ddrphy_dfi_p2_rddata_valid; +assign soc_k7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; +assign soc_k7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; +assign soc_k7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; +assign soc_k7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; +assign soc_k7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; +assign soc_k7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; +assign soc_k7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; +assign soc_k7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; +assign soc_k7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; +assign soc_k7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; +assign soc_k7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; +assign soc_k7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; +assign soc_k7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; +assign soc_k7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; +assign soc_litedramcore_master_p3_rddata = soc_k7ddrphy_dfi_p3_rddata; +assign soc_litedramcore_master_p3_rddata_valid = soc_k7ddrphy_dfi_p3_rddata_valid; +assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; +assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; +assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; +assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; +assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; +assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; +assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; +assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; +assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; +assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; +assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; +assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; +assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; +assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; +assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; +assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; +assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; +assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; +assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; +assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; +assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; +assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; +assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; +assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; +assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; +assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; +assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; +assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; +assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; +assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; +assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; +assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; +assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; +assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; +assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; +assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; +assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; +assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; +assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; +assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; +assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; +assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; +assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; +assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; +assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; +assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; +assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; +assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; +assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; +assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; +assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; +assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; +assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; +assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; +assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; +assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; +assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; +assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; +assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; +assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; +assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; +assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; +assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; +assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; + +// synthesis translate_off +reg dummy_d_42; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; + end else begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; + end +// synthesis translate_off + dummy_d_42 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_43; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p1_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; + end else begin + end +// synthesis translate_off + dummy_d_43 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_44; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; + end else begin + soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; + end +// synthesis translate_off + dummy_d_44 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_45; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_45 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_46; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; + end else begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; + end +// synthesis translate_off + dummy_d_46 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_47; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; + end else begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; + end +// synthesis translate_off + dummy_d_47 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_48; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; + end else begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; + end +// synthesis translate_off + dummy_d_48 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_49; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; + end else begin + soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; + end +// synthesis translate_off + dummy_d_49 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_50; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_wrdata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; + end else begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; + end +// synthesis translate_off + dummy_d_50 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_51; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; + end +// synthesis translate_off + dummy_d_51 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_52; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; + end else begin + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; + end +// synthesis translate_off + dummy_d_52 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_53; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + end +// synthesis translate_off + dummy_d_53 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_54; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_wrdata_mask <= 8'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; + end else begin + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; + end +// synthesis translate_off + dummy_d_54 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_55; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; + end else begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; + end +// synthesis translate_off + dummy_d_55 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_56; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_address <= 15'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; + end else begin + soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; + end +// synthesis translate_off + dummy_d_56 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_57; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; + end else begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; + end +// synthesis translate_off + dummy_d_57 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_58; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; + end else begin + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; + end +// synthesis translate_off + dummy_d_58 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_59; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + end else begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; + end +// synthesis translate_off + dummy_d_59 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_60; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; + end else begin + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; + end +// synthesis translate_off + dummy_d_60 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_61; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p2_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; + end else begin + end +// synthesis translate_off + dummy_d_61 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_62; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + end else begin + soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_62 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_63; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_63 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_64; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + end else begin + soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; + end +// synthesis translate_off + dummy_d_64 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_65; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + end else begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; + end +// synthesis translate_off + dummy_d_65 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_66; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; + end else begin + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; + end +// synthesis translate_off + dummy_d_66 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_67; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; + end else begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; + end +// synthesis translate_off + dummy_d_67 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_68; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_wrdata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; + end else begin + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; + end +// synthesis translate_off + dummy_d_68 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_69; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; + end +// synthesis translate_off + dummy_d_69 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_70; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; + end else begin + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; + end +// synthesis translate_off + dummy_d_70 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_71; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + end +// synthesis translate_off + dummy_d_71 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_72; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_wrdata_mask <= 8'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; + end else begin + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; + end +// synthesis translate_off + dummy_d_72 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_73; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; + end else begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; + end +// synthesis translate_off + dummy_d_73 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_74; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_address <= 15'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; + end else begin + soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; + end +// synthesis translate_off + dummy_d_74 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_75; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; + end else begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; + end +// synthesis translate_off + dummy_d_75 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_76; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; + end else begin + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; + end +// synthesis translate_off + dummy_d_76 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_77; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; + end else begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; + end +// synthesis translate_off + dummy_d_77 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_78; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; + end else begin + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; + end +// synthesis translate_off + dummy_d_78 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_79; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p3_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; + end else begin + end +// synthesis translate_off + dummy_d_79 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_80; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; + end else begin + soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; + end +// synthesis translate_off + dummy_d_80 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_81; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_81 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_82; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; + end else begin + soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; + end +// synthesis translate_off + dummy_d_82 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_83; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; + end else begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; + end +// synthesis translate_off + dummy_d_83 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_84; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; + end else begin + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; + end +// synthesis translate_off + dummy_d_84 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_85; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; + end else begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; + end +// synthesis translate_off + dummy_d_85 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_86; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_wrdata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; + end else begin + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; + end +// synthesis translate_off + dummy_d_86 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_87; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; + end +// synthesis translate_off + dummy_d_87 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_88; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; + end else begin + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; + end +// synthesis translate_off + dummy_d_88 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_89; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + end +// synthesis translate_off + dummy_d_89 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_90; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_wrdata_mask <= 8'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; + end else begin + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; + end +// synthesis translate_off + dummy_d_90 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_91; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; + end else begin + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; + end +// synthesis translate_off + dummy_d_91 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_92; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_address <= 15'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; + end else begin + soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; + end +// synthesis translate_off + dummy_d_92 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_93; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; + end else begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; + end +// synthesis translate_off + dummy_d_93 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; + end else begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; + end else begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; + end else begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p0_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; + end else begin + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_98; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; + end else begin + soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; + end +// synthesis translate_off + dummy_d_98 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_99; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_99 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_100; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; + end else begin + soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; + end +// synthesis translate_off + dummy_d_100 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_101; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; + end else begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; + end +// synthesis translate_off + dummy_d_101 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_102; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; + end else begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; + end +// synthesis translate_off + dummy_d_102 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_103; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; + end else begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; + end +// synthesis translate_off + dummy_d_103 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_104; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_wrdata <= 64'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; + end else begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; + end +// synthesis translate_off + dummy_d_104 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_105; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_rddata <= 64'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; + end +// synthesis translate_off + dummy_d_105 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_106; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; + end else begin + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; + end +// synthesis translate_off + dummy_d_106 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_107; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + end +// synthesis translate_off + dummy_d_107 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_108; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_wrdata_mask <= 8'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; + end else begin + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; + end +// synthesis translate_off + dummy_d_108 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_109; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; + end else begin + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; + end +// synthesis translate_off + dummy_d_109 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_110; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_address <= 15'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; + end else begin + soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; + end +// synthesis translate_off + dummy_d_110 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_111; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; + end else begin + soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; + end +// synthesis translate_off + dummy_d_111 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_112; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; + end else begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; + end +// synthesis translate_off + dummy_d_112 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_113; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + end else begin + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; + end +// synthesis translate_off + dummy_d_113 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; + +// synthesis translate_off +reg dummy_d_114; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); + end else begin + soc_litedramcore_inti_p0_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_114 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_115; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); + end else begin + soc_litedramcore_inti_p0_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_115 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_116; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); + end else begin + soc_litedramcore_inti_p0_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_116 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_117; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_117 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; +assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; +assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]); +assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]); +assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; +assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_118; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); + end else begin + soc_litedramcore_inti_p1_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_118 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_119; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); + end else begin + soc_litedramcore_inti_p1_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_119 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_120; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); + end else begin + soc_litedramcore_inti_p1_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_120 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_121; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_121 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; +assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; +assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]); +assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]); +assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; +assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_122; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); + end else begin + soc_litedramcore_inti_p2_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); + end else begin + soc_litedramcore_inti_p2_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_123 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_124; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); + end else begin + soc_litedramcore_inti_p2_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_124 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_125; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_125 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; +assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; +assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]); +assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]); +assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; +assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_126; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); + end else begin + soc_litedramcore_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_126 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_127; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); + end else begin + soc_litedramcore_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_127 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_128; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); + end else begin + soc_litedramcore_inti_p3_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_128 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_129; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_129 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; +assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; +assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]); +assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]); +assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; +assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0; +assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; +assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; +assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; +assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; +assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; +assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; +assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; +assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; +assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; +assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; +assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; +assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; +assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; +assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; +assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; +assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; +assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; +assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; +assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; +assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; +assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; +assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; +assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; +assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; +assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; +assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; +assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; +assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; +assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; +assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; +assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; +assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; +assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; +assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; +assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; +assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; +assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; +assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; +assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; +assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; +assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; +assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; +assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; +assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; +assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; +assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; +assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; +assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; +assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; +assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; +assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; +assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; +assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; +assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; +assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; +assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; +assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); +assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; +assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; +assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; +assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); +assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); +assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; +assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; +assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); +assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); +assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); +assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; +assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_130; +// synthesis translate_on +always @(*) begin + vns_refresher_next_state <= 2'd0; + vns_refresher_next_state <= vns_refresher_state; + case (vns_refresher_state) + 1'd1: begin + if (soc_litedramcore_cmd_ready) begin + vns_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + vns_refresher_next_state <= 2'd3; + end else begin + vns_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + vns_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (soc_litedramcore_wants_refresh) begin + vns_refresher_next_state <= 1'd1; + end + end + end + endcase +// synthesis translate_off + dummy_d_130 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_131; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cmd_valid <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + soc_litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_131 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_132; +// synthesis translate_on +always @(*) begin + soc_litedramcore_zqcs_executer_start <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + soc_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_132 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_133; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cmd_last <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_133 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_134; +// synthesis translate_on +always @(*) begin + soc_litedramcore_sequencer_start0 <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + if (soc_litedramcore_cmd_ready) begin + soc_litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; +assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); +assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_135 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); +assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); +assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); + +// synthesis translate_off +reg dummy_d_136; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_136 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_137; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_137 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_138; +// synthesis translate_on +always @(*) begin + vns_bankmachine0_next_state <= 4'd0; + vns_bankmachine0_next_state <= vns_bankmachine0_state; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine0_refresh_req)) begin + vns_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine0_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + vns_bankmachine0_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin + vns_bankmachine0_next_state <= 2'd2; + end + end else begin + vns_bankmachine0_next_state <= 1'd1; + end + end else begin + vns_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_138 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_139; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_139 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_140; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_140 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_141; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_141 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_142; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine0_twtpcon_ready) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_142 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_143; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_143 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_144; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_row_open <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_144 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_145; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_row_close <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_145 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_146; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_146 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_147; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_147 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_148; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_148 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_149; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_149 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_150; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_150 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_151; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_151 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; +assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); +assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; + +// synthesis translate_off +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_152 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); +assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); +assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_153; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_153 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_154; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_154 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_155; +// synthesis translate_on +always @(*) begin + vns_bankmachine1_next_state <= 4'd0; + vns_bankmachine1_next_state <= vns_bankmachine1_state; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine1_refresh_req)) begin + vns_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine1_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + vns_bankmachine1_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin + vns_bankmachine1_next_state <= 2'd2; + end + end else begin + vns_bankmachine1_next_state <= 1'd1; + end + end else begin + vns_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_155 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_156; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_156 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_157; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_157 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_158; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_158 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_159; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_159 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_160; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine1_twtpcon_ready) begin + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_160 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_161; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_161 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_162; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_row_open <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_162 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_163; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_row_close <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_163 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_164; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_164 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_165; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_165 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_166; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_166 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_167; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_167 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_168; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_168 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; +assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); +assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; + +// synthesis translate_off +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_169 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); +assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_170; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_170 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_171; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_171 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_172; +// synthesis translate_on +always @(*) begin + vns_bankmachine2_next_state <= 4'd0; + vns_bankmachine2_next_state <= vns_bankmachine2_state; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine2_refresh_req)) begin + vns_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine2_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + vns_bankmachine2_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin + vns_bankmachine2_next_state <= 2'd2; + end + end else begin + vns_bankmachine2_next_state <= 1'd1; + end + end else begin + vns_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_172 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_173; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_173 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_174; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_174 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_175; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_175 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_176; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine2_twtpcon_ready) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_176 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_177; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_177 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_178; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_178 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_179; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_row_open <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_179 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_180; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_row_close <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_180 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_181; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_181 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_182; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_182 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_183; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_183 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_184; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_184 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_185; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; +assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); +assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; + +// synthesis translate_off +reg dummy_d_186; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_186 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); +assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); +assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); + +// synthesis translate_off +reg dummy_d_187; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_187 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_188; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_188 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_189; +// synthesis translate_on +always @(*) begin + vns_bankmachine3_next_state <= 4'd0; + vns_bankmachine3_next_state <= vns_bankmachine3_state; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine3_refresh_req)) begin + vns_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine3_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + vns_bankmachine3_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin + vns_bankmachine3_next_state <= 2'd2; + end + end else begin + vns_bankmachine3_next_state <= 1'd1; + end + end else begin + vns_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_189 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_190; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_190 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_191; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_191 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_192; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_192 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_193; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_193 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_194; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_194 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_195; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_row_open <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_195 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_196; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_row_close <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_196 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_197; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_197 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_198; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_198 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_199; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_199 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_200; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_200 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_201; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_201 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_202; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_202 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; +assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); +assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; + +// synthesis translate_off +reg dummy_d_203; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_203 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); +assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); +assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); + +// synthesis translate_off +reg dummy_d_204; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_204 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_205; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_205 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_206; +// synthesis translate_on +always @(*) begin + vns_bankmachine4_next_state <= 4'd0; + vns_bankmachine4_next_state <= vns_bankmachine4_state; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine4_refresh_req)) begin + vns_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine4_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + vns_bankmachine4_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin + vns_bankmachine4_next_state <= 2'd2; + end + end else begin + vns_bankmachine4_next_state <= 1'd1; + end + end else begin + vns_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_206 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_207; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_207 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_208; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_208 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_209; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_209 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_210; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine4_twtpcon_ready) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_210 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_211; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_211 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_212; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_row_open <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_212 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_213; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_row_close <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_213 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_214; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_214 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_215; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_215 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_216; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_216 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_217; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_217 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_218; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_218 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_219; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_219 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; +assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); +assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; + +// synthesis translate_off +reg dummy_d_220; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_220 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); +assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); +assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); + +// synthesis translate_off +reg dummy_d_221; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_221 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_222; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_222 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_223; +// synthesis translate_on +always @(*) begin + vns_bankmachine5_next_state <= 4'd0; + vns_bankmachine5_next_state <= vns_bankmachine5_state; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine5_refresh_req)) begin + vns_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine5_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + vns_bankmachine5_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin + vns_bankmachine5_next_state <= 2'd2; + end + end else begin + vns_bankmachine5_next_state <= 1'd1; + end + end else begin + vns_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_223 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_224; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_224 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_225; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_225 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_226; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_226 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_227; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_227 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_228; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine5_twtpcon_ready) begin + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_228 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_229; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_229 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_230; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_row_open <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_230 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_231; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_row_close <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_231 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_232; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_232 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_233; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_233 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_234; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_234 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_235; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_235 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_236; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_236 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; +assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); +assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; + +// synthesis translate_off +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_237 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); +assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); +assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_238; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_238 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_239; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_239 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_240; +// synthesis translate_on +always @(*) begin + vns_bankmachine6_next_state <= 4'd0; + vns_bankmachine6_next_state <= vns_bankmachine6_state; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine6_refresh_req)) begin + vns_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine6_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + vns_bankmachine6_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin + vns_bankmachine6_next_state <= 2'd2; + end + end else begin + vns_bankmachine6_next_state <= 1'd1; + end + end else begin + vns_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_240 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_241; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_241 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_242; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_242 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_243; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_243 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_244; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine6_twtpcon_ready) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_244 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_245; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_245 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_246; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_246 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_247; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_row_open <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_247 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_248; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_row_close <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_248 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_249; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_249 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_250; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_250 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_251; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_251 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_252; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_252 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_253; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_253 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; +assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); +assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); +assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; + +// synthesis translate_off +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); +assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); +assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_255; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin + soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_255 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_256; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_256 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_257; +// synthesis translate_on +always @(*) begin + vns_bankmachine7_next_state <= 4'd0; + vns_bankmachine7_next_state <= vns_bankmachine7_state; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine7_refresh_req)) begin + vns_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine7_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + vns_bankmachine7_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin + vns_bankmachine7_next_state <= 2'd2; + end + end else begin + vns_bankmachine7_next_state <= 1'd1; + end + end else begin + vns_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_257 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_258; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_258 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_259; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_259 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_260; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_260 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_261; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_261 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_262; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_262 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_263; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_263 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_264; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_row_open <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_264 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_265; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_row_close <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_265 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_266; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_266 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_267; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_267 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_268; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_268 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_269; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_269 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_270; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_270 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); +assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); +assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; +assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); +assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); +assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); +assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); +assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); +assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); +assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); + +// synthesis translate_off +reg dummy_d_271; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_valids <= 8'd0; + soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_271 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; +assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0; +assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; +assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; +assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; +assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; +assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_272; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; + end +// synthesis translate_off + dummy_d_272 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_273; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + end +// synthesis translate_off + dummy_d_273 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_274; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + end +// synthesis translate_off + dummy_d_274 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_275; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_275 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_276; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_276 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_277; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_277 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_278; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_278 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_279; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_279 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_280; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_281 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_282; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_282 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); + +// synthesis translate_off +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_valids <= 8'd0; + soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; +assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6; +assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7; +assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; +assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; +assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; +assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; + +// synthesis translate_off +reg dummy_d_284; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + end +// synthesis translate_off + dummy_d_284 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_285; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + end +// synthesis translate_off + dummy_d_285 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_286; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5; + end +// synthesis translate_off + dummy_d_286 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); +assign soc_litedramcore_dfi_p0_reset_n = 1'd1; +assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; +assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; +assign soc_litedramcore_dfi_p1_reset_n = 1'd1; +assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; +assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; +assign soc_litedramcore_dfi_p2_reset_n = 1'd1; +assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; +assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; +assign soc_litedramcore_dfi_p3_reset_n = 1'd1; +assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; +assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; +assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); + +// synthesis translate_off +reg dummy_d_287; +// synthesis translate_on +always @(*) begin + vns_multiplexer_next_state <= 4'd0; + vns_multiplexer_next_state <= vns_multiplexer_state; + case (vns_multiplexer_state) + 1'd1: begin + if (soc_litedramcore_read_available) begin + if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin + vns_multiplexer_next_state <= 2'd3; + end + end + if (soc_litedramcore_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_litedramcore_cmd_last) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (soc_litedramcore_twtrcon_ready) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + vns_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + vns_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + vns_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + vns_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + vns_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + vns_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + vns_multiplexer_next_state <= 1'd1; + end + default: begin + if (soc_litedramcore_write_available) begin + if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin + vns_multiplexer_next_state <= 3'd4; + end + end + if (soc_litedramcore_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + endcase +// synthesis translate_off + dummy_d_287 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_288; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel2 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel2 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel2 <= 2'd2; + end + endcase +// synthesis translate_off + dummy_d_288 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_289; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_want_activates <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_289 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_290; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel3 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel3 <= 2'd2; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel3 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_290 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_291; +// synthesis translate_on +always @(*) begin + soc_litedramcore_en0 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_en0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_291 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_292; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + soc_litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_292 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_293; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end + end + endcase +// synthesis translate_off + dummy_d_293 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_294; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_want_reads <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_294 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_295; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_want_writes <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_295 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_296; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_296 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_297; +// synthesis translate_on +always @(*) begin + soc_litedramcore_en1 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_297 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_298; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel0 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel0 <= 1'd0; + end + 2'd2: begin + soc_litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel0 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel1 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel1 <= 1'd0; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel1 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end +assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); +assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12; +assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13; +assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14; +assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); +assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15; +assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16; +assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17; +assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); +assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18; +assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19; +assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20; +assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); +assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21; +assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22; +assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23; +assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); +assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24; +assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25; +assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26; +assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); +assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27; +assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28; +assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29; +assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); +assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30; +assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31; +assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32; +assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); +assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33; +assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34; +assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35; +assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); +assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2; +assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8; + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_wdata <= 256'd0; + case ({vns_new_master_wdata_ready2}) + 1'd1: begin + soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; + end + default: begin + soc_litedramcore_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_wdata_we <= 32'd0; + case ({vns_new_master_wdata_ready2}) + 1'd1: begin + soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; + end + default: begin + soc_litedramcore_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end +assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; +assign vns_roundrobin0_grant = 1'd0; +assign vns_roundrobin1_grant = 1'd0; +assign vns_roundrobin2_grant = 1'd0; +assign vns_roundrobin3_grant = 1'd0; +assign vns_roundrobin4_grant = 1'd0; +assign vns_roundrobin5_grant = 1'd0; +assign vns_roundrobin6_grant = 1'd0; +assign vns_roundrobin7_grant = 1'd0; +assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr; +assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; +assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r; +assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel; +assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc; +assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb; +assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack; +assign soc_litedramcore_wishbone_we = soc_wb_bus_we; +assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti; +assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte; +assign soc_wb_bus_err = soc_litedramcore_wishbone_err; +assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2); +assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0]; +assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0]; +assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank0_init_done0_w = soc_init_done_storage; +assign vns_csrbank0_init_error0_w = soc_init_error_storage; +assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0); +assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0]; +assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0]; +assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); +assign soc_k7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); +assign soc_k7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); +assign soc_k7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); +assign soc_k7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); +assign soc_k7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); +assign soc_k7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[3:0]; +assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); +assign soc_k7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); +assign soc_k7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); +assign soc_k7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); +assign soc_k7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); +assign soc_k7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); +assign soc_k7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); +assign soc_k7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); +assign soc_k7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); +assign soc_k7ddrphy_wdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_wdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd10)); +assign soc_k7ddrphy_wdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd10)); +assign soc_k7ddrphy_wdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_wdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd11)); +assign soc_k7ddrphy_wdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd11)); +assign soc_k7ddrphy_wdly_dqs_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_wdly_dqs_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd12)); +assign soc_k7ddrphy_wdly_dqs_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd12)); +assign soc_k7ddrphy_wdly_dqs_inc_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_k7ddrphy_wdly_dqs_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd13)); +assign soc_k7ddrphy_wdly_dqs_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd13)); +assign vns_csrbank1_half_sys8x_taps0_w = soc_k7ddrphy_half_sys8x_taps_storage[4:0]; +assign vns_csrbank1_wlevel_en0_w = soc_k7ddrphy_wlevel_en_storage; +assign vns_csrbank1_dly_sel0_w = soc_k7ddrphy_dly_sel_storage[3:0]; +assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1); +assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0]; +assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 1'd0)); +assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 1'd0)); +assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 1'd1)); +assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 1'd1)); +assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 2'd2)); +assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 2'd2)); +assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[14:0]; +assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 2'd3)); +assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 2'd3)); +assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd4)); +assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd4)); +assign vns_csrbank2_dfii_pi0_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi0_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd5)); +assign vns_csrbank2_dfii_pi0_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd5)); +assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd6)); +assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd6)); +assign vns_csrbank2_dfii_pi0_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi0_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 3'd7)); +assign vns_csrbank2_dfii_pi0_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 3'd7)); +assign vns_csrbank2_dfii_pi0_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi0_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd8)); +assign vns_csrbank2_dfii_pi0_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd8)); +assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd9)); +assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd9)); +assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd10)); +assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd10)); +assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[14:0]; +assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd11)); +assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd11)); +assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd12)); +assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd12)); +assign vns_csrbank2_dfii_pi1_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi1_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd13)); +assign vns_csrbank2_dfii_pi1_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd13)); +assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd14)); +assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd14)); +assign vns_csrbank2_dfii_pi1_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi1_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 4'd15)); +assign vns_csrbank2_dfii_pi1_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 4'd15)); +assign vns_csrbank2_dfii_pi1_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi1_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd16)); +assign vns_csrbank2_dfii_pi1_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd16)); +assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd17)); +assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd17)); +assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd18)); +assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd18)); +assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[14:0]; +assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd19)); +assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd19)); +assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd20)); +assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd20)); +assign vns_csrbank2_dfii_pi2_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi2_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd21)); +assign vns_csrbank2_dfii_pi2_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd21)); +assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd22)); +assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd22)); +assign vns_csrbank2_dfii_pi2_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi2_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd23)); +assign vns_csrbank2_dfii_pi2_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd23)); +assign vns_csrbank2_dfii_pi2_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi2_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd24)); +assign vns_csrbank2_dfii_pi2_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd24)); +assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd25)); +assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd25)); +assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd26)); +assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd26)); +assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[14:0]; +assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd27)); +assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd27)); +assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd28)); +assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd28)); +assign vns_csrbank2_dfii_pi3_wrdata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi3_wrdata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd29)); +assign vns_csrbank2_dfii_pi3_wrdata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd29)); +assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd30)); +assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd30)); +assign vns_csrbank2_dfii_pi3_rddata1_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi3_rddata1_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 5'd31)); +assign vns_csrbank2_dfii_pi3_rddata1_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 5'd31)); +assign vns_csrbank2_dfii_pi3_rddata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi3_rddata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[5:0] == 6'd32)); +assign vns_csrbank2_dfii_pi3_rddata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[5:0] == 6'd32)); +assign soc_litedramcore_sel = soc_litedramcore_storage[0]; +assign soc_litedramcore_cke = soc_litedramcore_storage[1]; +assign soc_litedramcore_odt = soc_litedramcore_storage[2]; +assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; +assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0]; +assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; +assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[14:0]; +assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi0_wrdata1_w = soc_litedramcore_phaseinjector0_wrdata_storage[63:32]; +assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi0_rddata1_w = soc_litedramcore_phaseinjector0_status[63:32]; +assign vns_csrbank2_dfii_pi0_rddata0_w = soc_litedramcore_phaseinjector0_status[31:0]; +assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata0_we; +assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; +assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[14:0]; +assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi1_wrdata1_w = soc_litedramcore_phaseinjector1_wrdata_storage[63:32]; +assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi1_rddata1_w = soc_litedramcore_phaseinjector1_status[63:32]; +assign vns_csrbank2_dfii_pi1_rddata0_w = soc_litedramcore_phaseinjector1_status[31:0]; +assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata0_we; +assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; +assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[14:0]; +assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi2_wrdata1_w = soc_litedramcore_phaseinjector2_wrdata_storage[63:32]; +assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi2_rddata1_w = soc_litedramcore_phaseinjector2_status[63:32]; +assign vns_csrbank2_dfii_pi2_rddata0_w = soc_litedramcore_phaseinjector2_status[31:0]; +assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata0_we; +assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; +assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[14:0]; +assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi3_wrdata1_w = soc_litedramcore_phaseinjector3_wrdata_storage[63:32]; +assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi3_rddata1_w = soc_litedramcore_phaseinjector3_status[63:32]; +assign vns_csrbank2_dfii_pi3_rddata0_w = soc_litedramcore_phaseinjector3_status[31:0]; +assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata0_we; +assign vns_adr = soc_litedramcore_adr; +assign vns_we = soc_litedramcore_we; +assign vns_dat_w = soc_litedramcore_dat_w; +assign soc_litedramcore_dat_r = vns_dat_r; +assign vns_interface0_bank_bus_adr = vns_adr; +assign vns_interface1_bank_bus_adr = vns_adr; +assign vns_interface2_bank_bus_adr = vns_adr; +assign vns_interface0_bank_bus_we = vns_we; +assign vns_interface1_bank_bus_we = vns_we; +assign vns_interface2_bank_bus_we = vns_we; +assign vns_interface0_bank_bus_dat_w = vns_dat_w; +assign vns_interface1_bank_bus_dat_w = vns_dat_w; +assign vns_interface2_bank_bus_dat_w = vns_dat_w; +assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed0 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + end + default: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed1 <= 15'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed2 <= 3'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed3 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed4 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_306 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed5 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed0 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed1 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed2 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed6 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + end + default: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed7 <= 15'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed8 <= 3'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed9 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed10 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed11 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed3 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed4 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed5 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed12 <= 22'd0; + case (vns_roundrobin0_grant) + default: begin + vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed13 <= 1'd0; + case (vns_roundrobin0_grant) + default: begin + vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed14 <= 1'd0; + case (vns_roundrobin0_grant) + default: begin + vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed15 <= 22'd0; + case (vns_roundrobin1_grant) + default: begin + vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed16 <= 1'd0; + case (vns_roundrobin1_grant) + default: begin + vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed17 <= 1'd0; + case (vns_roundrobin1_grant) + default: begin + vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed18 <= 22'd0; + case (vns_roundrobin2_grant) + default: begin + vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed19 <= 1'd0; + case (vns_roundrobin2_grant) + default: begin + vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed20 <= 1'd0; + case (vns_roundrobin2_grant) + default: begin + vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed21 <= 22'd0; + case (vns_roundrobin3_grant) + default: begin + vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed22 <= 1'd0; + case (vns_roundrobin3_grant) + default: begin + vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed23 <= 1'd0; + case (vns_roundrobin3_grant) + default: begin + vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed24 <= 22'd0; + case (vns_roundrobin4_grant) + default: begin + vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed25 <= 1'd0; + case (vns_roundrobin4_grant) + default: begin + vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed26 <= 1'd0; + case (vns_roundrobin4_grant) + default: begin + vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed27 <= 22'd0; + case (vns_roundrobin5_grant) + default: begin + vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed28 <= 1'd0; + case (vns_roundrobin5_grant) + default: begin + vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed29 <= 1'd0; + case (vns_roundrobin5_grant) + default: begin + vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed30 <= 22'd0; + case (vns_roundrobin6_grant) + default: begin + vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed31 <= 1'd0; + case (vns_roundrobin6_grant) + default: begin + vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed32 <= 1'd0; + case (vns_roundrobin6_grant) + default: begin + vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed33 <= 22'd0; + case (vns_roundrobin7_grant) + default: begin + vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed34 <= 1'd0; + case (vns_roundrobin7_grant) + default: begin + vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed35 <= 1'd0; + case (vns_roundrobin7_grant) + default: begin + vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + vns_array_muxed0 <= 3'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + vns_array_muxed1 <= 15'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed1 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed1 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + vns_array_muxed2 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed2 <= 1'd0; + end + 1'd1: begin + vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + vns_array_muxed3 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed3 <= 1'd0; + end + 1'd1: begin + vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + vns_array_muxed4 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed4 <= 1'd0; + end + 1'd1: begin + vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + vns_array_muxed5 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed5 <= 1'd0; + end + 1'd1: begin + vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + vns_array_muxed6 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed6 <= 1'd0; + end + 1'd1: begin + vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + vns_array_muxed7 <= 3'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + vns_array_muxed8 <= 15'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed8 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed8 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + vns_array_muxed9 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed9 <= 1'd0; + end + 1'd1: begin + vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + vns_array_muxed10 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed10 <= 1'd0; + end + 1'd1: begin + vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + vns_array_muxed11 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed11 <= 1'd0; + end + 1'd1: begin + vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_356; +// synthesis translate_on +always @(*) begin + vns_array_muxed12 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed12 <= 1'd0; + end + 1'd1: begin + vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_356 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_357; +// synthesis translate_on +always @(*) begin + vns_array_muxed13 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed13 <= 1'd0; + end + 1'd1: begin + vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_357 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_358; +// synthesis translate_on +always @(*) begin + vns_array_muxed14 <= 3'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_358 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_359; +// synthesis translate_on +always @(*) begin + vns_array_muxed15 <= 15'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed15 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed15 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_359 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_360; +// synthesis translate_on +always @(*) begin + vns_array_muxed16 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed16 <= 1'd0; + end + 1'd1: begin + vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_360 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_361; +// synthesis translate_on +always @(*) begin + vns_array_muxed17 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed17 <= 1'd0; + end + 1'd1: begin + vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_361 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_362; +// synthesis translate_on +always @(*) begin + vns_array_muxed18 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed18 <= 1'd0; + end + 1'd1: begin + vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_362 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_363; +// synthesis translate_on +always @(*) begin + vns_array_muxed19 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed19 <= 1'd0; + end + 1'd1: begin + vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_363 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_364; +// synthesis translate_on +always @(*) begin + vns_array_muxed20 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed20 <= 1'd0; + end + 1'd1: begin + vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_364 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_365; +// synthesis translate_on +always @(*) begin + vns_array_muxed21 <= 3'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_365 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_366; +// synthesis translate_on +always @(*) begin + vns_array_muxed22 <= 15'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed22 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed22 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_366 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_367; +// synthesis translate_on +always @(*) begin + vns_array_muxed23 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed23 <= 1'd0; + end + 1'd1: begin + vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_367 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_368; +// synthesis translate_on +always @(*) begin + vns_array_muxed24 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed24 <= 1'd0; + end + 1'd1: begin + vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_368 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_369; +// synthesis translate_on +always @(*) begin + vns_array_muxed25 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed25 <= 1'd0; + end + 1'd1: begin + vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_369 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_370; +// synthesis translate_on +always @(*) begin + vns_array_muxed26 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed26 <= 1'd0; + end + 1'd1: begin + vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_370 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_371; +// synthesis translate_on +always @(*) begin + vns_array_muxed27 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed27 <= 1'd0; + end + 1'd1: begin + vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_371 = dummy_s; +// synthesis translate_on +end +assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset); +assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset); +assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset); +assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset); + +always @(posedge iodelay_clk) begin + if ((soc_reset_counter != 1'd0)) begin + soc_reset_counter <= (soc_reset_counter - 1'd1); + end else begin + soc_ic_reset <= 1'd0; + end + if (iodelay_rst) begin + soc_reset_counter <= 4'd15; + soc_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + vns_state <= vns_next_state; + soc_k7ddrphy_dqs_oe_delayed <= ((soc_k7ddrphy_dqspattern0 | soc_k7ddrphy_dqs_oe) | soc_k7ddrphy_dqspattern1); + soc_k7ddrphy_dq_oe_delayed <= ((soc_k7ddrphy_dqspattern0 | soc_k7ddrphy_dq_oe) | soc_k7ddrphy_dqspattern1); + soc_k7ddrphy_rddata_en_last <= soc_k7ddrphy_rddata_en; + soc_k7ddrphy_dfi_p0_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); + soc_k7ddrphy_dfi_p1_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); + soc_k7ddrphy_dfi_p2_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); + soc_k7ddrphy_dfi_p3_rddata_valid <= (soc_k7ddrphy_rddata_en[7] | soc_k7ddrphy_wlevel_en_storage); + soc_k7ddrphy_wrdata_en_last <= soc_k7ddrphy_wrdata_en; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip0_value <= (soc_k7ddrphy_bitslip0_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip0_value <= 1'd0; + end + soc_k7ddrphy_bitslip0_r <= {soc_k7ddrphy_bitslip0_i, soc_k7ddrphy_bitslip0_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip1_value <= (soc_k7ddrphy_bitslip1_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip1_value <= 1'd0; + end + soc_k7ddrphy_bitslip1_r <= {soc_k7ddrphy_bitslip1_i, soc_k7ddrphy_bitslip1_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip2_value <= (soc_k7ddrphy_bitslip2_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip2_value <= 1'd0; + end + soc_k7ddrphy_bitslip2_r <= {soc_k7ddrphy_bitslip2_i, soc_k7ddrphy_bitslip2_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip3_value <= (soc_k7ddrphy_bitslip3_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip3_value <= 1'd0; + end + soc_k7ddrphy_bitslip3_r <= {soc_k7ddrphy_bitslip3_i, soc_k7ddrphy_bitslip3_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip4_value <= (soc_k7ddrphy_bitslip4_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip4_value <= 1'd0; + end + soc_k7ddrphy_bitslip4_r <= {soc_k7ddrphy_bitslip4_i, soc_k7ddrphy_bitslip4_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip5_value <= (soc_k7ddrphy_bitslip5_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip5_value <= 1'd0; + end + soc_k7ddrphy_bitslip5_r <= {soc_k7ddrphy_bitslip5_i, soc_k7ddrphy_bitslip5_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip6_value <= (soc_k7ddrphy_bitslip6_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip6_value <= 1'd0; + end + soc_k7ddrphy_bitslip6_r <= {soc_k7ddrphy_bitslip6_i, soc_k7ddrphy_bitslip6_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip7_value <= (soc_k7ddrphy_bitslip7_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip7_value <= 1'd0; + end + soc_k7ddrphy_bitslip7_r <= {soc_k7ddrphy_bitslip7_i, soc_k7ddrphy_bitslip7_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip8_value <= (soc_k7ddrphy_bitslip8_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip8_value <= 1'd0; + end + soc_k7ddrphy_bitslip8_r <= {soc_k7ddrphy_bitslip8_i, soc_k7ddrphy_bitslip8_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip9_value <= (soc_k7ddrphy_bitslip9_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip9_value <= 1'd0; + end + soc_k7ddrphy_bitslip9_r <= {soc_k7ddrphy_bitslip9_i, soc_k7ddrphy_bitslip9_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip10_value <= (soc_k7ddrphy_bitslip10_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip10_value <= 1'd0; + end + soc_k7ddrphy_bitslip10_r <= {soc_k7ddrphy_bitslip10_i, soc_k7ddrphy_bitslip10_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip11_value <= (soc_k7ddrphy_bitslip11_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip11_value <= 1'd0; + end + soc_k7ddrphy_bitslip11_r <= {soc_k7ddrphy_bitslip11_i, soc_k7ddrphy_bitslip11_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip12_value <= (soc_k7ddrphy_bitslip12_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip12_value <= 1'd0; + end + soc_k7ddrphy_bitslip12_r <= {soc_k7ddrphy_bitslip12_i, soc_k7ddrphy_bitslip12_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip13_value <= (soc_k7ddrphy_bitslip13_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip13_value <= 1'd0; + end + soc_k7ddrphy_bitslip13_r <= {soc_k7ddrphy_bitslip13_i, soc_k7ddrphy_bitslip13_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip14_value <= (soc_k7ddrphy_bitslip14_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip14_value <= 1'd0; + end + soc_k7ddrphy_bitslip14_r <= {soc_k7ddrphy_bitslip14_i, soc_k7ddrphy_bitslip14_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip15_value <= (soc_k7ddrphy_bitslip15_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip15_value <= 1'd0; + end + soc_k7ddrphy_bitslip15_r <= {soc_k7ddrphy_bitslip15_i, soc_k7ddrphy_bitslip15_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip16_value <= (soc_k7ddrphy_bitslip16_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip16_value <= 1'd0; + end + soc_k7ddrphy_bitslip16_r <= {soc_k7ddrphy_bitslip16_i, soc_k7ddrphy_bitslip16_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip17_value <= (soc_k7ddrphy_bitslip17_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip17_value <= 1'd0; + end + soc_k7ddrphy_bitslip17_r <= {soc_k7ddrphy_bitslip17_i, soc_k7ddrphy_bitslip17_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip18_value <= (soc_k7ddrphy_bitslip18_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip18_value <= 1'd0; + end + soc_k7ddrphy_bitslip18_r <= {soc_k7ddrphy_bitslip18_i, soc_k7ddrphy_bitslip18_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip19_value <= (soc_k7ddrphy_bitslip19_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip19_value <= 1'd0; + end + soc_k7ddrphy_bitslip19_r <= {soc_k7ddrphy_bitslip19_i, soc_k7ddrphy_bitslip19_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip20_value <= (soc_k7ddrphy_bitslip20_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip20_value <= 1'd0; + end + soc_k7ddrphy_bitslip20_r <= {soc_k7ddrphy_bitslip20_i, soc_k7ddrphy_bitslip20_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip21_value <= (soc_k7ddrphy_bitslip21_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip21_value <= 1'd0; + end + soc_k7ddrphy_bitslip21_r <= {soc_k7ddrphy_bitslip21_i, soc_k7ddrphy_bitslip21_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip22_value <= (soc_k7ddrphy_bitslip22_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip22_value <= 1'd0; + end + soc_k7ddrphy_bitslip22_r <= {soc_k7ddrphy_bitslip22_i, soc_k7ddrphy_bitslip22_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip23_value <= (soc_k7ddrphy_bitslip23_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip23_value <= 1'd0; + end + soc_k7ddrphy_bitslip23_r <= {soc_k7ddrphy_bitslip23_i, soc_k7ddrphy_bitslip23_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip24_value <= (soc_k7ddrphy_bitslip24_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip24_value <= 1'd0; + end + soc_k7ddrphy_bitslip24_r <= {soc_k7ddrphy_bitslip24_i, soc_k7ddrphy_bitslip24_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip25_value <= (soc_k7ddrphy_bitslip25_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip25_value <= 1'd0; + end + soc_k7ddrphy_bitslip25_r <= {soc_k7ddrphy_bitslip25_i, soc_k7ddrphy_bitslip25_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip26_value <= (soc_k7ddrphy_bitslip26_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip26_value <= 1'd0; + end + soc_k7ddrphy_bitslip26_r <= {soc_k7ddrphy_bitslip26_i, soc_k7ddrphy_bitslip26_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip27_value <= (soc_k7ddrphy_bitslip27_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip27_value <= 1'd0; + end + soc_k7ddrphy_bitslip27_r <= {soc_k7ddrphy_bitslip27_i, soc_k7ddrphy_bitslip27_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip28_value <= (soc_k7ddrphy_bitslip28_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip28_value <= 1'd0; + end + soc_k7ddrphy_bitslip28_r <= {soc_k7ddrphy_bitslip28_i, soc_k7ddrphy_bitslip28_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip29_value <= (soc_k7ddrphy_bitslip29_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip29_value <= 1'd0; + end + soc_k7ddrphy_bitslip29_r <= {soc_k7ddrphy_bitslip29_i, soc_k7ddrphy_bitslip29_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip30_value <= (soc_k7ddrphy_bitslip30_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip30_value <= 1'd0; + end + soc_k7ddrphy_bitslip30_r <= {soc_k7ddrphy_bitslip30_i, soc_k7ddrphy_bitslip30_r[23:8]}; + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_re)) begin + soc_k7ddrphy_bitslip31_value <= (soc_k7ddrphy_bitslip31_value + 1'd1); + end + if ((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_k7ddrphy_bitslip31_value <= 1'd0; + end + soc_k7ddrphy_bitslip31_r <= {soc_k7ddrphy_bitslip31_i, soc_k7ddrphy_bitslip31_r[23:8]}; + if (soc_litedramcore_inti_p0_rddata_valid) begin + soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata; + end + if (soc_litedramcore_inti_p1_rddata_valid) begin + soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata; + end + if (soc_litedramcore_inti_p2_rddata_valid) begin + soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata; + end + if (soc_litedramcore_inti_p3_rddata_valid) begin + soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata; + end + if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin + soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + end else begin + soc_litedramcore_timer_count1 <= 10'd781; + end + soc_litedramcore_postponer_req_o <= 1'd0; + if (soc_litedramcore_postponer_req_i) begin + soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); + if ((soc_litedramcore_postponer_count == 1'd0)) begin + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_postponer_req_o <= 1'd1; + end + end + if (soc_litedramcore_sequencer_start0) begin + soc_litedramcore_sequencer_count <= 1'd0; + end else begin + if (soc_litedramcore_sequencer_done1) begin + if ((soc_litedramcore_sequencer_count != 1'd0)) begin + soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); + end + end + end + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_sequencer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd1; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd0; + end + if ((soc_litedramcore_sequencer_counter == 6'd55)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd1; + end + if ((soc_litedramcore_sequencer_counter == 6'd55)) begin + soc_litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((soc_litedramcore_sequencer_counter != 1'd0)) begin + soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + end else begin + if (soc_litedramcore_sequencer_start1) begin + soc_litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin + soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + soc_litedramcore_zqcs_executer_done <= 1'd0; + if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin + soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (soc_litedramcore_zqcs_executer_start) begin + soc_litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + vns_refresher_state <= vns_refresher_next_state; + if (soc_litedramcore_bankmachine0_row_close) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine0_row_open) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd1; + soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; + soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine0_twtpcon_valid) begin + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin + soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trccon_valid) begin + soc_litedramcore_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin + soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trascon_valid) begin + soc_litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine0_state <= vns_bankmachine0_next_state; + if (soc_litedramcore_bankmachine1_row_close) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine1_row_open) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd1; + soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; + soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine1_twtpcon_valid) begin + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin + soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trccon_valid) begin + soc_litedramcore_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin + soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trascon_valid) begin + soc_litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine1_state <= vns_bankmachine1_next_state; + if (soc_litedramcore_bankmachine2_row_close) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine2_row_open) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd1; + soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; + soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine2_twtpcon_valid) begin + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin + soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trccon_valid) begin + soc_litedramcore_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin + soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trascon_valid) begin + soc_litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine2_state <= vns_bankmachine2_next_state; + if (soc_litedramcore_bankmachine3_row_close) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine3_row_open) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd1; + soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; + soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine3_twtpcon_valid) begin + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin + soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trccon_valid) begin + soc_litedramcore_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin + soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trascon_valid) begin + soc_litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine3_state <= vns_bankmachine3_next_state; + if (soc_litedramcore_bankmachine4_row_close) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine4_row_open) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd1; + soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; + soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine4_twtpcon_valid) begin + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin + soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trccon_valid) begin + soc_litedramcore_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin + soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trascon_valid) begin + soc_litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine4_state <= vns_bankmachine4_next_state; + if (soc_litedramcore_bankmachine5_row_close) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine5_row_open) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd1; + soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; + soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine5_twtpcon_valid) begin + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin + soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trccon_valid) begin + soc_litedramcore_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin + soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trascon_valid) begin + soc_litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine5_state <= vns_bankmachine5_next_state; + if (soc_litedramcore_bankmachine6_row_close) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine6_row_open) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd1; + soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; + soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine6_twtpcon_valid) begin + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin + soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trccon_valid) begin + soc_litedramcore_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin + soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trascon_valid) begin + soc_litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine6_state <= vns_bankmachine6_next_state; + if (soc_litedramcore_bankmachine7_row_close) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine7_row_open) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd1; + soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; + soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine7_twtpcon_valid) begin + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin + soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trccon_valid) begin + soc_litedramcore_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin + soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trascon_valid) begin + soc_litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine7_state <= vns_bankmachine7_next_state; + if ((~soc_litedramcore_en0)) begin + soc_litedramcore_time0 <= 5'd31; + end else begin + if ((~soc_litedramcore_max_time0)) begin + soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + end + end + if ((~soc_litedramcore_en1)) begin + soc_litedramcore_time1 <= 4'd15; + end else begin + if ((~soc_litedramcore_max_time1)) begin + soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + end + end + if (soc_litedramcore_choose_cmd_ce) begin + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (soc_litedramcore_choose_req_ce) begin + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + soc_litedramcore_dfi_p0_cs_n <= 1'd0; + soc_litedramcore_dfi_p0_bank <= vns_array_muxed0; + soc_litedramcore_dfi_p0_address <= vns_array_muxed1; + soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2); + soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3); + soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4); + soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5; + soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6; + soc_litedramcore_dfi_p1_cs_n <= 1'd0; + soc_litedramcore_dfi_p1_bank <= vns_array_muxed7; + soc_litedramcore_dfi_p1_address <= vns_array_muxed8; + soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9); + soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10); + soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11); + soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12; + soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13; + soc_litedramcore_dfi_p2_cs_n <= 1'd0; + soc_litedramcore_dfi_p2_bank <= vns_array_muxed14; + soc_litedramcore_dfi_p2_address <= vns_array_muxed15; + soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16); + soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17); + soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18); + soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19; + soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20; + soc_litedramcore_dfi_p3_cs_n <= 1'd0; + soc_litedramcore_dfi_p3_bank <= vns_array_muxed21; + soc_litedramcore_dfi_p3_address <= vns_array_muxed22; + soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23); + soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24); + soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25); + soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26; + soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27; + if (soc_litedramcore_trrdcon_valid) begin + soc_litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end else begin + soc_litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_trrdcon_ready)) begin + soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); + if ((soc_litedramcore_trrdcon_count == 1'd1)) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end + end + end + soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; + if ((soc_litedramcore_tfawcon_count < 3'd4)) begin + if ((soc_litedramcore_tfawcon_count == 2'd3)) begin + soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + end else begin + soc_litedramcore_tfawcon_ready <= 1'd1; + end + end + if (soc_litedramcore_tccdcon_valid) begin + soc_litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end else begin + soc_litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_tccdcon_ready)) begin + soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); + if ((soc_litedramcore_tccdcon_count == 1'd1)) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_twtrcon_valid) begin + soc_litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end else begin + soc_litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_twtrcon_ready)) begin + soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); + if ((soc_litedramcore_twtrcon_count == 1'd1)) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + vns_multiplexer_state <= vns_multiplexer_next_state; + vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); + vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; + vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; + vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); + vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; + vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; + vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; + vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; + vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; + vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; + vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; + vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; + vns_interface0_bank_bus_dat_r <= 1'd0; + if (vns_csrbank0_sel) begin + case (vns_interface0_bank_bus_adr[0]) + 1'd0: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w; + end + 1'd1: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w; + end + endcase + end + if (vns_csrbank0_init_done0_re) begin + soc_init_done_storage <= vns_csrbank0_init_done0_r; + end + soc_init_done_re <= vns_csrbank0_init_done0_re; + if (vns_csrbank0_init_error0_re) begin + soc_init_error_storage <= vns_csrbank0_init_error0_r; + end + soc_init_error_re <= vns_csrbank0_init_error0_re; + vns_interface1_bank_bus_dat_r <= 1'd0; + if (vns_csrbank1_sel) begin + case (vns_interface1_bank_bus_adr[3:0]) + 1'd0: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w; + end + 1'd1: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w; + end + 2'd2: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wlevel_strobe_w; + end + 2'd3: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_cdly_rst_w; + end + 3'd4: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_cdly_inc_w; + end + 3'd5: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w; + end + 3'd6: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_rst_w; + end + 3'd7: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_inc_w; + end + 4'd8: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd9: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_rdly_dq_bitslip_w; + end + 4'd10: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dq_rst_w; + end + 4'd11: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dq_inc_w; + end + 4'd12: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dqs_rst_w; + end + 4'd13: begin + vns_interface1_bank_bus_dat_r <= soc_k7ddrphy_wdly_dqs_inc_w; + end + endcase + end + if (vns_csrbank1_half_sys8x_taps0_re) begin + soc_k7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r; + end + soc_k7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re; + if (vns_csrbank1_wlevel_en0_re) begin + soc_k7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r; + end + soc_k7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re; + if (vns_csrbank1_dly_sel0_re) begin + soc_k7ddrphy_dly_sel_storage[3:0] <= vns_csrbank1_dly_sel0_r; + end + soc_k7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re; + vns_interface2_bank_bus_dat_r <= 1'd0; + if (vns_csrbank2_sel) begin + case (vns_interface2_bank_bus_adr[5:0]) + 1'd0: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w; + end + 1'd1: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata1_w; + end + 3'd6: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w; + end + 3'd7: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata1_w; + end + 4'd8: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata0_w; + end + 4'd9: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w; + end + 4'd10: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + end + 4'd11: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w; + end + 4'd12: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w; + end + 4'd13: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata1_w; + end + 4'd14: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w; + end + 4'd15: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata1_w; + end + 5'd16: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata0_w; + end + 5'd17: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w; + end + 5'd18: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + end + 5'd19: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w; + end + 5'd20: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w; + end + 5'd21: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata1_w; + end + 5'd22: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w; + end + 5'd23: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata1_w; + end + 5'd24: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata0_w; + end + 5'd25: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w; + end + 5'd26: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + end + 5'd27: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w; + end + 5'd28: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w; + end + 5'd29: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata1_w; + end + 5'd30: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w; + end + 5'd31: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata1_w; + end + 6'd32: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata0_w; + end + endcase + end + if (vns_csrbank2_dfii_control0_re) begin + soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r; + end + soc_litedramcore_re <= vns_csrbank2_dfii_control0_re; + if (vns_csrbank2_dfii_pi0_command0_re) begin + soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r; + end + soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re; + if (vns_csrbank2_dfii_pi0_address0_re) begin + soc_litedramcore_phaseinjector0_address_storage[14:0] <= vns_csrbank2_dfii_pi0_address0_r; + end + soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re; + if (vns_csrbank2_dfii_pi0_baddress0_re) begin + soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r; + end + soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re; + if (vns_csrbank2_dfii_pi0_wrdata1_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi0_wrdata1_r; + end + if (vns_csrbank2_dfii_pi0_wrdata0_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r; + end + soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re; + if (vns_csrbank2_dfii_pi1_command0_re) begin + soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r; + end + soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re; + if (vns_csrbank2_dfii_pi1_address0_re) begin + soc_litedramcore_phaseinjector1_address_storage[14:0] <= vns_csrbank2_dfii_pi1_address0_r; + end + soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re; + if (vns_csrbank2_dfii_pi1_baddress0_re) begin + soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r; + end + soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re; + if (vns_csrbank2_dfii_pi1_wrdata1_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi1_wrdata1_r; + end + if (vns_csrbank2_dfii_pi1_wrdata0_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r; + end + soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re; + if (vns_csrbank2_dfii_pi2_command0_re) begin + soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r; + end + soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re; + if (vns_csrbank2_dfii_pi2_address0_re) begin + soc_litedramcore_phaseinjector2_address_storage[14:0] <= vns_csrbank2_dfii_pi2_address0_r; + end + soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re; + if (vns_csrbank2_dfii_pi2_baddress0_re) begin + soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r; + end + soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re; + if (vns_csrbank2_dfii_pi2_wrdata1_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi2_wrdata1_r; + end + if (vns_csrbank2_dfii_pi2_wrdata0_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r; + end + soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re; + if (vns_csrbank2_dfii_pi3_command0_re) begin + soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r; + end + soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re; + if (vns_csrbank2_dfii_pi3_address0_re) begin + soc_litedramcore_phaseinjector3_address_storage[14:0] <= vns_csrbank2_dfii_pi3_address0_r; + end + soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re; + if (vns_csrbank2_dfii_pi3_baddress0_re) begin + soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r; + end + soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re; + if (vns_csrbank2_dfii_pi3_wrdata1_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage[63:32] <= vns_csrbank2_dfii_pi3_wrdata1_r; + end + if (vns_csrbank2_dfii_pi3_wrdata0_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r; + end + soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re; + if (sys_rst) begin + soc_k7ddrphy_half_sys8x_taps_storage <= 5'd8; + soc_k7ddrphy_half_sys8x_taps_re <= 1'd0; + soc_k7ddrphy_wlevel_en_storage <= 1'd0; + soc_k7ddrphy_wlevel_en_re <= 1'd0; + soc_k7ddrphy_dly_sel_storage <= 4'd0; + soc_k7ddrphy_dly_sel_re <= 1'd0; + soc_k7ddrphy_dfi_p0_rddata_valid <= 1'd0; + soc_k7ddrphy_dfi_p1_rddata_valid <= 1'd0; + soc_k7ddrphy_dfi_p2_rddata_valid <= 1'd0; + soc_k7ddrphy_dfi_p3_rddata_valid <= 1'd0; + soc_k7ddrphy_dqs_oe_delayed <= 1'd0; + soc_k7ddrphy_dq_oe_delayed <= 1'd0; + soc_k7ddrphy_bitslip0_value <= 4'd0; + soc_k7ddrphy_bitslip1_value <= 4'd0; + soc_k7ddrphy_bitslip2_value <= 4'd0; + soc_k7ddrphy_bitslip3_value <= 4'd0; + soc_k7ddrphy_bitslip4_value <= 4'd0; + soc_k7ddrphy_bitslip5_value <= 4'd0; + soc_k7ddrphy_bitslip6_value <= 4'd0; + soc_k7ddrphy_bitslip7_value <= 4'd0; + soc_k7ddrphy_bitslip8_value <= 4'd0; + soc_k7ddrphy_bitslip9_value <= 4'd0; + soc_k7ddrphy_bitslip10_value <= 4'd0; + soc_k7ddrphy_bitslip11_value <= 4'd0; + soc_k7ddrphy_bitslip12_value <= 4'd0; + soc_k7ddrphy_bitslip13_value <= 4'd0; + soc_k7ddrphy_bitslip14_value <= 4'd0; + soc_k7ddrphy_bitslip15_value <= 4'd0; + soc_k7ddrphy_bitslip16_value <= 4'd0; + soc_k7ddrphy_bitslip17_value <= 4'd0; + soc_k7ddrphy_bitslip18_value <= 4'd0; + soc_k7ddrphy_bitslip19_value <= 4'd0; + soc_k7ddrphy_bitslip20_value <= 4'd0; + soc_k7ddrphy_bitslip21_value <= 4'd0; + soc_k7ddrphy_bitslip22_value <= 4'd0; + soc_k7ddrphy_bitslip23_value <= 4'd0; + soc_k7ddrphy_bitslip24_value <= 4'd0; + soc_k7ddrphy_bitslip25_value <= 4'd0; + soc_k7ddrphy_bitslip26_value <= 4'd0; + soc_k7ddrphy_bitslip27_value <= 4'd0; + soc_k7ddrphy_bitslip28_value <= 4'd0; + soc_k7ddrphy_bitslip29_value <= 4'd0; + soc_k7ddrphy_bitslip30_value <= 4'd0; + soc_k7ddrphy_bitslip31_value <= 4'd0; + soc_k7ddrphy_rddata_en_last <= 8'd0; + soc_k7ddrphy_wrdata_en_last <= 4'd0; + soc_litedramcore_storage <= 4'd1; + soc_litedramcore_re <= 1'd0; + soc_litedramcore_phaseinjector0_command_storage <= 6'd0; + soc_litedramcore_phaseinjector0_command_re <= 1'd0; + soc_litedramcore_phaseinjector0_address_re <= 1'd0; + soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector0_status <= 64'd0; + soc_litedramcore_phaseinjector1_command_storage <= 6'd0; + soc_litedramcore_phaseinjector1_command_re <= 1'd0; + soc_litedramcore_phaseinjector1_address_re <= 1'd0; + soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector1_status <= 64'd0; + soc_litedramcore_phaseinjector2_command_storage <= 6'd0; + soc_litedramcore_phaseinjector2_command_re <= 1'd0; + soc_litedramcore_phaseinjector2_address_re <= 1'd0; + soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector2_status <= 64'd0; + soc_litedramcore_phaseinjector3_command_storage <= 6'd0; + soc_litedramcore_phaseinjector3_command_re <= 1'd0; + soc_litedramcore_phaseinjector3_address_re <= 1'd0; + soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector3_status <= 64'd0; + soc_litedramcore_dfi_p0_address <= 15'd0; + soc_litedramcore_dfi_p0_bank <= 3'd0; + soc_litedramcore_dfi_p0_cas_n <= 1'd1; + soc_litedramcore_dfi_p0_cs_n <= 1'd1; + soc_litedramcore_dfi_p0_ras_n <= 1'd1; + soc_litedramcore_dfi_p0_we_n <= 1'd1; + soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p0_rddata_en <= 1'd0; + soc_litedramcore_dfi_p1_address <= 15'd0; + soc_litedramcore_dfi_p1_bank <= 3'd0; + soc_litedramcore_dfi_p1_cas_n <= 1'd1; + soc_litedramcore_dfi_p1_cs_n <= 1'd1; + soc_litedramcore_dfi_p1_ras_n <= 1'd1; + soc_litedramcore_dfi_p1_we_n <= 1'd1; + soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p1_rddata_en <= 1'd0; + soc_litedramcore_dfi_p2_address <= 15'd0; + soc_litedramcore_dfi_p2_bank <= 3'd0; + soc_litedramcore_dfi_p2_cas_n <= 1'd1; + soc_litedramcore_dfi_p2_cs_n <= 1'd1; + soc_litedramcore_dfi_p2_ras_n <= 1'd1; + soc_litedramcore_dfi_p2_we_n <= 1'd1; + soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p2_rddata_en <= 1'd0; + soc_litedramcore_dfi_p3_address <= 15'd0; + soc_litedramcore_dfi_p3_bank <= 3'd0; + soc_litedramcore_dfi_p3_cas_n <= 1'd1; + soc_litedramcore_dfi_p3_cs_n <= 1'd1; + soc_litedramcore_dfi_p3_ras_n <= 1'd1; + soc_litedramcore_dfi_p3_we_n <= 1'd1; + soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p3_rddata_en <= 1'd0; + soc_litedramcore_timer_count1 <= 10'd781; + soc_litedramcore_postponer_req_o <= 1'd0; + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + soc_litedramcore_sequencer_counter <= 6'd0; + soc_litedramcore_sequencer_count <= 1'd0; + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; + soc_litedramcore_zqcs_executer_done <= 1'd0; + soc_litedramcore_zqcs_executer_counter <= 5'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine0_row <= 15'd0; + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trccon_count <= 3'd0; + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trascon_count <= 3'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine1_row <= 15'd0; + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trccon_count <= 3'd0; + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trascon_count <= 3'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine2_row <= 15'd0; + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trccon_count <= 3'd0; + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trascon_count <= 3'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine3_row <= 15'd0; + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trccon_count <= 3'd0; + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trascon_count <= 3'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine4_row <= 15'd0; + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trccon_count <= 3'd0; + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trascon_count <= 3'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine5_row <= 15'd0; + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trccon_count <= 3'd0; + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trascon_count <= 3'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine6_row <= 15'd0; + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trccon_count <= 3'd0; + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trascon_count <= 3'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine7_row <= 15'd0; + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trccon_count <= 3'd0; + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trascon_count <= 3'd0; + soc_litedramcore_choose_cmd_grant <= 3'd0; + soc_litedramcore_choose_req_grant <= 3'd0; + soc_litedramcore_trrdcon_ready <= 1'd0; + soc_litedramcore_trrdcon_count <= 1'd0; + soc_litedramcore_tfawcon_ready <= 1'd1; + soc_litedramcore_tfawcon_window <= 5'd0; + soc_litedramcore_tccdcon_ready <= 1'd0; + soc_litedramcore_tccdcon_count <= 1'd0; + soc_litedramcore_twtrcon_ready <= 1'd0; + soc_litedramcore_twtrcon_count <= 3'd0; + soc_litedramcore_time0 <= 5'd0; + soc_litedramcore_time1 <= 4'd0; + soc_init_done_storage <= 1'd0; + soc_init_done_re <= 1'd0; + soc_init_error_storage <= 1'd0; + soc_init_error_re <= 1'd0; + vns_state <= 1'd0; + vns_refresher_state <= 2'd0; + vns_bankmachine0_state <= 4'd0; + vns_bankmachine1_state <= 4'd0; + vns_bankmachine2_state <= 4'd0; + vns_bankmachine3_state <= 4'd0; + vns_bankmachine4_state <= 4'd0; + vns_bankmachine5_state <= 4'd0; + vns_bankmachine6_state <= 4'd0; + vns_bankmachine7_state <= 4'd0; + vns_multiplexer_state <= 4'd0; + vns_new_master_wdata_ready0 <= 1'd0; + vns_new_master_wdata_ready1 <= 1'd0; + vns_new_master_wdata_ready2 <= 1'd0; + vns_new_master_rdata_valid0 <= 1'd0; + vns_new_master_rdata_valid1 <= 1'd0; + vns_new_master_rdata_valid2 <= 1'd0; + vns_new_master_rdata_valid3 <= 1'd0; + vns_new_master_rdata_valid4 <= 1'd0; + vns_new_master_rdata_valid5 <= 1'd0; + vns_new_master_rdata_valid6 <= 1'd0; + vns_new_master_rdata_valid7 <= 1'd0; + vns_new_master_rdata_valid8 <= 1'd0; + end +end + +BUFG BUFG( + .I(soc_clkout0), + .O(soc_clkout_buf0) +); + +BUFG BUFG_1( + .I(soc_clkout1), + .O(soc_clkout_buf1) +); + +BUFG BUFG_2( + .I(soc_clkout2), + .O(soc_clkout_buf2) +); + +BUFG BUFG_3( + .I(soc_clkout3), + .O(soc_clkout_buf3) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(iodelay_clk), + .RST(soc_ic_reset) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(1'd0), + .D2(1'd1), + .D3(1'd0), + .D4(1'd1), + .D5(1'd0), + .D6(1'd1), + .D7(1'd0), + .D8(1'd1), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_sd_clk_se_nodelay) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_sd_clk_se_delayed), + .ODATAIN(soc_k7ddrphy_sd_clk_se_nodelay) +); + +OBUFDS OBUFDS( + .I(soc_k7ddrphy_sd_clk_se_delayed), + .O(ddram_clk_p), + .OB(ddram_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_1 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[0]), + .D2(soc_k7ddrphy_dfi_p0_address[0]), + .D3(soc_k7ddrphy_dfi_p1_address[0]), + .D4(soc_k7ddrphy_dfi_p1_address[0]), + .D5(soc_k7ddrphy_dfi_p2_address[0]), + .D6(soc_k7ddrphy_dfi_p2_address[0]), + .D7(soc_k7ddrphy_dfi_p3_address[0]), + .D8(soc_k7ddrphy_dfi_p3_address[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address0) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_1 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[0]), + .ODATAIN(soc_k7ddrphy_address0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[1]), + .D2(soc_k7ddrphy_dfi_p0_address[1]), + .D3(soc_k7ddrphy_dfi_p1_address[1]), + .D4(soc_k7ddrphy_dfi_p1_address[1]), + .D5(soc_k7ddrphy_dfi_p2_address[1]), + .D6(soc_k7ddrphy_dfi_p2_address[1]), + .D7(soc_k7ddrphy_dfi_p3_address[1]), + .D8(soc_k7ddrphy_dfi_p3_address[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address1) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_2 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[1]), + .ODATAIN(soc_k7ddrphy_address1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_3 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[2]), + .D2(soc_k7ddrphy_dfi_p0_address[2]), + .D3(soc_k7ddrphy_dfi_p1_address[2]), + .D4(soc_k7ddrphy_dfi_p1_address[2]), + .D5(soc_k7ddrphy_dfi_p2_address[2]), + .D6(soc_k7ddrphy_dfi_p2_address[2]), + .D7(soc_k7ddrphy_dfi_p3_address[2]), + .D8(soc_k7ddrphy_dfi_p3_address[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address2) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_3 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[2]), + .ODATAIN(soc_k7ddrphy_address2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_4 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[3]), + .D2(soc_k7ddrphy_dfi_p0_address[3]), + .D3(soc_k7ddrphy_dfi_p1_address[3]), + .D4(soc_k7ddrphy_dfi_p1_address[3]), + .D5(soc_k7ddrphy_dfi_p2_address[3]), + .D6(soc_k7ddrphy_dfi_p2_address[3]), + .D7(soc_k7ddrphy_dfi_p3_address[3]), + .D8(soc_k7ddrphy_dfi_p3_address[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address3) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_4 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[3]), + .ODATAIN(soc_k7ddrphy_address3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_5 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[4]), + .D2(soc_k7ddrphy_dfi_p0_address[4]), + .D3(soc_k7ddrphy_dfi_p1_address[4]), + .D4(soc_k7ddrphy_dfi_p1_address[4]), + .D5(soc_k7ddrphy_dfi_p2_address[4]), + .D6(soc_k7ddrphy_dfi_p2_address[4]), + .D7(soc_k7ddrphy_dfi_p3_address[4]), + .D8(soc_k7ddrphy_dfi_p3_address[4]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address4) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_5 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[4]), + .ODATAIN(soc_k7ddrphy_address4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_6 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[5]), + .D2(soc_k7ddrphy_dfi_p0_address[5]), + .D3(soc_k7ddrphy_dfi_p1_address[5]), + .D4(soc_k7ddrphy_dfi_p1_address[5]), + .D5(soc_k7ddrphy_dfi_p2_address[5]), + .D6(soc_k7ddrphy_dfi_p2_address[5]), + .D7(soc_k7ddrphy_dfi_p3_address[5]), + .D8(soc_k7ddrphy_dfi_p3_address[5]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address5) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_6 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[5]), + .ODATAIN(soc_k7ddrphy_address5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_7 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[6]), + .D2(soc_k7ddrphy_dfi_p0_address[6]), + .D3(soc_k7ddrphy_dfi_p1_address[6]), + .D4(soc_k7ddrphy_dfi_p1_address[6]), + .D5(soc_k7ddrphy_dfi_p2_address[6]), + .D6(soc_k7ddrphy_dfi_p2_address[6]), + .D7(soc_k7ddrphy_dfi_p3_address[6]), + .D8(soc_k7ddrphy_dfi_p3_address[6]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address6) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_7 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[6]), + .ODATAIN(soc_k7ddrphy_address6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_8 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[7]), + .D2(soc_k7ddrphy_dfi_p0_address[7]), + .D3(soc_k7ddrphy_dfi_p1_address[7]), + .D4(soc_k7ddrphy_dfi_p1_address[7]), + .D5(soc_k7ddrphy_dfi_p2_address[7]), + .D6(soc_k7ddrphy_dfi_p2_address[7]), + .D7(soc_k7ddrphy_dfi_p3_address[7]), + .D8(soc_k7ddrphy_dfi_p3_address[7]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address7) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_8 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[7]), + .ODATAIN(soc_k7ddrphy_address7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_9 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[8]), + .D2(soc_k7ddrphy_dfi_p0_address[8]), + .D3(soc_k7ddrphy_dfi_p1_address[8]), + .D4(soc_k7ddrphy_dfi_p1_address[8]), + .D5(soc_k7ddrphy_dfi_p2_address[8]), + .D6(soc_k7ddrphy_dfi_p2_address[8]), + .D7(soc_k7ddrphy_dfi_p3_address[8]), + .D8(soc_k7ddrphy_dfi_p3_address[8]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address8) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_9 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[8]), + .ODATAIN(soc_k7ddrphy_address8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_10 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[9]), + .D2(soc_k7ddrphy_dfi_p0_address[9]), + .D3(soc_k7ddrphy_dfi_p1_address[9]), + .D4(soc_k7ddrphy_dfi_p1_address[9]), + .D5(soc_k7ddrphy_dfi_p2_address[9]), + .D6(soc_k7ddrphy_dfi_p2_address[9]), + .D7(soc_k7ddrphy_dfi_p3_address[9]), + .D8(soc_k7ddrphy_dfi_p3_address[9]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address9) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_10 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[9]), + .ODATAIN(soc_k7ddrphy_address9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_11 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[10]), + .D2(soc_k7ddrphy_dfi_p0_address[10]), + .D3(soc_k7ddrphy_dfi_p1_address[10]), + .D4(soc_k7ddrphy_dfi_p1_address[10]), + .D5(soc_k7ddrphy_dfi_p2_address[10]), + .D6(soc_k7ddrphy_dfi_p2_address[10]), + .D7(soc_k7ddrphy_dfi_p3_address[10]), + .D8(soc_k7ddrphy_dfi_p3_address[10]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address10) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_11 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[10]), + .ODATAIN(soc_k7ddrphy_address10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_12 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[11]), + .D2(soc_k7ddrphy_dfi_p0_address[11]), + .D3(soc_k7ddrphy_dfi_p1_address[11]), + .D4(soc_k7ddrphy_dfi_p1_address[11]), + .D5(soc_k7ddrphy_dfi_p2_address[11]), + .D6(soc_k7ddrphy_dfi_p2_address[11]), + .D7(soc_k7ddrphy_dfi_p3_address[11]), + .D8(soc_k7ddrphy_dfi_p3_address[11]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address11) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_12 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[11]), + .ODATAIN(soc_k7ddrphy_address11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_13 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[12]), + .D2(soc_k7ddrphy_dfi_p0_address[12]), + .D3(soc_k7ddrphy_dfi_p1_address[12]), + .D4(soc_k7ddrphy_dfi_p1_address[12]), + .D5(soc_k7ddrphy_dfi_p2_address[12]), + .D6(soc_k7ddrphy_dfi_p2_address[12]), + .D7(soc_k7ddrphy_dfi_p3_address[12]), + .D8(soc_k7ddrphy_dfi_p3_address[12]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address12) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_13 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[12]), + .ODATAIN(soc_k7ddrphy_address12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_14 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[13]), + .D2(soc_k7ddrphy_dfi_p0_address[13]), + .D3(soc_k7ddrphy_dfi_p1_address[13]), + .D4(soc_k7ddrphy_dfi_p1_address[13]), + .D5(soc_k7ddrphy_dfi_p2_address[13]), + .D6(soc_k7ddrphy_dfi_p2_address[13]), + .D7(soc_k7ddrphy_dfi_p3_address[13]), + .D8(soc_k7ddrphy_dfi_p3_address[13]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address13) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_14 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[13]), + .ODATAIN(soc_k7ddrphy_address13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_15 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_address[14]), + .D2(soc_k7ddrphy_dfi_p0_address[14]), + .D3(soc_k7ddrphy_dfi_p1_address[14]), + .D4(soc_k7ddrphy_dfi_p1_address[14]), + .D5(soc_k7ddrphy_dfi_p2_address[14]), + .D6(soc_k7ddrphy_dfi_p2_address[14]), + .D7(soc_k7ddrphy_dfi_p3_address[14]), + .D8(soc_k7ddrphy_dfi_p3_address[14]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_address14) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_15 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_a[14]), + .ODATAIN(soc_k7ddrphy_address14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_16 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_bank[0]), + .D2(soc_k7ddrphy_dfi_p0_bank[0]), + .D3(soc_k7ddrphy_dfi_p1_bank[0]), + .D4(soc_k7ddrphy_dfi_p1_bank[0]), + .D5(soc_k7ddrphy_dfi_p2_bank[0]), + .D6(soc_k7ddrphy_dfi_p2_bank[0]), + .D7(soc_k7ddrphy_dfi_p3_bank[0]), + .D8(soc_k7ddrphy_dfi_p3_bank[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_bank0) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_16 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_ba[0]), + .ODATAIN(soc_k7ddrphy_bank0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_17 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_bank[1]), + .D2(soc_k7ddrphy_dfi_p0_bank[1]), + .D3(soc_k7ddrphy_dfi_p1_bank[1]), + .D4(soc_k7ddrphy_dfi_p1_bank[1]), + .D5(soc_k7ddrphy_dfi_p2_bank[1]), + .D6(soc_k7ddrphy_dfi_p2_bank[1]), + .D7(soc_k7ddrphy_dfi_p3_bank[1]), + .D8(soc_k7ddrphy_dfi_p3_bank[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_bank1) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_17 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_ba[1]), + .ODATAIN(soc_k7ddrphy_bank1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_18 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_bank[2]), + .D2(soc_k7ddrphy_dfi_p0_bank[2]), + .D3(soc_k7ddrphy_dfi_p1_bank[2]), + .D4(soc_k7ddrphy_dfi_p1_bank[2]), + .D5(soc_k7ddrphy_dfi_p2_bank[2]), + .D6(soc_k7ddrphy_dfi_p2_bank[2]), + .D7(soc_k7ddrphy_dfi_p3_bank[2]), + .D8(soc_k7ddrphy_dfi_p3_bank[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_bank2) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_18 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_ba[2]), + .ODATAIN(soc_k7ddrphy_bank2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_19 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_ras_n), + .D2(soc_k7ddrphy_dfi_p0_ras_n), + .D3(soc_k7ddrphy_dfi_p1_ras_n), + .D4(soc_k7ddrphy_dfi_p1_ras_n), + .D5(soc_k7ddrphy_dfi_p2_ras_n), + .D6(soc_k7ddrphy_dfi_p2_ras_n), + .D7(soc_k7ddrphy_dfi_p3_ras_n), + .D8(soc_k7ddrphy_dfi_p3_ras_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_cmd0) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_19 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_ras_n), + .ODATAIN(soc_k7ddrphy_cmd0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_20 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_cas_n), + .D2(soc_k7ddrphy_dfi_p0_cas_n), + .D3(soc_k7ddrphy_dfi_p1_cas_n), + .D4(soc_k7ddrphy_dfi_p1_cas_n), + .D5(soc_k7ddrphy_dfi_p2_cas_n), + .D6(soc_k7ddrphy_dfi_p2_cas_n), + .D7(soc_k7ddrphy_dfi_p3_cas_n), + .D8(soc_k7ddrphy_dfi_p3_cas_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_cmd1) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_20 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_cas_n), + .ODATAIN(soc_k7ddrphy_cmd1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_21 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_we_n), + .D2(soc_k7ddrphy_dfi_p0_we_n), + .D3(soc_k7ddrphy_dfi_p1_we_n), + .D4(soc_k7ddrphy_dfi_p1_we_n), + .D5(soc_k7ddrphy_dfi_p2_we_n), + .D6(soc_k7ddrphy_dfi_p2_we_n), + .D7(soc_k7ddrphy_dfi_p3_we_n), + .D8(soc_k7ddrphy_dfi_p3_we_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_cmd2) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_21 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_we_n), + .ODATAIN(soc_k7ddrphy_cmd2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_22 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_cke), + .D2(soc_k7ddrphy_dfi_p0_cke), + .D3(soc_k7ddrphy_dfi_p1_cke), + .D4(soc_k7ddrphy_dfi_p1_cke), + .D5(soc_k7ddrphy_dfi_p2_cke), + .D6(soc_k7ddrphy_dfi_p2_cke), + .D7(soc_k7ddrphy_dfi_p3_cke), + .D8(soc_k7ddrphy_dfi_p3_cke), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_cmd3) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_22 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_cke), + .ODATAIN(soc_k7ddrphy_cmd3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_23 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_odt), + .D2(soc_k7ddrphy_dfi_p0_odt), + .D3(soc_k7ddrphy_dfi_p1_odt), + .D4(soc_k7ddrphy_dfi_p1_odt), + .D5(soc_k7ddrphy_dfi_p2_odt), + .D6(soc_k7ddrphy_dfi_p2_odt), + .D7(soc_k7ddrphy_dfi_p3_odt), + .D8(soc_k7ddrphy_dfi_p3_odt), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_cmd4) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_23 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_odt), + .ODATAIN(soc_k7ddrphy_cmd4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_24 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_reset_n), + .D2(soc_k7ddrphy_dfi_p0_reset_n), + .D3(soc_k7ddrphy_dfi_p1_reset_n), + .D4(soc_k7ddrphy_dfi_p1_reset_n), + .D5(soc_k7ddrphy_dfi_p2_reset_n), + .D6(soc_k7ddrphy_dfi_p2_reset_n), + .D7(soc_k7ddrphy_dfi_p3_reset_n), + .D8(soc_k7ddrphy_dfi_p3_reset_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_cmd5) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_24 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_reset_n), + .ODATAIN(soc_k7ddrphy_cmd5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_25 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_cs_n), + .D2(soc_k7ddrphy_dfi_p0_cs_n), + .D3(soc_k7ddrphy_dfi_p1_cs_n), + .D4(soc_k7ddrphy_dfi_p1_cs_n), + .D5(soc_k7ddrphy_dfi_p2_cs_n), + .D6(soc_k7ddrphy_dfi_p2_cs_n), + .D7(soc_k7ddrphy_dfi_p3_cs_n), + .D8(soc_k7ddrphy_dfi_p3_cs_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_cmd6) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_25 ( + .C(sys_clk), + .CE(soc_k7ddrphy_cdly_inc_re), + .INC(1'd1), + .LD(soc_k7ddrphy_cdly_rst_re), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_cs_n), + .ODATAIN(soc_k7ddrphy_cmd6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_26 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[0]), + .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[4]), + .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[0]), + .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[4]), + .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[0]), + .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[4]), + .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[0]), + .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[4]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_dm_o_nodelay0) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_26 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_dm[0]), + .ODATAIN(soc_k7ddrphy_dm_o_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_27 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[1]), + .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[5]), + .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[1]), + .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[5]), + .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[1]), + .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[5]), + .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[1]), + .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[5]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_dm_o_nodelay1) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_27 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_dm[1]), + .ODATAIN(soc_k7ddrphy_dm_o_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_28 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[2]), + .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[6]), + .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[2]), + .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[6]), + .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[2]), + .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[6]), + .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[2]), + .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[6]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_dm_o_nodelay2) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_28 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_dm[2]), + .ODATAIN(soc_k7ddrphy_dm_o_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_29 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata_mask[3]), + .D2(soc_k7ddrphy_dfi_p0_wrdata_mask[7]), + .D3(soc_k7ddrphy_dfi_p1_wrdata_mask[3]), + .D4(soc_k7ddrphy_dfi_p1_wrdata_mask[7]), + .D5(soc_k7ddrphy_dfi_p2_wrdata_mask[3]), + .D6(soc_k7ddrphy_dfi_p2_wrdata_mask[7]), + .D7(soc_k7ddrphy_dfi_p3_wrdata_mask[3]), + .D8(soc_k7ddrphy_dfi_p3_wrdata_mask[7]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_k7ddrphy_dm_o_nodelay3) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_29 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(ddram_dm[3]), + .ODATAIN(soc_k7ddrphy_dm_o_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_30 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dqspattern_o[0]), + .D2(soc_k7ddrphy_dqspattern_o[1]), + .D3(soc_k7ddrphy_dqspattern_o[2]), + .D4(soc_k7ddrphy_dqspattern_o[3]), + .D5(soc_k7ddrphy_dqspattern_o[4]), + .D6(soc_k7ddrphy_dqspattern_o[5]), + .D7(soc_k7ddrphy_dqspattern_o[6]), + .D8(soc_k7ddrphy_dqspattern_o[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_k7ddrphy_dqs_o_no_delay0), + .OQ(soc_k7ddrphy0), + .TQ(soc_k7ddrphy_dqs_t0) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_30 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dqs_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dqs_o_delayed0), + .ODATAIN(soc_k7ddrphy_dqs_o_no_delay0) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2 ( + .IDATAIN(soc_k7ddrphy_dqs_i[0]), + .DATAOUT(soc_k7ddrphy_dqs_i_delayed[0]) +); + +IOBUFDS IOBUFDS( + .I(soc_k7ddrphy_dqs_o_delayed0), + .T(soc_k7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]), + .O(soc_k7ddrphy_dqs_i[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_31 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dqspattern_o[0]), + .D2(soc_k7ddrphy_dqspattern_o[1]), + .D3(soc_k7ddrphy_dqspattern_o[2]), + .D4(soc_k7ddrphy_dqspattern_o[3]), + .D5(soc_k7ddrphy_dqspattern_o[4]), + .D6(soc_k7ddrphy_dqspattern_o[5]), + .D7(soc_k7ddrphy_dqspattern_o[6]), + .D8(soc_k7ddrphy_dqspattern_o[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_k7ddrphy_dqs_o_no_delay1), + .OQ(soc_k7ddrphy1), + .TQ(soc_k7ddrphy_dqs_t1) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_31 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dqs_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dqs_o_delayed1), + .ODATAIN(soc_k7ddrphy_dqs_o_no_delay1) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_1 ( + .IDATAIN(soc_k7ddrphy_dqs_i[1]), + .DATAOUT(soc_k7ddrphy_dqs_i_delayed[1]) +); + +IOBUFDS IOBUFDS_1( + .I(soc_k7ddrphy_dqs_o_delayed1), + .T(soc_k7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]), + .O(soc_k7ddrphy_dqs_i[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_32 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dqspattern_o[0]), + .D2(soc_k7ddrphy_dqspattern_o[1]), + .D3(soc_k7ddrphy_dqspattern_o[2]), + .D4(soc_k7ddrphy_dqspattern_o[3]), + .D5(soc_k7ddrphy_dqspattern_o[4]), + .D6(soc_k7ddrphy_dqspattern_o[5]), + .D7(soc_k7ddrphy_dqspattern_o[6]), + .D8(soc_k7ddrphy_dqspattern_o[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_k7ddrphy_dqs_o_no_delay2), + .OQ(soc_k7ddrphy2), + .TQ(soc_k7ddrphy_dqs_t2) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_32 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dqs_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dqs_o_delayed2), + .ODATAIN(soc_k7ddrphy_dqs_o_no_delay2) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_2 ( + .IDATAIN(soc_k7ddrphy_dqs_i[2]), + .DATAOUT(soc_k7ddrphy_dqs_i_delayed[2]) +); + +IOBUFDS IOBUFDS_2( + .I(soc_k7ddrphy_dqs_o_delayed2), + .T(soc_k7ddrphy_dqs_t2), + .IO(ddram_dqs_p[2]), + .IOB(ddram_dqs_n[2]), + .O(soc_k7ddrphy_dqs_i[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_33 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dqspattern_o[0]), + .D2(soc_k7ddrphy_dqspattern_o[1]), + .D3(soc_k7ddrphy_dqspattern_o[2]), + .D4(soc_k7ddrphy_dqspattern_o[3]), + .D5(soc_k7ddrphy_dqspattern_o[4]), + .D6(soc_k7ddrphy_dqspattern_o[5]), + .D7(soc_k7ddrphy_dqspattern_o[6]), + .D8(soc_k7ddrphy_dqspattern_o[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_k7ddrphy_dqs_o_no_delay3), + .OQ(soc_k7ddrphy3), + .TQ(soc_k7ddrphy_dqs_t3) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_33 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dqs_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dqs_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dqs_o_delayed3), + .ODATAIN(soc_k7ddrphy_dqs_o_no_delay3) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_3 ( + .IDATAIN(soc_k7ddrphy_dqs_i[3]), + .DATAOUT(soc_k7ddrphy_dqs_i_delayed[3]) +); + +IOBUFDS IOBUFDS_3( + .I(soc_k7ddrphy_dqs_o_delayed3), + .T(soc_k7ddrphy_dqs_t3), + .IO(ddram_dqs_p[3]), + .IOB(ddram_dqs_n[3]), + .O(soc_k7ddrphy_dqs_i[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_34 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[0]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[32]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[0]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[32]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[0]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[32]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[0]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[32]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay0), + .TQ(soc_k7ddrphy_dq_t0) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed0), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data0[7]), + .Q2(soc_k7ddrphy_dq_i_data0[6]), + .Q3(soc_k7ddrphy_dq_i_data0[5]), + .Q4(soc_k7ddrphy_dq_i_data0[4]), + .Q5(soc_k7ddrphy_dq_i_data0[3]), + .Q6(soc_k7ddrphy_dq_i_data0[2]), + .Q7(soc_k7ddrphy_dq_i_data0[1]), + .Q8(soc_k7ddrphy_dq_i_data0[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_34 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed0), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay0) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_4 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay0), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed0) +); + +IOBUF IOBUF( + .I(soc_k7ddrphy_dq_o_delayed0), + .T(soc_k7ddrphy_dq_t0), + .IO(ddram_dq[0]), + .O(soc_k7ddrphy_dq_i_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_35 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[1]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[33]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[1]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[33]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[1]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[33]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[1]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[33]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay1), + .TQ(soc_k7ddrphy_dq_t1) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_1 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed1), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data1[7]), + .Q2(soc_k7ddrphy_dq_i_data1[6]), + .Q3(soc_k7ddrphy_dq_i_data1[5]), + .Q4(soc_k7ddrphy_dq_i_data1[4]), + .Q5(soc_k7ddrphy_dq_i_data1[3]), + .Q6(soc_k7ddrphy_dq_i_data1[2]), + .Q7(soc_k7ddrphy_dq_i_data1[1]), + .Q8(soc_k7ddrphy_dq_i_data1[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_35 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed1), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay1) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_5 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay1), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed1) +); + +IOBUF IOBUF_1( + .I(soc_k7ddrphy_dq_o_delayed1), + .T(soc_k7ddrphy_dq_t1), + .IO(ddram_dq[1]), + .O(soc_k7ddrphy_dq_i_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_36 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[2]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[34]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[2]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[34]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[2]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[34]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[2]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[34]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay2), + .TQ(soc_k7ddrphy_dq_t2) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed2), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data2[7]), + .Q2(soc_k7ddrphy_dq_i_data2[6]), + .Q3(soc_k7ddrphy_dq_i_data2[5]), + .Q4(soc_k7ddrphy_dq_i_data2[4]), + .Q5(soc_k7ddrphy_dq_i_data2[3]), + .Q6(soc_k7ddrphy_dq_i_data2[2]), + .Q7(soc_k7ddrphy_dq_i_data2[1]), + .Q8(soc_k7ddrphy_dq_i_data2[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_36 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed2), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay2) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_6 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay2), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed2) +); + +IOBUF IOBUF_2( + .I(soc_k7ddrphy_dq_o_delayed2), + .T(soc_k7ddrphy_dq_t2), + .IO(ddram_dq[2]), + .O(soc_k7ddrphy_dq_i_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_37 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[3]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[35]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[3]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[35]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[3]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[35]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[3]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[35]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay3), + .TQ(soc_k7ddrphy_dq_t3) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_3 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed3), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data3[7]), + .Q2(soc_k7ddrphy_dq_i_data3[6]), + .Q3(soc_k7ddrphy_dq_i_data3[5]), + .Q4(soc_k7ddrphy_dq_i_data3[4]), + .Q5(soc_k7ddrphy_dq_i_data3[3]), + .Q6(soc_k7ddrphy_dq_i_data3[2]), + .Q7(soc_k7ddrphy_dq_i_data3[1]), + .Q8(soc_k7ddrphy_dq_i_data3[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_37 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed3), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay3) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_7 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay3), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed3) +); + +IOBUF IOBUF_3( + .I(soc_k7ddrphy_dq_o_delayed3), + .T(soc_k7ddrphy_dq_t3), + .IO(ddram_dq[3]), + .O(soc_k7ddrphy_dq_i_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_38 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[4]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[36]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[4]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[36]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[4]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[36]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[4]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[36]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay4), + .TQ(soc_k7ddrphy_dq_t4) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_4 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed4), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data4[7]), + .Q2(soc_k7ddrphy_dq_i_data4[6]), + .Q3(soc_k7ddrphy_dq_i_data4[5]), + .Q4(soc_k7ddrphy_dq_i_data4[4]), + .Q5(soc_k7ddrphy_dq_i_data4[3]), + .Q6(soc_k7ddrphy_dq_i_data4[2]), + .Q7(soc_k7ddrphy_dq_i_data4[1]), + .Q8(soc_k7ddrphy_dq_i_data4[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_38 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed4), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay4) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_8 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay4), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed4) +); + +IOBUF IOBUF_4( + .I(soc_k7ddrphy_dq_o_delayed4), + .T(soc_k7ddrphy_dq_t4), + .IO(ddram_dq[4]), + .O(soc_k7ddrphy_dq_i_nodelay4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_39 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[5]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[37]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[5]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[37]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[5]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[37]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[5]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[37]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay5), + .TQ(soc_k7ddrphy_dq_t5) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_5 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed5), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data5[7]), + .Q2(soc_k7ddrphy_dq_i_data5[6]), + .Q3(soc_k7ddrphy_dq_i_data5[5]), + .Q4(soc_k7ddrphy_dq_i_data5[4]), + .Q5(soc_k7ddrphy_dq_i_data5[3]), + .Q6(soc_k7ddrphy_dq_i_data5[2]), + .Q7(soc_k7ddrphy_dq_i_data5[1]), + .Q8(soc_k7ddrphy_dq_i_data5[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_39 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed5), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay5) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_9 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay5), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed5) +); + +IOBUF IOBUF_5( + .I(soc_k7ddrphy_dq_o_delayed5), + .T(soc_k7ddrphy_dq_t5), + .IO(ddram_dq[5]), + .O(soc_k7ddrphy_dq_i_nodelay5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_40 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[6]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[38]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[6]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[38]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[6]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[38]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[6]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[38]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay6), + .TQ(soc_k7ddrphy_dq_t6) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_6 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed6), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data6[7]), + .Q2(soc_k7ddrphy_dq_i_data6[6]), + .Q3(soc_k7ddrphy_dq_i_data6[5]), + .Q4(soc_k7ddrphy_dq_i_data6[4]), + .Q5(soc_k7ddrphy_dq_i_data6[3]), + .Q6(soc_k7ddrphy_dq_i_data6[2]), + .Q7(soc_k7ddrphy_dq_i_data6[1]), + .Q8(soc_k7ddrphy_dq_i_data6[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_40 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed6), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay6) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_10 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay6), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed6) +); + +IOBUF IOBUF_6( + .I(soc_k7ddrphy_dq_o_delayed6), + .T(soc_k7ddrphy_dq_t6), + .IO(ddram_dq[6]), + .O(soc_k7ddrphy_dq_i_nodelay6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_41 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[7]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[39]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[7]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[39]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[7]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[39]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[7]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[39]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay7), + .TQ(soc_k7ddrphy_dq_t7) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_7 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed7), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data7[7]), + .Q2(soc_k7ddrphy_dq_i_data7[6]), + .Q3(soc_k7ddrphy_dq_i_data7[5]), + .Q4(soc_k7ddrphy_dq_i_data7[4]), + .Q5(soc_k7ddrphy_dq_i_data7[3]), + .Q6(soc_k7ddrphy_dq_i_data7[2]), + .Q7(soc_k7ddrphy_dq_i_data7[1]), + .Q8(soc_k7ddrphy_dq_i_data7[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_41 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed7), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay7) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_11 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay7), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[0] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed7) +); + +IOBUF IOBUF_7( + .I(soc_k7ddrphy_dq_o_delayed7), + .T(soc_k7ddrphy_dq_t7), + .IO(ddram_dq[7]), + .O(soc_k7ddrphy_dq_i_nodelay7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_42 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[8]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[40]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[8]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[40]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[8]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[40]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[8]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[40]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay8), + .TQ(soc_k7ddrphy_dq_t8) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_8 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed8), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data8[7]), + .Q2(soc_k7ddrphy_dq_i_data8[6]), + .Q3(soc_k7ddrphy_dq_i_data8[5]), + .Q4(soc_k7ddrphy_dq_i_data8[4]), + .Q5(soc_k7ddrphy_dq_i_data8[3]), + .Q6(soc_k7ddrphy_dq_i_data8[2]), + .Q7(soc_k7ddrphy_dq_i_data8[1]), + .Q8(soc_k7ddrphy_dq_i_data8[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_42 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed8), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay8) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_12 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay8), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed8) +); + +IOBUF IOBUF_8( + .I(soc_k7ddrphy_dq_o_delayed8), + .T(soc_k7ddrphy_dq_t8), + .IO(ddram_dq[8]), + .O(soc_k7ddrphy_dq_i_nodelay8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_43 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[9]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[41]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[9]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[41]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[9]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[41]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[9]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[41]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay9), + .TQ(soc_k7ddrphy_dq_t9) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_9 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed9), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data9[7]), + .Q2(soc_k7ddrphy_dq_i_data9[6]), + .Q3(soc_k7ddrphy_dq_i_data9[5]), + .Q4(soc_k7ddrphy_dq_i_data9[4]), + .Q5(soc_k7ddrphy_dq_i_data9[3]), + .Q6(soc_k7ddrphy_dq_i_data9[2]), + .Q7(soc_k7ddrphy_dq_i_data9[1]), + .Q8(soc_k7ddrphy_dq_i_data9[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_43 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed9), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay9) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_13 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay9), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed9) +); + +IOBUF IOBUF_9( + .I(soc_k7ddrphy_dq_o_delayed9), + .T(soc_k7ddrphy_dq_t9), + .IO(ddram_dq[9]), + .O(soc_k7ddrphy_dq_i_nodelay9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_44 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[10]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[42]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[10]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[42]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[10]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[42]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[10]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[42]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay10), + .TQ(soc_k7ddrphy_dq_t10) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_10 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed10), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data10[7]), + .Q2(soc_k7ddrphy_dq_i_data10[6]), + .Q3(soc_k7ddrphy_dq_i_data10[5]), + .Q4(soc_k7ddrphy_dq_i_data10[4]), + .Q5(soc_k7ddrphy_dq_i_data10[3]), + .Q6(soc_k7ddrphy_dq_i_data10[2]), + .Q7(soc_k7ddrphy_dq_i_data10[1]), + .Q8(soc_k7ddrphy_dq_i_data10[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_44 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed10), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay10) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_14 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay10), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed10) +); + +IOBUF IOBUF_10( + .I(soc_k7ddrphy_dq_o_delayed10), + .T(soc_k7ddrphy_dq_t10), + .IO(ddram_dq[10]), + .O(soc_k7ddrphy_dq_i_nodelay10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_45 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[11]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[43]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[11]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[43]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[11]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[43]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[11]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[43]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay11), + .TQ(soc_k7ddrphy_dq_t11) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_11 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed11), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data11[7]), + .Q2(soc_k7ddrphy_dq_i_data11[6]), + .Q3(soc_k7ddrphy_dq_i_data11[5]), + .Q4(soc_k7ddrphy_dq_i_data11[4]), + .Q5(soc_k7ddrphy_dq_i_data11[3]), + .Q6(soc_k7ddrphy_dq_i_data11[2]), + .Q7(soc_k7ddrphy_dq_i_data11[1]), + .Q8(soc_k7ddrphy_dq_i_data11[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_45 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed11), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay11) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_15 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay11), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed11) +); + +IOBUF IOBUF_11( + .I(soc_k7ddrphy_dq_o_delayed11), + .T(soc_k7ddrphy_dq_t11), + .IO(ddram_dq[11]), + .O(soc_k7ddrphy_dq_i_nodelay11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_46 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[12]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[44]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[12]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[44]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[12]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[44]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[12]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[44]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay12), + .TQ(soc_k7ddrphy_dq_t12) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_12 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed12), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data12[7]), + .Q2(soc_k7ddrphy_dq_i_data12[6]), + .Q3(soc_k7ddrphy_dq_i_data12[5]), + .Q4(soc_k7ddrphy_dq_i_data12[4]), + .Q5(soc_k7ddrphy_dq_i_data12[3]), + .Q6(soc_k7ddrphy_dq_i_data12[2]), + .Q7(soc_k7ddrphy_dq_i_data12[1]), + .Q8(soc_k7ddrphy_dq_i_data12[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_46 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed12), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay12) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_16 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay12), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed12) +); + +IOBUF IOBUF_12( + .I(soc_k7ddrphy_dq_o_delayed12), + .T(soc_k7ddrphy_dq_t12), + .IO(ddram_dq[12]), + .O(soc_k7ddrphy_dq_i_nodelay12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_47 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[13]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[45]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[13]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[45]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[13]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[45]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[13]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[45]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay13), + .TQ(soc_k7ddrphy_dq_t13) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_13 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed13), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data13[7]), + .Q2(soc_k7ddrphy_dq_i_data13[6]), + .Q3(soc_k7ddrphy_dq_i_data13[5]), + .Q4(soc_k7ddrphy_dq_i_data13[4]), + .Q5(soc_k7ddrphy_dq_i_data13[3]), + .Q6(soc_k7ddrphy_dq_i_data13[2]), + .Q7(soc_k7ddrphy_dq_i_data13[1]), + .Q8(soc_k7ddrphy_dq_i_data13[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_47 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed13), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay13) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_17 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay13), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed13) +); + +IOBUF IOBUF_13( + .I(soc_k7ddrphy_dq_o_delayed13), + .T(soc_k7ddrphy_dq_t13), + .IO(ddram_dq[13]), + .O(soc_k7ddrphy_dq_i_nodelay13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_48 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[14]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[46]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[14]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[46]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[14]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[46]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[14]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[46]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay14), + .TQ(soc_k7ddrphy_dq_t14) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_14 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed14), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data14[7]), + .Q2(soc_k7ddrphy_dq_i_data14[6]), + .Q3(soc_k7ddrphy_dq_i_data14[5]), + .Q4(soc_k7ddrphy_dq_i_data14[4]), + .Q5(soc_k7ddrphy_dq_i_data14[3]), + .Q6(soc_k7ddrphy_dq_i_data14[2]), + .Q7(soc_k7ddrphy_dq_i_data14[1]), + .Q8(soc_k7ddrphy_dq_i_data14[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_48 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed14), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay14) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_18 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay14), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed14) +); + +IOBUF IOBUF_14( + .I(soc_k7ddrphy_dq_o_delayed14), + .T(soc_k7ddrphy_dq_t14), + .IO(ddram_dq[14]), + .O(soc_k7ddrphy_dq_i_nodelay14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_49 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[15]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[47]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[15]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[47]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[15]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[47]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[15]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[47]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay15), + .TQ(soc_k7ddrphy_dq_t15) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_15 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed15), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data15[7]), + .Q2(soc_k7ddrphy_dq_i_data15[6]), + .Q3(soc_k7ddrphy_dq_i_data15[5]), + .Q4(soc_k7ddrphy_dq_i_data15[4]), + .Q5(soc_k7ddrphy_dq_i_data15[3]), + .Q6(soc_k7ddrphy_dq_i_data15[2]), + .Q7(soc_k7ddrphy_dq_i_data15[1]), + .Q8(soc_k7ddrphy_dq_i_data15[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_49 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed15), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay15) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_19 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay15), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[1] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed15) +); + +IOBUF IOBUF_15( + .I(soc_k7ddrphy_dq_o_delayed15), + .T(soc_k7ddrphy_dq_t15), + .IO(ddram_dq[15]), + .O(soc_k7ddrphy_dq_i_nodelay15) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_50 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[16]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[48]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[16]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[48]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[16]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[48]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[16]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[48]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay16), + .TQ(soc_k7ddrphy_dq_t16) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_16 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed16), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data16[7]), + .Q2(soc_k7ddrphy_dq_i_data16[6]), + .Q3(soc_k7ddrphy_dq_i_data16[5]), + .Q4(soc_k7ddrphy_dq_i_data16[4]), + .Q5(soc_k7ddrphy_dq_i_data16[3]), + .Q6(soc_k7ddrphy_dq_i_data16[2]), + .Q7(soc_k7ddrphy_dq_i_data16[1]), + .Q8(soc_k7ddrphy_dq_i_data16[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_50 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed16), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay16) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_20 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay16), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed16) +); + +IOBUF IOBUF_16( + .I(soc_k7ddrphy_dq_o_delayed16), + .T(soc_k7ddrphy_dq_t16), + .IO(ddram_dq[16]), + .O(soc_k7ddrphy_dq_i_nodelay16) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_51 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[17]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[49]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[17]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[49]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[17]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[49]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[17]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[49]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay17), + .TQ(soc_k7ddrphy_dq_t17) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_17 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed17), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data17[7]), + .Q2(soc_k7ddrphy_dq_i_data17[6]), + .Q3(soc_k7ddrphy_dq_i_data17[5]), + .Q4(soc_k7ddrphy_dq_i_data17[4]), + .Q5(soc_k7ddrphy_dq_i_data17[3]), + .Q6(soc_k7ddrphy_dq_i_data17[2]), + .Q7(soc_k7ddrphy_dq_i_data17[1]), + .Q8(soc_k7ddrphy_dq_i_data17[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_51 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed17), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay17) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_21 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay17), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed17) +); + +IOBUF IOBUF_17( + .I(soc_k7ddrphy_dq_o_delayed17), + .T(soc_k7ddrphy_dq_t17), + .IO(ddram_dq[17]), + .O(soc_k7ddrphy_dq_i_nodelay17) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_52 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[18]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[50]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[18]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[50]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[18]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[50]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[18]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[50]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay18), + .TQ(soc_k7ddrphy_dq_t18) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_18 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed18), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data18[7]), + .Q2(soc_k7ddrphy_dq_i_data18[6]), + .Q3(soc_k7ddrphy_dq_i_data18[5]), + .Q4(soc_k7ddrphy_dq_i_data18[4]), + .Q5(soc_k7ddrphy_dq_i_data18[3]), + .Q6(soc_k7ddrphy_dq_i_data18[2]), + .Q7(soc_k7ddrphy_dq_i_data18[1]), + .Q8(soc_k7ddrphy_dq_i_data18[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_52 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed18), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay18) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_22 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay18), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed18) +); + +IOBUF IOBUF_18( + .I(soc_k7ddrphy_dq_o_delayed18), + .T(soc_k7ddrphy_dq_t18), + .IO(ddram_dq[18]), + .O(soc_k7ddrphy_dq_i_nodelay18) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_53 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[19]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[51]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[19]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[51]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[19]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[51]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[19]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[51]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay19), + .TQ(soc_k7ddrphy_dq_t19) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_19 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed19), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data19[7]), + .Q2(soc_k7ddrphy_dq_i_data19[6]), + .Q3(soc_k7ddrphy_dq_i_data19[5]), + .Q4(soc_k7ddrphy_dq_i_data19[4]), + .Q5(soc_k7ddrphy_dq_i_data19[3]), + .Q6(soc_k7ddrphy_dq_i_data19[2]), + .Q7(soc_k7ddrphy_dq_i_data19[1]), + .Q8(soc_k7ddrphy_dq_i_data19[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_53 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed19), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay19) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_23 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay19), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed19) +); + +IOBUF IOBUF_19( + .I(soc_k7ddrphy_dq_o_delayed19), + .T(soc_k7ddrphy_dq_t19), + .IO(ddram_dq[19]), + .O(soc_k7ddrphy_dq_i_nodelay19) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_54 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[20]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[52]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[20]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[52]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[20]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[52]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[20]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[52]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay20), + .TQ(soc_k7ddrphy_dq_t20) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_20 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed20), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data20[7]), + .Q2(soc_k7ddrphy_dq_i_data20[6]), + .Q3(soc_k7ddrphy_dq_i_data20[5]), + .Q4(soc_k7ddrphy_dq_i_data20[4]), + .Q5(soc_k7ddrphy_dq_i_data20[3]), + .Q6(soc_k7ddrphy_dq_i_data20[2]), + .Q7(soc_k7ddrphy_dq_i_data20[1]), + .Q8(soc_k7ddrphy_dq_i_data20[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_54 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed20), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay20) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_24 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay20), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed20) +); + +IOBUF IOBUF_20( + .I(soc_k7ddrphy_dq_o_delayed20), + .T(soc_k7ddrphy_dq_t20), + .IO(ddram_dq[20]), + .O(soc_k7ddrphy_dq_i_nodelay20) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_55 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[21]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[53]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[21]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[53]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[21]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[53]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[21]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[53]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay21), + .TQ(soc_k7ddrphy_dq_t21) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_21 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed21), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data21[7]), + .Q2(soc_k7ddrphy_dq_i_data21[6]), + .Q3(soc_k7ddrphy_dq_i_data21[5]), + .Q4(soc_k7ddrphy_dq_i_data21[4]), + .Q5(soc_k7ddrphy_dq_i_data21[3]), + .Q6(soc_k7ddrphy_dq_i_data21[2]), + .Q7(soc_k7ddrphy_dq_i_data21[1]), + .Q8(soc_k7ddrphy_dq_i_data21[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_55 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed21), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay21) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_25 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay21), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed21) +); + +IOBUF IOBUF_21( + .I(soc_k7ddrphy_dq_o_delayed21), + .T(soc_k7ddrphy_dq_t21), + .IO(ddram_dq[21]), + .O(soc_k7ddrphy_dq_i_nodelay21) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_56 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[22]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[54]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[22]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[54]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[22]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[54]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[22]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[54]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay22), + .TQ(soc_k7ddrphy_dq_t22) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_22 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed22), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data22[7]), + .Q2(soc_k7ddrphy_dq_i_data22[6]), + .Q3(soc_k7ddrphy_dq_i_data22[5]), + .Q4(soc_k7ddrphy_dq_i_data22[4]), + .Q5(soc_k7ddrphy_dq_i_data22[3]), + .Q6(soc_k7ddrphy_dq_i_data22[2]), + .Q7(soc_k7ddrphy_dq_i_data22[1]), + .Q8(soc_k7ddrphy_dq_i_data22[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_56 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed22), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay22) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_26 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay22), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed22) +); + +IOBUF IOBUF_22( + .I(soc_k7ddrphy_dq_o_delayed22), + .T(soc_k7ddrphy_dq_t22), + .IO(ddram_dq[22]), + .O(soc_k7ddrphy_dq_i_nodelay22) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_57 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[23]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[55]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[23]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[55]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[23]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[55]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[23]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[55]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay23), + .TQ(soc_k7ddrphy_dq_t23) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_23 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed23), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data23[7]), + .Q2(soc_k7ddrphy_dq_i_data23[6]), + .Q3(soc_k7ddrphy_dq_i_data23[5]), + .Q4(soc_k7ddrphy_dq_i_data23[4]), + .Q5(soc_k7ddrphy_dq_i_data23[3]), + .Q6(soc_k7ddrphy_dq_i_data23[2]), + .Q7(soc_k7ddrphy_dq_i_data23[1]), + .Q8(soc_k7ddrphy_dq_i_data23[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_57 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed23), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay23) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_27 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay23), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[2] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed23) +); + +IOBUF IOBUF_23( + .I(soc_k7ddrphy_dq_o_delayed23), + .T(soc_k7ddrphy_dq_t23), + .IO(ddram_dq[23]), + .O(soc_k7ddrphy_dq_i_nodelay23) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_58 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[24]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[56]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[24]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[56]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[24]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[56]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[24]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[56]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay24), + .TQ(soc_k7ddrphy_dq_t24) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_24 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed24), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data24[7]), + .Q2(soc_k7ddrphy_dq_i_data24[6]), + .Q3(soc_k7ddrphy_dq_i_data24[5]), + .Q4(soc_k7ddrphy_dq_i_data24[4]), + .Q5(soc_k7ddrphy_dq_i_data24[3]), + .Q6(soc_k7ddrphy_dq_i_data24[2]), + .Q7(soc_k7ddrphy_dq_i_data24[1]), + .Q8(soc_k7ddrphy_dq_i_data24[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_58 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed24), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay24) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_28 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay24), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed24) +); + +IOBUF IOBUF_24( + .I(soc_k7ddrphy_dq_o_delayed24), + .T(soc_k7ddrphy_dq_t24), + .IO(ddram_dq[24]), + .O(soc_k7ddrphy_dq_i_nodelay24) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_59 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[25]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[57]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[25]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[57]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[25]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[57]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[25]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[57]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay25), + .TQ(soc_k7ddrphy_dq_t25) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_25 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed25), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data25[7]), + .Q2(soc_k7ddrphy_dq_i_data25[6]), + .Q3(soc_k7ddrphy_dq_i_data25[5]), + .Q4(soc_k7ddrphy_dq_i_data25[4]), + .Q5(soc_k7ddrphy_dq_i_data25[3]), + .Q6(soc_k7ddrphy_dq_i_data25[2]), + .Q7(soc_k7ddrphy_dq_i_data25[1]), + .Q8(soc_k7ddrphy_dq_i_data25[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_59 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed25), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay25) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_29 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay25), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed25) +); + +IOBUF IOBUF_25( + .I(soc_k7ddrphy_dq_o_delayed25), + .T(soc_k7ddrphy_dq_t25), + .IO(ddram_dq[25]), + .O(soc_k7ddrphy_dq_i_nodelay25) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_60 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[26]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[58]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[26]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[58]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[26]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[58]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[26]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[58]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay26), + .TQ(soc_k7ddrphy_dq_t26) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_26 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed26), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data26[7]), + .Q2(soc_k7ddrphy_dq_i_data26[6]), + .Q3(soc_k7ddrphy_dq_i_data26[5]), + .Q4(soc_k7ddrphy_dq_i_data26[4]), + .Q5(soc_k7ddrphy_dq_i_data26[3]), + .Q6(soc_k7ddrphy_dq_i_data26[2]), + .Q7(soc_k7ddrphy_dq_i_data26[1]), + .Q8(soc_k7ddrphy_dq_i_data26[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_60 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed26), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay26) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_30 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay26), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed26) +); + +IOBUF IOBUF_26( + .I(soc_k7ddrphy_dq_o_delayed26), + .T(soc_k7ddrphy_dq_t26), + .IO(ddram_dq[26]), + .O(soc_k7ddrphy_dq_i_nodelay26) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_61 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[27]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[59]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[27]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[59]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[27]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[59]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[27]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[59]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay27), + .TQ(soc_k7ddrphy_dq_t27) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_27 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed27), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data27[7]), + .Q2(soc_k7ddrphy_dq_i_data27[6]), + .Q3(soc_k7ddrphy_dq_i_data27[5]), + .Q4(soc_k7ddrphy_dq_i_data27[4]), + .Q5(soc_k7ddrphy_dq_i_data27[3]), + .Q6(soc_k7ddrphy_dq_i_data27[2]), + .Q7(soc_k7ddrphy_dq_i_data27[1]), + .Q8(soc_k7ddrphy_dq_i_data27[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_61 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed27), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay27) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_31 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay27), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed27) +); + +IOBUF IOBUF_27( + .I(soc_k7ddrphy_dq_o_delayed27), + .T(soc_k7ddrphy_dq_t27), + .IO(ddram_dq[27]), + .O(soc_k7ddrphy_dq_i_nodelay27) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_62 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[28]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[60]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[28]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[60]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[28]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[60]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[28]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[60]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay28), + .TQ(soc_k7ddrphy_dq_t28) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_28 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed28), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data28[7]), + .Q2(soc_k7ddrphy_dq_i_data28[6]), + .Q3(soc_k7ddrphy_dq_i_data28[5]), + .Q4(soc_k7ddrphy_dq_i_data28[4]), + .Q5(soc_k7ddrphy_dq_i_data28[3]), + .Q6(soc_k7ddrphy_dq_i_data28[2]), + .Q7(soc_k7ddrphy_dq_i_data28[1]), + .Q8(soc_k7ddrphy_dq_i_data28[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_62 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed28), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay28) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_32 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay28), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed28) +); + +IOBUF IOBUF_28( + .I(soc_k7ddrphy_dq_o_delayed28), + .T(soc_k7ddrphy_dq_t28), + .IO(ddram_dq[28]), + .O(soc_k7ddrphy_dq_i_nodelay28) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_63 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[29]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[61]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[29]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[61]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[29]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[61]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[29]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[61]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay29), + .TQ(soc_k7ddrphy_dq_t29) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_29 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed29), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data29[7]), + .Q2(soc_k7ddrphy_dq_i_data29[6]), + .Q3(soc_k7ddrphy_dq_i_data29[5]), + .Q4(soc_k7ddrphy_dq_i_data29[4]), + .Q5(soc_k7ddrphy_dq_i_data29[3]), + .Q6(soc_k7ddrphy_dq_i_data29[2]), + .Q7(soc_k7ddrphy_dq_i_data29[1]), + .Q8(soc_k7ddrphy_dq_i_data29[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_63 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed29), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay29) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_33 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay29), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed29) +); + +IOBUF IOBUF_29( + .I(soc_k7ddrphy_dq_o_delayed29), + .T(soc_k7ddrphy_dq_t29), + .IO(ddram_dq[29]), + .O(soc_k7ddrphy_dq_i_nodelay29) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_64 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[30]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[62]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[30]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[62]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[30]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[62]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[30]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[62]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay30), + .TQ(soc_k7ddrphy_dq_t30) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_30 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed30), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data30[7]), + .Q2(soc_k7ddrphy_dq_i_data30[6]), + .Q3(soc_k7ddrphy_dq_i_data30[5]), + .Q4(soc_k7ddrphy_dq_i_data30[4]), + .Q5(soc_k7ddrphy_dq_i_data30[3]), + .Q6(soc_k7ddrphy_dq_i_data30[2]), + .Q7(soc_k7ddrphy_dq_i_data30[1]), + .Q8(soc_k7ddrphy_dq_i_data30[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_64 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed30), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay30) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_34 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay30), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed30) +); + +IOBUF IOBUF_30( + .I(soc_k7ddrphy_dq_o_delayed30), + .T(soc_k7ddrphy_dq_t30), + .IO(ddram_dq[30]), + .O(soc_k7ddrphy_dq_i_nodelay30) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_65 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_k7ddrphy_dfi_p0_wrdata[31]), + .D2(soc_k7ddrphy_dfi_p0_wrdata[63]), + .D3(soc_k7ddrphy_dfi_p1_wrdata[31]), + .D4(soc_k7ddrphy_dfi_p1_wrdata[63]), + .D5(soc_k7ddrphy_dfi_p2_wrdata[31]), + .D6(soc_k7ddrphy_dfi_p2_wrdata[63]), + .D7(soc_k7ddrphy_dfi_p3_wrdata[31]), + .D8(soc_k7ddrphy_dfi_p3_wrdata[63]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_k7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_k7ddrphy_dq_o_nodelay31), + .TQ(soc_k7ddrphy_dq_t31) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_31 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_k7ddrphy_dq_i_delayed31), + .RST(sys_rst), + .Q1(soc_k7ddrphy_dq_i_data31[7]), + .Q2(soc_k7ddrphy_dq_i_data31[6]), + .Q3(soc_k7ddrphy_dq_i_data31[5]), + .Q4(soc_k7ddrphy_dq_i_data31[4]), + .Q5(soc_k7ddrphy_dq_i_data31[3]), + .Q6(soc_k7ddrphy_dq_i_data31[2]), + .Q7(soc_k7ddrphy_dq_i_data31[1]), + .Q8(soc_k7ddrphy_dq_i_data31[0]) +); + +ODELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("ODATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .ODELAY_TYPE("VARIABLE"), + .ODELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) ODELAYE2_65 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_inc_re)), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_wdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_o_delayed31), + .ODATAIN(soc_k7ddrphy_dq_o_nodelay31) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_35 ( + .C(sys_clk), + .CE((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_k7ddrphy_dq_i_nodelay31), + .INC(1'd1), + .LD((soc_k7ddrphy_dly_sel_storage[3] & soc_k7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_k7ddrphy_dq_i_delayed31) +); + +IOBUF IOBUF_31( + .I(soc_k7ddrphy_dq_o_delayed31), + .T(soc_k7ddrphy_dq_t31), + .IO(ddram_dq[31]), + .O(soc_k7ddrphy_dq_i_nodelay31) +); + +reg [24:0] storage[0:15]; +reg [24:0] memdat; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_1[0:15]; +reg [24:0] memdat_1; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_2[0:15]; +reg [24:0] memdat_2; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_3[0:15]; +reg [24:0] memdat_3; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_4[0:15]; +reg [24:0] memdat_4; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_5[0:15]; +reg [24:0] memdat_5; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_6[0:15]; +reg [24:0] memdat_6; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_7[0:15]; +reg [24:0] memdat_7; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +PLLE2_ADV #( + .CLKFBOUT_MULT(4'd8), + .CLKIN1_PERIOD(5.0), + .CLKOUT0_DIVIDE(4'd8), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(5'd16), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(3'd4), + .CLKOUT2_PHASE(1'd0), + .CLKOUT3_DIVIDE(3'd4), + .CLKOUT3_PHASE(7'd90), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV ( + .CLKFBIN(vns_pll_fb), + .CLKIN1(soc_clkin), + .RST(soc_reset), + .CLKFBOUT(vns_pll_fb), + .CLKOUT0(soc_clkout0), + .CLKOUT1(soc_clkout1), + .CLKOUT2(soc_clkout2), + .CLKOUT3(soc_clkout3), + .LOCKED(soc_locked) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(iodelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(iodelay_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(iodelay_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(sys4x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(sys4x_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_6 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_7 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(vns_xilinxasyncresetsynchronizerimpl3_expr) +); + +endmodule diff --git a/litedram/generated/nexys-video/litedram-initmem.vhdl b/litedram/generated/nexys-video/litedram-initmem.vhdl index a1b87d3..395602b 100644 --- a/litedram/generated/nexys-video/litedram-initmem.vhdl +++ b/litedram/generated/nexys-video/litedram-initmem.vhdl @@ -21,7 +21,7 @@ end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; + constant INIT_RAM_SIZE : integer := 24576; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 3604d59..0f92f5b 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -5,7 +5,7 @@ a64b5a7d14004a39 2402004ca64b7b7d 602100003c200000 6421ff00782107c6 -3d80000060213f00 +3d80000060215f00 798c07c6618c0000 618c10e0658cff00 4e8004217d8903a6 @@ -518,7 +518,7 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842a6c4 +7c0802a63842a9c4 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612935347d908026 65293332792907c6 @@ -1378,7 +1458,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428be4 +7c0802a638428c64 f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -1394,7 +1474,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a638428b64 +7c0802a638428be4 f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -1425,16 +1505,16 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -38428a683c4c0001 +38428ae83c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 2fa4000041820068 39210040419e0060 -3ac4ffff60000000 +3ac4ffff3e42ffff f92100703b410020 3ae0000060000000 -3a42802839228070 +3a527fc039228008 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1665,9 +1745,9 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -6633623461653832 +3830643432643338 0000000000000000 -0039326232623162 +0064623161656634 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1709,29 +1789,6 @@ e8010010ebc1fff0 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -20747365746d654d -6c69616620737562 -252f6425203a6465 -73726f7272652064 -000000000000000a -20747365746d654d -6961662061746164 -2f6425203a64656c -726f727265206425 -0000000000000a73 -20747365746d654d -6961662072646461 -2f6425203a64656c -726f727265206425 -0000000000000a73 -20747365746d654d -00000000000a4b4f -64656570736d654d -3a73657469725720 -7370624d646c2520 -203a736461655220 -0a7370624d646c25 -0000000000000000 203a7379616c6564 0000000000000000 000000000000002d @@ -1747,8 +1804,9 @@ e8010010ebc1fff0 6c6f72746e6f6320 000000000000000a 696c616974696e49 -52445320676e697a -00000a2e2e2e4d41 +41524420676e697a +383025783040204d +0000000a2e2e2e78 76656c2064616552 000a3a676e696c65 302562202c64256d @@ -1763,6 +1821,31 @@ e8010010ebc1fff0 6572617774666f73 6c6f72746e6f6320 000000000000000a +64656570736d654d +7025783020746120 +000000000a2e2e2e +203a736574697257 +7370624d20646c25 +000000000000000a +20203a7364616552 +7370624d20646c25 +000000000000000a +20747365746d654d +2e70257830207461 +00000000000a2e2e +726520737562202d +2520203a73726f72 +00000a646c252f64 +652072646461202d +25203a73726f7272 +00000a646c252f64 +652061746164202d +25203a73726f7272 +00000a646c252f64 +20747365746d654d +00000000000a4f4b +20747365746d654d +00000000000a4b4f 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index cb2097a..a9b11c2 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:04 +// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:22 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/litedram/generated/sim/litedram-initmem.vhdl b/litedram/generated/sim/litedram-initmem.vhdl index b6886f9..796d45e 100644 --- a/litedram/generated/sim/litedram-initmem.vhdl +++ b/litedram/generated/sim/litedram-initmem.vhdl @@ -21,7 +21,7 @@ end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; + constant INIT_RAM_SIZE : integer := 24576; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index 583a2ff..d486310 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -5,7 +5,7 @@ a64b5a7d14004a39 2402004ca64b7b7d 602100003c200000 6421ff00782107c6 -3d80000060213f00 +3d80000060215f00 798c07c6618c0000 618c10e0658cff00 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+7c9c2378419d0008 +7c9d23782ba40080 +3ba00080409d0008 +7c9f23782ba40400 +3be00400409d0008 +7fc4f3783c62ffff +4bfff29138637fc0 +7f84e37860000000 +4bfffb8d7fc3f378 +7fa4eb7838a00000 +7fc3f3787c791b78 +38a000014bfffc81 +7c7a1b787fe4fb78 +4bfffd617fc3f378 +7d291a147d39d214 +2f8900007c7b1b78 +3c62ffff419e0068 +7f24cb787b85f882 +4bfff23138637fd8 +3c62ffff60000000 +7f44d3787ba5f082 +4bfff21938637ff0 +6000000060000000 +7f64db787be5f082 +4bfff20138628008 +6000000060000000 +4bfff1f138628020 +3860000060000000 +48000c84382100a0 +3862803060000000 +600000004bfff1d5 +38a000007fc3f378 +4bfffde97fe4fb78 +4bffffd438600001 +0100000000000000 +3c4c000100000780 +6000000038429064 +6000000039228098 +8929000039428090 419e002c2f890000 39290014e92a0000 7d204eaa7c0004ac @@ -916,7 +994,7 @@ e94a00005469063e 7d2057ea7c0004ac 000000004e800020 0000000000000000 -384290503c4c0001 +38428fe03c4c0001 fbc1fff07c0802a6 3bc3fffffbe1fff8 f821ffd1f8010010 @@ -928,7 +1006,7 @@ f821ffd1f8010010 4bffff397fe3fb78 000000004bffffd0 0000028001000000 -38428ff03c4c0001 +38428f803c4c0001 612900203d20c000 7c0004ac79290020 3d00c0007d204eea @@ -940,8 +1018,8 @@ f821ffd1f8010010 7c0004ac794a0020 3d00c0007d4056ea 6000000060000000 -6108200038e28010 -f902800879080020 +6108200038e28098 +f902809079080020 610820003d00001c 7948f8047d294392 4182008079080fc3 @@ -949,15 +1027,15 @@ f902800879080020 994700006108200c 3940ff8079080020 7d4047aa7c0004ac -7c0004ace9428008 -e94280087d2057aa +7c0004ace9428090 +e94280907d2057aa 394a00047929c202 7d2057aa7c0004ac -39400003e9228008 +39400003e9228090 7c0004ac3929000c -e92280087d404faa +e92280907d404faa 7c0004ac39290010 -e92280087d404faa +e92280907d404faa 3929000839400007 7d404faa7c0004ac 3d40c0004e800020 @@ -1028,7 +1106,7 @@ f924000039290002 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428cd03c4c0001 +38428c603c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1062,7 +1140,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428bc4 +7c0802a638428b54 f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -1078,7 +1156,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a638428b44 +7c0802a638428ad4 f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -1109,16 +1187,16 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -38428a483c4c0001 +384289d83c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 2fa4000041820068 39210040419e0060 -3ac4ffff3e42ffff +3ac4ffff60000000 f92100703b410020 3ae0000060000000 -3a527fb839228000 +3a42804039228088 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1349,9 +1427,9 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -6633623461653832 +3830643432643338 0000000000000000 -0039326232623162 +0064623161656634 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1393,42 +1471,45 @@ e8010010ebc1fff0 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -20747365746d654d -6c69616620737562 -252f6425203a6465 -73726f7272652064 -000000000000000a -20747365746d654d -6961662061746164 -2f6425203a64656c -726f727265206425 -0000000000000a73 -20747365746d654d -6961662072646461 -2f6425203a64656c -726f727265206425 -0000000000000a73 -20747365746d654d -00000000000a4b4f -64656570736d654d -3a73657469725720 -7370624d646c2520 -203a736461655220 -0a7370624d646c25 -0000000000000000 6f6e204d41524453 207265646e752077 6572617764726168 6c6f72746e6f6320 000000000000000a 696c616974696e49 -52445320676e697a -00000a2e2e2e4d41 +41524420676e697a +383025783040204d +0000000a2e2e2e78 6f6e204d41524453 207265646e752077 6572617774666f73 6c6f72746e6f6320 000000000000000a +64656570736d654d +7025783020746120 +000000000a2e2e2e +203a736574697257 +7370624d20646c25 +000000000000000a +20203a7364616552 +7370624d20646c25 +000000000000000a +20747365746d654d +2e70257830207461 +00000000000a2e2e +726520737562202d +2520203a73726f72 +00000a646c252f64 +652072646461202d +25203a73726f7272 +00000a646c252f64 +652061746164202d +25203a73726f7272 +00000a646c252f64 +20747365746d654d +00000000000a4f4b +20747365746d654d +00000000000a4b4f 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index d28d6a1..85d1ee1 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:06 +// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:26 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -1876,36 +1876,36 @@ always @(*) begin endcase end always @(*) begin - litedramcore_adr = 14'd0; + litedramcore_wishbone_ack = 1'd0; case (state) 1'd1: begin + litedramcore_wishbone_ack = 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr = litedramcore_wishbone_adr; - end end endcase end always @(*) begin - litedramcore_we = 1'd0; + litedramcore_adr = 14'd0; case (state) 1'd1: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + litedramcore_adr = litedramcore_wishbone_adr; end end endcase end always @(*) begin - litedramcore_wishbone_ack = 1'd0; + litedramcore_we = 1'd0; case (state) 1'd1: begin - litedramcore_wishbone_ack = 1'd1; end default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end end endcase end @@ -1920,36 +1920,36 @@ always @(*) begin ddrphy_activates0[3] = ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel0_activate = 1'd0; + ddrphy_bankmodel0_activate_row = 14'd0; case (ddrphy_activates0) 1'd1: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p0_bank == 1'd0); + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p1_bank == 1'd0); + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p2_bank == 1'd0); + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel0_activate = (ddrphy_dfi_p3_bank == 1'd0); + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel0_activate_row = 14'd0; + ddrphy_bankmodel0_activate = 1'd0; case (ddrphy_activates0) 1'd1: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p0_address; + ddrphy_bankmodel0_activate = (ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p1_address; + ddrphy_bankmodel0_activate = (ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p2_address; + ddrphy_bankmodel0_activate = (ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - ddrphy_bankmodel0_activate_row = ddrphy_dfi_p3_address; + ddrphy_bankmodel0_activate = (ddrphy_dfi_p3_bank == 1'd0); end endcase end @@ -2071,36 +2071,36 @@ always @(*) begin ddrphy_activates1[3] = ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel1_activate_row = 14'd0; + ddrphy_bankmodel1_activate = 1'd0; case (ddrphy_activates1) 1'd1: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address; + ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address; + ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address; + ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address; + ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - ddrphy_bankmodel1_activate = 1'd0; + ddrphy_bankmodel1_activate_row = 14'd0; case (ddrphy_activates1) 1'd1: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1); + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1); + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1); + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1); + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address; end endcase end @@ -2136,36 +2136,36 @@ always @(*) begin ddrphy_writes1[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write_col1 = 10'd0; + ddrphy_bank_write1 = 1'd0; case (ddrphy_writes1) 1'd1: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p0_address; + ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p1_address; + ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p2_address; + ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - ddrphy_bank_write_col1 = ddrphy_dfi_p3_address; + ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - ddrphy_bank_write1 = 1'd0; + ddrphy_bank_write_col1 = 10'd0; case (ddrphy_writes1) 1'd1: begin - ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1); + ddrphy_bank_write_col1 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1); + ddrphy_bank_write_col1 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1); + ddrphy_bank_write_col1 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1); + ddrphy_bank_write_col1 = ddrphy_dfi_p3_address; end endcase end @@ -2287,36 +2287,36 @@ always @(*) begin ddrphy_writes2[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write2 = 1'd0; + ddrphy_bank_write_col2 = 10'd0; case (ddrphy_writes2) 1'd1: begin - ddrphy_bank_write2 = (ddrphy_dfi_p0_bank == 2'd2); + ddrphy_bank_write_col2 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write2 = (ddrphy_dfi_p1_bank == 2'd2); + ddrphy_bank_write_col2 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write2 = (ddrphy_dfi_p2_bank == 2'd2); + ddrphy_bank_write_col2 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write2 = (ddrphy_dfi_p3_bank == 2'd2); + ddrphy_bank_write_col2 = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bank_write_col2 = 10'd0; + ddrphy_bank_write2 = 1'd0; case (ddrphy_writes2) 1'd1: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p0_address; + ddrphy_bank_write2 = (ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p1_address; + ddrphy_bank_write2 = (ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p2_address; + ddrphy_bank_write2 = (ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - ddrphy_bank_write_col2 = ddrphy_dfi_p3_address; + ddrphy_bank_write2 = (ddrphy_dfi_p3_bank == 2'd2); end endcase end @@ -2483,36 +2483,36 @@ always @(*) begin ddrphy_reads3[3] = ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel3_read = 1'd0; + ddrphy_bankmodel3_read_col = 10'd0; case (ddrphy_reads3) 1'd1: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p0_bank == 2'd3); + ddrphy_bankmodel3_read_col = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p1_bank == 2'd3); + ddrphy_bankmodel3_read_col = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p2_bank == 2'd3); + ddrphy_bankmodel3_read_col = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel3_read = (ddrphy_dfi_p3_bank == 2'd3); + ddrphy_bankmodel3_read_col = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel3_read_col = 10'd0; + ddrphy_bankmodel3_read = 1'd0; case (ddrphy_reads3) 1'd1: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p0_address; + ddrphy_bankmodel3_read = (ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p1_address; + ddrphy_bankmodel3_read = (ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p2_address; + ddrphy_bankmodel3_read = (ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - ddrphy_bankmodel3_read_col = ddrphy_dfi_p3_address; + ddrphy_bankmodel3_read = (ddrphy_dfi_p3_bank == 2'd3); end endcase end @@ -2634,36 +2634,36 @@ always @(*) begin ddrphy_reads4[3] = ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel4_read_col = 10'd0; + ddrphy_bankmodel4_read = 1'd0; case (ddrphy_reads4) 1'd1: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address; + ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address; + ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address; + ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address; + ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4); end endcase end always @(*) begin - ddrphy_bankmodel4_read = 1'd0; + ddrphy_bankmodel4_read_col = 10'd0; case (ddrphy_reads4) 1'd1: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4); + ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4); + ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4); + ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4); + ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address; end endcase end @@ -2675,36 +2675,36 @@ always @(*) begin ddrphy_activates5[3] = ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel5_activate = 1'd0; + ddrphy_bankmodel5_activate_row = 14'd0; case (ddrphy_activates5) 1'd1: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p0_bank == 3'd5); + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p1_bank == 3'd5); + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p2_bank == 3'd5); + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel5_activate = (ddrphy_dfi_p3_bank == 3'd5); + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel5_activate_row = 14'd0; + ddrphy_bankmodel5_activate = 1'd0; case (ddrphy_activates5) 1'd1: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p0_address; + ddrphy_bankmodel5_activate = (ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p1_address; + ddrphy_bankmodel5_activate = (ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p2_address; + ddrphy_bankmodel5_activate = (ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - ddrphy_bankmodel5_activate_row = ddrphy_dfi_p3_address; + ddrphy_bankmodel5_activate = (ddrphy_dfi_p3_bank == 3'd5); end endcase end @@ -2740,36 +2740,36 @@ always @(*) begin ddrphy_writes5[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write_col5 = 10'd0; + ddrphy_bank_write5 = 1'd0; case (ddrphy_writes5) 1'd1: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p0_address; + ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p1_address; + ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p2_address; + ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - ddrphy_bank_write_col5 = ddrphy_dfi_p3_address; + ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5); end endcase end always @(*) begin - ddrphy_bank_write5 = 1'd0; + ddrphy_bank_write_col5 = 10'd0; case (ddrphy_writes5) 1'd1: begin - ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5); + ddrphy_bank_write_col5 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5); + ddrphy_bank_write_col5 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5); + ddrphy_bank_write_col5 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5); + ddrphy_bank_write_col5 = ddrphy_dfi_p3_address; end endcase end @@ -2826,36 +2826,36 @@ always @(*) begin ddrphy_activates6[3] = ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel6_activate_row = 14'd0; + ddrphy_bankmodel6_activate = 1'd0; case (ddrphy_activates6) 1'd1: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address; + ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address; + ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address; + ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address; + ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - ddrphy_bankmodel6_activate = 1'd0; + ddrphy_bankmodel6_activate_row = 14'd0; case (ddrphy_activates6) 1'd1: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6); + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6); + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6); + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6); + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address; end endcase end @@ -2891,36 +2891,36 @@ always @(*) begin ddrphy_writes6[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write6 = 1'd0; + ddrphy_bank_write_col6 = 10'd0; case (ddrphy_writes6) 1'd1: begin - ddrphy_bank_write6 = (ddrphy_dfi_p0_bank == 3'd6); + ddrphy_bank_write_col6 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write6 = (ddrphy_dfi_p1_bank == 3'd6); + ddrphy_bank_write_col6 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write6 = (ddrphy_dfi_p2_bank == 3'd6); + ddrphy_bank_write_col6 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write6 = (ddrphy_dfi_p3_bank == 3'd6); + ddrphy_bank_write_col6 = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bank_write_col6 = 10'd0; + ddrphy_bank_write6 = 1'd0; case (ddrphy_writes6) 1'd1: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p0_address; + ddrphy_bank_write6 = (ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p1_address; + ddrphy_bank_write6 = (ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p2_address; + ddrphy_bank_write6 = (ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - ddrphy_bank_write_col6 = ddrphy_dfi_p3_address; + ddrphy_bank_write6 = (ddrphy_dfi_p3_bank == 3'd6); end endcase end @@ -2936,36 +2936,36 @@ always @(*) begin ddrphy_reads6[3] = ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel6_read = 1'd0; + ddrphy_bankmodel6_read_col = 10'd0; case (ddrphy_reads6) 1'd1: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p0_bank == 3'd6); + ddrphy_bankmodel6_read_col = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p1_bank == 3'd6); + ddrphy_bankmodel6_read_col = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p2_bank == 3'd6); + ddrphy_bankmodel6_read_col = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel6_read = (ddrphy_dfi_p3_bank == 3'd6); + ddrphy_bankmodel6_read_col = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel6_read_col = 10'd0; + ddrphy_bankmodel6_read = 1'd0; case (ddrphy_reads6) 1'd1: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p0_address; + ddrphy_bankmodel6_read = (ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p1_address; + ddrphy_bankmodel6_read = (ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p2_address; + ddrphy_bankmodel6_read = (ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - ddrphy_bankmodel6_read_col = ddrphy_dfi_p3_address; + ddrphy_bankmodel6_read = (ddrphy_dfi_p3_bank == 3'd6); end endcase end @@ -3087,36 +3087,36 @@ always @(*) begin ddrphy_reads7[3] = ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel7_read_col = 10'd0; + ddrphy_bankmodel7_read = 1'd0; case (ddrphy_reads7) 1'd1: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address; + ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address; + ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address; + ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address; + ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - ddrphy_bankmodel7_read = 1'd0; + ddrphy_bankmodel7_read_col = 10'd0; case (ddrphy_reads7) 1'd1: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7); + ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7); + ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7); + ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7); + ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address; end endcase end @@ -3131,15 +3131,15 @@ assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; always @(*) begin - ddrphy_dfiphasemodel0_activate = 1'd0; + ddrphy_dfiphasemodel0_precharge = 1'd0; if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin - ddrphy_dfiphasemodel0_activate = ddrphy_dfi_p0_we_n; + ddrphy_dfiphasemodel0_precharge = (~ddrphy_dfi_p0_we_n); end end always @(*) begin - ddrphy_dfiphasemodel0_precharge = 1'd0; + ddrphy_dfiphasemodel0_activate = 1'd0; if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin - ddrphy_dfiphasemodel0_precharge = (~ddrphy_dfi_p0_we_n); + ddrphy_dfiphasemodel0_activate = ddrphy_dfi_p0_we_n; end end always @(*) begin @@ -3155,15 +3155,15 @@ always @(*) begin end end always @(*) begin - ddrphy_dfiphasemodel1_precharge = 1'd0; + ddrphy_dfiphasemodel1_activate = 1'd0; if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin - ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n); + ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n; end end always @(*) begin - ddrphy_dfiphasemodel1_activate = 1'd0; + ddrphy_dfiphasemodel1_precharge = 1'd0; if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin - ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n; + ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n); end end always @(*) begin @@ -3191,15 +3191,15 @@ always @(*) begin end end always @(*) begin - ddrphy_dfiphasemodel2_write = 1'd0; + ddrphy_dfiphasemodel2_read = 1'd0; if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin - ddrphy_dfiphasemodel2_write = (~ddrphy_dfi_p2_we_n); + ddrphy_dfiphasemodel2_read = ddrphy_dfi_p2_we_n; end end always @(*) begin - ddrphy_dfiphasemodel2_read = 1'd0; + ddrphy_dfiphasemodel2_write = 1'd0; if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin - ddrphy_dfiphasemodel2_read = ddrphy_dfi_p2_we_n; + ddrphy_dfiphasemodel2_write = (~ddrphy_dfi_p2_we_n); end end always @(*) begin @@ -3215,19 +3215,33 @@ always @(*) begin end end always @(*) begin - ddrphy_dfiphasemodel3_read = 1'd0; + ddrphy_dfiphasemodel3_write = 1'd0; if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin - ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n; + ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n); end end always @(*) begin - ddrphy_dfiphasemodel3_write = 1'd0; + ddrphy_dfiphasemodel3_read = 1'd0; if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin - ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n); + ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n; end end assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3]; assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3]; +always @(*) begin + ddrphy_bankmodel0_read_data = 128'd0; + if (ddrphy_bankmodel0_active) begin + if (ddrphy_bankmodel0_read) begin + ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r; + end + end +end +always @(*) begin + ddrphy_bankmodel0_write_port_adr = 21'd0; + if (ddrphy_bankmodel0_active) begin + ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr; + end +end always @(*) begin ddrphy_bankmodel0_write_port_we = 16'd0; if (ddrphy_bankmodel0_active) begin @@ -3252,22 +3266,24 @@ always @(*) begin end end end +assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; +assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; always @(*) begin - ddrphy_bankmodel0_read_data = 128'd0; - if (ddrphy_bankmodel0_active) begin - if (ddrphy_bankmodel0_read) begin - ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r; - end + ddrphy_bankmodel1_write_port_adr = 21'd0; + if (ddrphy_bankmodel1_active) begin + ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr; end end always @(*) begin - ddrphy_bankmodel0_write_port_adr = 21'd0; - if (ddrphy_bankmodel0_active) begin - ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr; + ddrphy_bankmodel1_write_port_we = 16'd0; + if (ddrphy_bankmodel1_active) begin + if (4'd8) begin + ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask)); + end else begin + ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write; + end end end -assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; -assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; always @(*) begin ddrphy_bankmodel1_write_port_dat_w = 128'd0; if (ddrphy_bankmodel1_active) begin @@ -3290,32 +3306,8 @@ always @(*) begin end end end -always @(*) begin - ddrphy_bankmodel1_write_port_adr = 21'd0; - if (ddrphy_bankmodel1_active) begin - ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr; - end -end -always @(*) begin - ddrphy_bankmodel1_write_port_we = 16'd0; - if (ddrphy_bankmodel1_active) begin - if (4'd8) begin - ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask)); - end else begin - ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write; - end - end -end assign ddrphy_bankmodel2_wraddr = slice_proxy4[24:3]; assign ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3]; -always @(*) begin - ddrphy_bankmodel2_read_data = 128'd0; - if (ddrphy_bankmodel2_active) begin - if (ddrphy_bankmodel2_read) begin - ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r; - end - end -end always @(*) begin ddrphy_bankmodel2_write_port_adr = 21'd0; if (ddrphy_bankmodel2_active) begin @@ -3346,8 +3338,30 @@ always @(*) begin end end end +always @(*) begin + ddrphy_bankmodel2_read_data = 128'd0; + if (ddrphy_bankmodel2_active) begin + if (ddrphy_bankmodel2_read) begin + ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r; + end + end +end assign ddrphy_bankmodel3_wraddr = slice_proxy6[24:3]; assign ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3]; +always @(*) begin + ddrphy_bankmodel3_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel3_active) begin + ddrphy_bankmodel3_write_port_dat_w = ddrphy_bankmodel3_write_data; + end +end +always @(*) begin + ddrphy_bankmodel3_read_port_adr = 21'd0; + if (ddrphy_bankmodel3_active) begin + if (ddrphy_bankmodel3_read) begin + ddrphy_bankmodel3_read_port_adr = ddrphy_bankmodel3_rdaddr; + end + end +end always @(*) begin ddrphy_bankmodel3_read_data = 128'd0; if (ddrphy_bankmodel3_active) begin @@ -3372,22 +3386,16 @@ always @(*) begin end end end +assign ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; +assign ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; always @(*) begin - ddrphy_bankmodel3_write_port_dat_w = 128'd0; - if (ddrphy_bankmodel3_active) begin - ddrphy_bankmodel3_write_port_dat_w = ddrphy_bankmodel3_write_data; - end -end -always @(*) begin - ddrphy_bankmodel3_read_port_adr = 21'd0; - if (ddrphy_bankmodel3_active) begin - if (ddrphy_bankmodel3_read) begin - ddrphy_bankmodel3_read_port_adr = ddrphy_bankmodel3_rdaddr; + ddrphy_bankmodel4_read_port_adr = 21'd0; + if (ddrphy_bankmodel4_active) begin + if (ddrphy_bankmodel4_read) begin + ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr; end end end -assign ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; -assign ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; always @(*) begin ddrphy_bankmodel4_read_data = 128'd0; if (ddrphy_bankmodel4_active) begin @@ -3418,16 +3426,16 @@ always @(*) begin ddrphy_bankmodel4_write_port_dat_w = ddrphy_bankmodel4_write_data; end end +assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; +assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; always @(*) begin - ddrphy_bankmodel4_read_port_adr = 21'd0; - if (ddrphy_bankmodel4_active) begin - if (ddrphy_bankmodel4_read) begin - ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr; + ddrphy_bankmodel5_read_data = 128'd0; + if (ddrphy_bankmodel5_active) begin + if (ddrphy_bankmodel5_read) begin + ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r; end end end -assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; -assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; always @(*) begin ddrphy_bankmodel5_write_port_adr = 21'd0; if (ddrphy_bankmodel5_active) begin @@ -3458,16 +3466,16 @@ always @(*) begin end end end +assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; +assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; always @(*) begin - ddrphy_bankmodel5_read_data = 128'd0; - if (ddrphy_bankmodel5_active) begin - if (ddrphy_bankmodel5_read) begin - ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r; + ddrphy_bankmodel6_read_data = 128'd0; + if (ddrphy_bankmodel6_active) begin + if (ddrphy_bankmodel6_read) begin + ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r; end end end -assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; -assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; always @(*) begin ddrphy_bankmodel6_write_port_adr = 21'd0; if (ddrphy_bankmodel6_active) begin @@ -3498,16 +3506,14 @@ always @(*) begin end end end +assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3]; +assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3]; always @(*) begin - ddrphy_bankmodel6_read_data = 128'd0; - if (ddrphy_bankmodel6_active) begin - if (ddrphy_bankmodel6_read) begin - ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r; - end + ddrphy_bankmodel7_write_port_adr = 21'd0; + if (ddrphy_bankmodel7_active) begin + ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr; end end -assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3]; -assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3]; always @(*) begin ddrphy_bankmodel7_write_port_we = 16'd0; if (ddrphy_bankmodel7_active) begin @@ -3540,12 +3546,6 @@ always @(*) begin end end end -always @(*) begin - ddrphy_bankmodel7_write_port_adr = 21'd0; - if (ddrphy_bankmodel7_active) begin - ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr; - end -end assign ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; @@ -3675,563 +3675,563 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_master_p3_wrdata = 32'd0; + litedramcore_master_p2_we_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata; + litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n; end else begin - litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata; + litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n; end end always @(*) begin - litedramcore_inti_p0_rddata = 32'd0; + litedramcore_slave_p2_rddata_valid = 1'd0; if (litedramcore_sel) begin + litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid; end else begin - litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_master_p3_wrdata_en = 1'd0; + litedramcore_master_p2_cke = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en; + litedramcore_master_p2_cke = litedramcore_slave_p2_cke; end else begin - litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en; + litedramcore_master_p2_cke = litedramcore_inti_p2_cke; end end always @(*) begin - litedramcore_inti_p0_rddata_valid = 1'd0; + litedramcore_master_p2_odt = 1'd0; if (litedramcore_sel) begin + litedramcore_master_p2_odt = litedramcore_slave_p2_odt; end else begin - litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + litedramcore_master_p2_odt = litedramcore_inti_p2_odt; end end always @(*) begin - litedramcore_master_p3_wrdata_mask = 4'd0; + litedramcore_master_p2_reset_n = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n; end end always @(*) begin - litedramcore_master_p3_rddata_en = 1'd0; + litedramcore_master_p2_act_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en; + litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n; end else begin - litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en; + litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n; end end always @(*) begin - litedramcore_master_p0_address = 14'd0; + litedramcore_master_p2_wrdata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p0_address = litedramcore_slave_p0_address; + litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata; end else begin - litedramcore_master_p0_address = litedramcore_inti_p0_address; + litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata; end end always @(*) begin - litedramcore_master_p0_bank = 3'd0; + litedramcore_inti_p3_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p0_bank = litedramcore_slave_p0_bank; end else begin - litedramcore_master_p0_bank = litedramcore_inti_p0_bank; + litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata; end end always @(*) begin - litedramcore_master_p0_cas_n = 1'd1; + litedramcore_master_p2_wrdata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n; + litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n; + litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en; end end always @(*) begin - litedramcore_master_p0_cs_n = 1'd1; + litedramcore_inti_p3_rddata_valid = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n; + litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid; end end always @(*) begin - litedramcore_master_p0_ras_n = 1'd1; + litedramcore_master_p2_wrdata_mask = 4'd0; if (litedramcore_sel) begin - litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n; + litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n; + litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask; end end always @(*) begin - litedramcore_slave_p0_rddata = 32'd0; + litedramcore_master_p2_rddata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata; + litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en; end else begin + litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en; end end always @(*) begin - litedramcore_master_p0_we_n = 1'd1; + litedramcore_master_p3_address = 14'd0; if (litedramcore_sel) begin - litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n; + litedramcore_master_p3_address = litedramcore_slave_p3_address; end else begin - litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n; + litedramcore_master_p3_address = litedramcore_inti_p3_address; end end always @(*) begin - litedramcore_slave_p0_rddata_valid = 1'd0; + litedramcore_master_p3_bank = 3'd0; if (litedramcore_sel) begin - litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + litedramcore_master_p3_bank = litedramcore_slave_p3_bank; end else begin + litedramcore_master_p3_bank = litedramcore_inti_p3_bank; end end always @(*) begin - litedramcore_master_p0_cke = 1'd0; + litedramcore_master_p3_cas_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p0_cke = litedramcore_slave_p0_cke; + litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n; end else begin - litedramcore_master_p0_cke = litedramcore_inti_p0_cke; + litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n; end end always @(*) begin - litedramcore_master_p0_odt = 1'd0; + litedramcore_master_p3_cs_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p0_odt = litedramcore_slave_p0_odt; + litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p0_odt = litedramcore_inti_p0_odt; + litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n; end end always @(*) begin - litedramcore_master_p0_reset_n = 1'd0; + litedramcore_master_p3_ras_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n; + litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n; + litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n; end end always @(*) begin - litedramcore_master_p0_act_n = 1'd1; + litedramcore_slave_p3_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n; + litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata; end else begin - litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n; end end always @(*) begin - litedramcore_master_p0_wrdata = 32'd0; + litedramcore_master_p3_we_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata; + litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata; + litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n; end end always @(*) begin - litedramcore_inti_p1_rddata = 32'd0; + litedramcore_slave_p3_rddata_valid = 1'd0; if (litedramcore_sel) begin + litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid; end else begin - litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_master_p0_wrdata_en = 1'd0; + litedramcore_master_p3_cke = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en; + litedramcore_master_p3_cke = litedramcore_slave_p3_cke; end else begin - litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en; + litedramcore_master_p3_cke = litedramcore_inti_p3_cke; end end always @(*) begin - litedramcore_inti_p1_rddata_valid = 1'd0; + litedramcore_master_p3_odt = 1'd0; if (litedramcore_sel) begin + litedramcore_master_p3_odt = litedramcore_slave_p3_odt; end else begin - litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + litedramcore_master_p3_odt = litedramcore_inti_p3_odt; end end always @(*) begin - litedramcore_master_p0_wrdata_mask = 4'd0; + litedramcore_master_p3_reset_n = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n; end end always @(*) begin - litedramcore_master_p0_rddata_en = 1'd0; + litedramcore_master_p3_act_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en; + litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n; end else begin - litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en; + litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n; end end always @(*) begin - litedramcore_master_p1_address = 14'd0; + litedramcore_master_p3_wrdata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p1_address = litedramcore_slave_p1_address; + litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata; end else begin - litedramcore_master_p1_address = litedramcore_inti_p1_address; + litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata; end end always @(*) begin - litedramcore_master_p1_bank = 3'd0; + litedramcore_inti_p0_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p1_bank = litedramcore_slave_p1_bank; end else begin - litedramcore_master_p1_bank = litedramcore_inti_p1_bank; + litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_master_p1_cas_n = 1'd1; + litedramcore_master_p3_wrdata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n; + litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n; + litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en; end end always @(*) begin - litedramcore_master_p1_cs_n = 1'd1; + litedramcore_inti_p0_rddata_valid = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n; + litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid; end end always @(*) begin - litedramcore_master_p1_ras_n = 1'd1; + litedramcore_slave_p2_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n; + litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata; end else begin - litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n; end end always @(*) begin - litedramcore_slave_p1_rddata = 32'd0; + litedramcore_master_p3_wrdata_mask = 4'd0; if (litedramcore_sel) begin - litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata; + litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask; end else begin + litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask; end end always @(*) begin - litedramcore_master_p1_we_n = 1'd1; + litedramcore_master_p3_rddata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n; + litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n; + litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en; end end always @(*) begin - litedramcore_slave_p1_rddata_valid = 1'd0; + litedramcore_master_p0_address = 14'd0; if (litedramcore_sel) begin - litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + litedramcore_master_p0_address = litedramcore_slave_p0_address; end else begin + litedramcore_master_p0_address = litedramcore_inti_p0_address; end end always @(*) begin - litedramcore_master_p1_cke = 1'd0; + litedramcore_master_p0_bank = 3'd0; if (litedramcore_sel) begin - litedramcore_master_p1_cke = litedramcore_slave_p1_cke; + litedramcore_master_p0_bank = litedramcore_slave_p0_bank; end else begin - litedramcore_master_p1_cke = litedramcore_inti_p1_cke; + litedramcore_master_p0_bank = litedramcore_inti_p0_bank; end end always @(*) begin - litedramcore_master_p1_odt = 1'd0; + litedramcore_master_p0_cas_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p1_odt = litedramcore_slave_p1_odt; + litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n; end else begin - litedramcore_master_p1_odt = litedramcore_inti_p1_odt; + litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n; end end always @(*) begin - litedramcore_master_p1_reset_n = 1'd0; + litedramcore_master_p0_cs_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n; + litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n; + litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n; end end always @(*) begin - litedramcore_master_p1_act_n = 1'd1; + litedramcore_slave_p0_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n; + litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata; end else begin - litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n; end end always @(*) begin - litedramcore_master_p1_wrdata = 32'd0; + litedramcore_master_p0_ras_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata; + litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata; + litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n; end end always @(*) begin - litedramcore_inti_p2_rddata = 32'd0; + litedramcore_master_p0_we_n = 1'd1; if (litedramcore_sel) begin + litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n; end else begin - litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata; + litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n; end end always @(*) begin - litedramcore_master_p1_wrdata_en = 1'd0; + litedramcore_slave_p0_rddata_valid = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en; + litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid; end else begin - litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en; end end always @(*) begin - litedramcore_inti_p2_rddata_valid = 1'd0; + litedramcore_master_p0_cke = 1'd0; if (litedramcore_sel) begin + litedramcore_master_p0_cke = litedramcore_slave_p0_cke; end else begin - litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + litedramcore_master_p0_cke = litedramcore_inti_p0_cke; end end always @(*) begin - litedramcore_master_p1_wrdata_mask = 4'd0; + litedramcore_master_p0_odt = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p0_odt = litedramcore_slave_p0_odt; end else begin - litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p0_odt = litedramcore_inti_p0_odt; end end always @(*) begin - litedramcore_master_p1_rddata_en = 1'd0; + litedramcore_master_p0_reset_n = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en; + litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en; + litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n; end end always @(*) begin - litedramcore_master_p2_address = 14'd0; + litedramcore_master_p0_act_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p2_address = litedramcore_slave_p2_address; + litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n; end else begin - litedramcore_master_p2_address = litedramcore_inti_p2_address; + litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n; end end always @(*) begin - litedramcore_master_p2_bank = 3'd0; + litedramcore_master_p0_wrdata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p2_bank = litedramcore_slave_p2_bank; + litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata; end else begin - litedramcore_master_p2_bank = litedramcore_inti_p2_bank; + litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata; end end always @(*) begin - litedramcore_master_p2_cas_n = 1'd1; + litedramcore_inti_p1_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n; + litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_master_p2_cs_n = 1'd1; + litedramcore_master_p0_wrdata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n; + litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en; end else begin - litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n; + litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en; end end always @(*) begin - litedramcore_master_p2_ras_n = 1'd1; + litedramcore_inti_p1_rddata_valid = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n; end else begin - litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n; + litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid; end end always @(*) begin - litedramcore_slave_p2_rddata = 32'd0; + litedramcore_master_p0_wrdata_mask = 4'd0; if (litedramcore_sel) begin - litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata; + litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask; end else begin + litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask; end end always @(*) begin - litedramcore_master_p2_we_n = 1'd1; + litedramcore_master_p0_rddata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n; + litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n; + litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en; end end always @(*) begin - litedramcore_slave_p2_rddata_valid = 1'd0; + litedramcore_master_p1_address = 14'd0; if (litedramcore_sel) begin - litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + litedramcore_master_p1_address = litedramcore_slave_p1_address; end else begin + litedramcore_master_p1_address = litedramcore_inti_p1_address; end end always @(*) begin - litedramcore_master_p2_cke = 1'd0; + litedramcore_master_p1_bank = 3'd0; if (litedramcore_sel) begin - litedramcore_master_p2_cke = litedramcore_slave_p2_cke; + litedramcore_master_p1_bank = litedramcore_slave_p1_bank; end else begin - litedramcore_master_p2_cke = litedramcore_inti_p2_cke; + litedramcore_master_p1_bank = litedramcore_inti_p1_bank; end end always @(*) begin - litedramcore_master_p2_odt = 1'd0; + litedramcore_master_p1_cas_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p2_odt = litedramcore_slave_p2_odt; + litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n; end else begin - litedramcore_master_p2_odt = litedramcore_inti_p2_odt; + litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n; end end always @(*) begin - litedramcore_master_p2_reset_n = 1'd0; + litedramcore_master_p1_cs_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n; + litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n; + litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n; end end always @(*) begin - litedramcore_master_p2_act_n = 1'd1; + litedramcore_master_p1_ras_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n; + litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n; end else begin - litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n; + litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n; end end always @(*) begin - litedramcore_master_p2_wrdata = 32'd0; + litedramcore_slave_p1_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata; + litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata; end else begin - litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata; end end always @(*) begin - litedramcore_inti_p3_rddata = 32'd0; + litedramcore_master_p1_we_n = 1'd1; if (litedramcore_sel) begin + litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n; end else begin - litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata; + litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n; end end always @(*) begin - litedramcore_master_p2_wrdata_en = 1'd0; + litedramcore_slave_p1_rddata_valid = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en; + litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid; end else begin - litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en; end end always @(*) begin - litedramcore_inti_p3_rddata_valid = 1'd0; + litedramcore_master_p1_cke = 1'd0; if (litedramcore_sel) begin + litedramcore_master_p1_cke = litedramcore_slave_p1_cke; end else begin - litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + litedramcore_master_p1_cke = litedramcore_inti_p1_cke; end end always @(*) begin - litedramcore_master_p2_wrdata_mask = 4'd0; + litedramcore_master_p1_odt = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p1_odt = litedramcore_slave_p1_odt; end else begin - litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p1_odt = litedramcore_inti_p1_odt; end end always @(*) begin - litedramcore_master_p2_rddata_en = 1'd0; + litedramcore_master_p1_reset_n = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en; + litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en; + litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n; end end always @(*) begin - litedramcore_master_p3_address = 14'd0; + litedramcore_master_p1_act_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p3_address = litedramcore_slave_p3_address; + litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n; end else begin - litedramcore_master_p3_address = litedramcore_inti_p3_address; + litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n; end end always @(*) begin - litedramcore_master_p3_bank = 3'd0; + litedramcore_master_p1_wrdata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p3_bank = litedramcore_slave_p3_bank; + litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata; end else begin - litedramcore_master_p3_bank = litedramcore_inti_p3_bank; + litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata; end end always @(*) begin - litedramcore_master_p3_cas_n = 1'd1; + litedramcore_inti_p2_rddata = 32'd0; if (litedramcore_sel) begin - litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n; end else begin - litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n; + litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_master_p3_cs_n = 1'd1; + litedramcore_master_p1_wrdata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n; + litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n; + litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en; end end always @(*) begin - litedramcore_master_p3_ras_n = 1'd1; + litedramcore_inti_p2_rddata_valid = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n; + litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid; end end always @(*) begin - litedramcore_slave_p3_rddata = 32'd0; + litedramcore_master_p1_wrdata_mask = 4'd0; if (litedramcore_sel) begin - litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata; + litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask; end else begin + litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_we_n = 1'd1; + litedramcore_master_p1_rddata_en = 1'd0; if (litedramcore_sel) begin - litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n; + litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n; + litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en; end end always @(*) begin - litedramcore_slave_p3_rddata_valid = 1'd0; + litedramcore_master_p2_address = 14'd0; if (litedramcore_sel) begin - litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + litedramcore_master_p2_address = litedramcore_slave_p2_address; end else begin + litedramcore_master_p2_address = litedramcore_inti_p2_address; end end always @(*) begin - litedramcore_master_p3_cke = 1'd0; + litedramcore_master_p2_bank = 3'd0; if (litedramcore_sel) begin - litedramcore_master_p3_cke = litedramcore_slave_p3_cke; + litedramcore_master_p2_bank = litedramcore_slave_p2_bank; end else begin - litedramcore_master_p3_cke = litedramcore_inti_p3_cke; + litedramcore_master_p2_bank = litedramcore_inti_p2_bank; end end always @(*) begin - litedramcore_master_p3_odt = 1'd0; + litedramcore_master_p2_cas_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p3_odt = litedramcore_slave_p3_odt; + litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p3_odt = litedramcore_inti_p3_odt; + litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n; end end always @(*) begin - litedramcore_master_p3_reset_n = 1'd0; + litedramcore_master_p2_cs_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n; + litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n; end else begin - litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n; + litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n; end end always @(*) begin - litedramcore_master_p3_act_n = 1'd1; + litedramcore_master_p2_ras_n = 1'd1; if (litedramcore_sel) begin - litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n; + litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n; end else begin - litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n; + litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n; end end assign litedramcore_inti_p0_cke = litedramcore_cke; @@ -4246,6 +4246,14 @@ assign litedramcore_inti_p0_reset_n = litedramcore_reset_n; assign litedramcore_inti_p1_reset_n = litedramcore_reset_n; assign litedramcore_inti_p2_reset_n = litedramcore_reset_n; assign litedramcore_inti_p3_reset_n = litedramcore_reset_n; +always @(*) begin + litedramcore_inti_p0_we_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]); + end else begin + litedramcore_inti_p0_we_n = 1'd1; + end +end always @(*) begin litedramcore_inti_p0_cas_n = 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin @@ -4270,20 +4278,20 @@ always @(*) begin litedramcore_inti_p0_ras_n = 1'd1; end end -always @(*) begin - litedramcore_inti_p0_we_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]); - end else begin - litedramcore_inti_p0_we_n = 1'd1; - end -end assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_inti_p0_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p1_we_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]); + end else begin + litedramcore_inti_p1_we_n = 1'd1; + end +end always @(*) begin litedramcore_inti_p1_cas_n = 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin @@ -4308,20 +4316,20 @@ always @(*) begin litedramcore_inti_p1_ras_n = 1'd1; end end -always @(*) begin - litedramcore_inti_p1_we_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]); - end else begin - litedramcore_inti_p1_we_n = 1'd1; - end -end assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_inti_p1_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p2_we_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]); + end else begin + litedramcore_inti_p2_we_n = 1'd1; + end +end always @(*) begin litedramcore_inti_p2_cas_n = 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin @@ -4346,20 +4354,20 @@ always @(*) begin litedramcore_inti_p2_ras_n = 1'd1; end end -always @(*) begin - litedramcore_inti_p2_we_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]); - end else begin - litedramcore_inti_p2_we_n = 1'd1; - end -end assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_inti_p2_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p3_we_n = 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_we_n = (~litedramcore_phaseinjector3_command_storage[1]); + end else begin + litedramcore_inti_p3_we_n = 1'd1; + end +end always @(*) begin litedramcore_inti_p3_cas_n = 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin @@ -4384,14 +4392,6 @@ always @(*) begin litedramcore_inti_p3_ras_n = 1'd1; end end -always @(*) begin - litedramcore_inti_p3_we_n = 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_we_n = (~litedramcore_phaseinjector3_command_storage[1]); - end else begin - litedramcore_inti_p3_we_n = 1'd1; - end -end assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage; assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]); @@ -4499,22 +4499,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_sequencer_start0 = 1'd0; - case (refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 = 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_cmd_valid = 1'd0; case (refresher_state) @@ -4581,6 +4565,22 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_sequencer_start0 = 1'd0; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; @@ -4709,44 +4709,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_open = 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_close = 1'd0; + litedramcore_bankmachine0_req_wdata_ready = 1'd0; case (bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine0_row_close = 1'd1; end 3'd5: begin end @@ -4757,11 +4728,26 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas = 1'd0; + litedramcore_bankmachine0_req_rdata_valid = 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4785,7 +4771,10 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas = 1'd1; + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready; + end end else begin end end else begin @@ -4796,21 +4785,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras = 1'd0; + litedramcore_bankmachine0_refresh_gnt = 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -4825,16 +4811,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_we = 1'd0; + litedramcore_bankmachine0_cmd_valid = 1'd0; case (bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we = 1'd1; + litedramcore_bankmachine0_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -4852,10 +4841,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine0_cmd_valid = 1'd1; end else begin end end else begin @@ -4866,7 +4852,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine0_row_open = 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4874,7 +4860,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine0_row_open = 1'd1; end end 3'd4: begin @@ -4892,22 +4878,44 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine0_row_close = 1'd0; + case (bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -4922,7 +4930,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine0_cmd_payload_cas = 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4946,10 +4954,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; - end + litedramcore_bankmachine0_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -4960,9 +4965,41 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine0_cmd_payload_ras = 1'd0; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we = 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -4985,7 +5022,7 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; + litedramcore_bankmachine0_cmd_payload_we = 1'd1; end else begin end end else begin @@ -4998,15 +5035,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_wdata_ready = 1'd0; + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -5017,26 +5061,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_req_rdata_valid = 1'd0; + litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -5062,7 +5091,7 @@ always @(*) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin end else begin - litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready; + litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; end end else begin end @@ -5074,45 +5103,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_refresh_gnt = 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt = 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_valid = 1'd0; + litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -5130,7 +5127,10 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid = 1'd1; + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -5268,44 +5268,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_open = 1'd0; - case (bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_close = 1'd0; + litedramcore_bankmachine1_req_wdata_ready = 1'd0; case (bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close = 1'd1; end 3'd5: begin end @@ -5316,11 +5287,26 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas = 1'd0; + litedramcore_bankmachine1_req_rdata_valid = 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5344,7 +5330,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas = 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -5355,21 +5344,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras = 1'd0; + litedramcore_bankmachine1_refresh_gnt = 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -5384,16 +5370,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we = 1'd0; + litedramcore_bankmachine1_cmd_valid = 1'd0; case (bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we = 1'd1; + litedramcore_bankmachine1_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -5411,10 +5400,7 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine1_cmd_valid = 1'd1; end else begin end end else begin @@ -5425,7 +5411,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine1_row_open = 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5433,7 +5419,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine1_row_open = 1'd1; end end 3'd4: begin @@ -5451,22 +5437,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine1_row_close = 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; - end + litedramcore_bankmachine1_row_close = 1'd1; end 2'd2: begin + litedramcore_bankmachine1_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine1_row_close = 1'd1; end 3'd5: begin end @@ -5481,7 +5463,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine1_cmd_payload_cas = 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5505,10 +5487,7 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; - end + litedramcore_bankmachine1_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -5519,13 +5498,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine1_cmd_payload_ras = 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -5538,28 +5523,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_req_wdata_ready = 1'd0; + litedramcore_bankmachine1_cmd_payload_we = 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -5582,7 +5555,7 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready; + litedramcore_bankmachine1_cmd_payload_we = 1'd1; end else begin end end else begin @@ -5595,15 +5568,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_rdata_valid = 1'd0; + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -5614,26 +5594,37 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; end end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt = 1'd0; + litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5642,9 +5633,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -5655,23 +5643,32 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid = 1'd0; + litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -5689,7 +5686,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid = 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -5827,16 +5827,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_open = 1'd0; + litedramcore_bankmachine2_req_wdata_ready = 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open = 1'd1; - end end 3'd4: begin end @@ -5849,22 +5846,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_row_close = 1'd0; + litedramcore_bankmachine2_req_rdata_valid = 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close = 1'd1; end 3'd5: begin end @@ -5875,17 +5884,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas = 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -5898,37 +5925,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras = 1'd0; + litedramcore_bankmachine2_refresh_gnt = 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -5943,16 +5955,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we = 1'd0; + litedramcore_bankmachine2_cmd_valid = 1'd0; case (bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we = 1'd1; + litedramcore_bankmachine2_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -5970,10 +5985,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine2_cmd_valid = 1'd1; end else begin end end else begin @@ -5984,7 +5996,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine2_row_open = 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -5992,7 +6004,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine2_row_open = 1'd1; end end 3'd4: begin @@ -6010,22 +6022,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine2_row_close = 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; - end + litedramcore_bankmachine2_row_close = 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine2_row_close = 1'd1; end 3'd5: begin end @@ -6040,7 +6048,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine2_cmd_payload_cas = 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6064,10 +6072,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; - end + litedramcore_bankmachine2_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -6078,13 +6083,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine2_cmd_payload_ras = 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -6097,28 +6108,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_req_wdata_ready = 1'd0; + litedramcore_bankmachine2_cmd_payload_we = 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -6141,7 +6140,7 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready; + litedramcore_bankmachine2_cmd_payload_we = 1'd1; end else begin end end else begin @@ -6154,15 +6153,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid = 1'd0; + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -6173,26 +6179,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt = 1'd0; + litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6201,9 +6192,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -6214,23 +6202,32 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_valid = 1'd0; + litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -6248,7 +6245,10 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid = 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -6386,44 +6386,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_open = 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_close = 1'd0; + litedramcore_bankmachine3_req_wdata_ready = 1'd0; case (bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close = 1'd1; end 3'd5: begin end @@ -6434,11 +6405,26 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas = 1'd0; + litedramcore_bankmachine3_req_rdata_valid = 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6462,7 +6448,10 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas = 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready; + end end else begin end end else begin @@ -6473,21 +6462,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras = 1'd0; + litedramcore_bankmachine3_refresh_gnt = 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -6502,16 +6488,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we = 1'd0; + litedramcore_bankmachine3_cmd_valid = 1'd0; case (bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we = 1'd1; + litedramcore_bankmachine3_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -6529,10 +6518,7 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine3_cmd_valid = 1'd1; end else begin end end else begin @@ -6569,22 +6555,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine3_row_open = 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine3_row_open = 1'd1; end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -6599,15 +6581,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine3_row_close = 1'd0; case (bankmachine3_state) 1'd1: begin + litedramcore_bankmachine3_row_close = 1'd1; end 2'd2: begin + litedramcore_bankmachine3_row_close = 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine3_row_close = 1'd1; end 3'd5: begin end @@ -6618,26 +6603,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine3_cmd_payload_cas = 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6661,10 +6631,7 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; - end else begin - end + litedramcore_bankmachine3_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -6675,13 +6642,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_wdata_ready = 1'd0; + litedramcore_bankmachine3_cmd_payload_ras = 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -6694,28 +6667,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid = 1'd0; + litedramcore_bankmachine3_cmd_payload_we = 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -6738,8 +6699,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we = 1'd1; end else begin - litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6751,18 +6712,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt = 1'd0; + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt = 1'd1; - end + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -6777,20 +6742,52 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid = 1'd0; + litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid = 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end end end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end 3'd4: begin end 3'd5: begin @@ -6807,7 +6804,10 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid = 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -6945,44 +6945,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_open = 1'd0; - case (bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_close = 1'd0; + litedramcore_bankmachine4_req_wdata_ready = 1'd0; case (bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close = 1'd1; end 3'd5: begin end @@ -6993,11 +6964,26 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas = 1'd0; + litedramcore_bankmachine4_req_rdata_valid = 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7021,7 +7007,10 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas = 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready; + end end else begin end end else begin @@ -7032,21 +7021,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras = 1'd0; + litedramcore_bankmachine4_refresh_gnt = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -7061,16 +7047,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we = 1'd0; + litedramcore_bankmachine4_cmd_valid = 1'd0; case (bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we = 1'd1; + litedramcore_bankmachine4_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -7088,10 +7077,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine4_cmd_valid = 1'd1; end else begin end end else begin @@ -7102,7 +7088,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine4_row_open = 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7110,7 +7096,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine4_row_open = 1'd1; end end 3'd4: begin @@ -7128,22 +7114,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine4_row_close = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; - end + litedramcore_bankmachine4_row_close = 1'd1; end 2'd2: begin + litedramcore_bankmachine4_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine4_row_close = 1'd1; end 3'd5: begin end @@ -7158,7 +7140,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine4_cmd_payload_cas = 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7182,10 +7164,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; - end + litedramcore_bankmachine4_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -7196,13 +7175,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine4_cmd_payload_ras = 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -7215,28 +7200,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready = 1'd0; + litedramcore_bankmachine4_cmd_payload_we = 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -7259,7 +7232,7 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready; + litedramcore_bankmachine4_cmd_payload_we = 1'd1; end else begin end end else begin @@ -7272,7 +7245,37 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid = 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; + case (bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7298,7 +7301,7 @@ always @(*) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin end else begin - litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready; + litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; end end else begin end @@ -7310,18 +7313,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt = 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -7336,19 +7339,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid = 1'd0; + litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -7366,7 +7363,10 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -7504,7 +7504,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_open = 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7512,7 +7512,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open = 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; end end 3'd4: begin @@ -7530,18 +7530,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_close = 1'd0; + litedramcore_bankmachine5_req_wdata_ready = 1'd0; case (bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close = 1'd1; end 3'd5: begin end @@ -7552,11 +7549,26 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas = 1'd0; + litedramcore_bankmachine5_req_rdata_valid = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7580,7 +7592,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas = 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready; + end end else begin end end else begin @@ -7591,21 +7606,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras = 1'd0; + litedramcore_bankmachine5_refresh_gnt = 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -7620,16 +7632,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we = 1'd0; + litedramcore_bankmachine5_cmd_valid = 1'd0; case (bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we = 1'd1; + litedramcore_bankmachine5_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -7647,10 +7662,7 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine5_cmd_valid = 1'd1; end else begin end end else begin @@ -7661,7 +7673,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine5_row_open = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7669,7 +7681,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine5_row_open = 1'd1; end end 3'd4: begin @@ -7687,22 +7699,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine5_row_close = 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; - end + litedramcore_bankmachine5_row_close = 1'd1; end 2'd2: begin + litedramcore_bankmachine5_row_close = 1'd1; end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine5_row_close = 1'd1; end 3'd5: begin end @@ -7717,7 +7725,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine5_cmd_payload_cas = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7741,10 +7749,7 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; - end + litedramcore_bankmachine5_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -7755,13 +7760,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine5_cmd_payload_ras = 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -7774,28 +7785,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_req_wdata_ready = 1'd0; + litedramcore_bankmachine5_cmd_payload_we = 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -7818,7 +7817,7 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready; + litedramcore_bankmachine5_cmd_payload_we = 1'd1; end else begin end end else begin @@ -7831,15 +7830,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_rdata_valid = 1'd0; + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -7850,26 +7856,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_refresh_gnt = 1'd0; + litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7878,9 +7869,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -7891,23 +7879,32 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid = 1'd0; - case (bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; - end + litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; + case (bankmachine5_state) + 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -7925,7 +7922,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -8063,44 +8063,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_open = 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_close = 1'd0; + litedramcore_bankmachine6_req_wdata_ready = 1'd0; case (bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine6_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine6_row_close = 1'd1; end 3'd5: begin end @@ -8111,11 +8082,26 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas = 1'd0; + litedramcore_bankmachine6_req_rdata_valid = 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8139,7 +8125,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas = 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready; + end end else begin end end else begin @@ -8150,21 +8139,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras = 1'd0; + litedramcore_bankmachine6_refresh_gnt = 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -8179,16 +8165,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we = 1'd0; + litedramcore_bankmachine6_cmd_valid = 1'd0; case (bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we = 1'd1; + litedramcore_bankmachine6_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -8206,10 +8195,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine6_cmd_valid = 1'd1; end else begin end end else begin @@ -8246,22 +8232,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine6_row_open = 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine6_row_open = 1'd1; end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8276,15 +8258,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine6_row_close = 1'd0; case (bankmachine6_state) 1'd1: begin + litedramcore_bankmachine6_row_close = 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close = 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine6_row_close = 1'd1; end 3'd5: begin end @@ -8295,26 +8280,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine6_cmd_payload_cas = 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8338,10 +8308,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; - end else begin - end + litedramcore_bankmachine6_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -8352,13 +8319,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready = 1'd0; + litedramcore_bankmachine6_cmd_payload_ras = 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -8371,28 +8344,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid = 1'd0; + litedramcore_bankmachine6_cmd_payload_we = 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -8415,8 +8376,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we = 1'd1; end else begin - litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -8428,18 +8389,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt = 1'd0; + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt = 1'd1; - end + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8454,20 +8419,52 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_valid = 1'd0; + litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid = 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end end end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end 3'd4: begin end 3'd5: begin @@ -8484,7 +8481,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid = 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -8622,44 +8622,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_open = 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_close = 1'd0; + litedramcore_bankmachine7_req_wdata_ready = 1'd0; case (bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close = 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close = 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine7_row_close = 1'd1; end 3'd5: begin end @@ -8670,11 +8641,26 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas = 1'd0; + litedramcore_bankmachine7_req_rdata_valid = 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8698,7 +8684,10 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas = 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready; + end end else begin end end else begin @@ -8709,21 +8698,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras = 1'd0; + litedramcore_bankmachine7_refresh_gnt = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -8738,16 +8724,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we = 1'd0; + litedramcore_bankmachine7_cmd_valid = 1'd0; case (bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we = 1'd1; + litedramcore_bankmachine7_cmd_valid = 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + end end 3'd4: begin end @@ -8765,10 +8754,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we = 1'd1; - end else begin - end + litedramcore_bankmachine7_cmd_valid = 1'd1; end else begin end end else begin @@ -8779,7 +8765,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine7_row_open = 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8787,7 +8773,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine7_row_open = 1'd1; end end 3'd4: begin @@ -8805,22 +8791,44 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; + litedramcore_bankmachine7_row_close = 1'd0; + case (bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8835,7 +8843,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; + litedramcore_bankmachine7_cmd_payload_cas = 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8859,10 +8867,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; - end + litedramcore_bankmachine7_cmd_payload_cas = 1'd1; end else begin end end else begin @@ -8873,13 +8878,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine7_cmd_payload_ras = 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end end 3'd4: begin end @@ -8892,28 +8903,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_req_wdata_ready = 1'd0; + litedramcore_bankmachine7_cmd_payload_we = 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we = 1'd1; + end end 2'd2: begin end @@ -8936,7 +8935,7 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready; + litedramcore_bankmachine7_cmd_payload_we = 1'd1; end else begin end end else begin @@ -8949,15 +8948,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid = 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8968,26 +8974,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt = 1'd0; + litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8996,9 +8987,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -9009,23 +8997,32 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid = 1'd0; + litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -9043,7 +9040,10 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; + end else begin + end end else begin end end else begin @@ -9301,13 +9301,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_choose_req_cmd_ready = 1'd0; + litedramcore_choose_cmd_want_activates = 1'd0; case (multiplexer_state) 1'd1: begin if (1'd0) begin - litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); end else begin - litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; end end 2'd2: begin @@ -9332,18 +9331,17 @@ always @(*) begin end default: begin if (1'd0) begin - litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); end else begin - litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; end end endcase end always @(*) begin - litedramcore_en1 = 1'd0; + litedramcore_steerer_sel3 = 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 = 1'd1; + litedramcore_steerer_sel3 = 2'd2; end 2'd2: begin end @@ -9366,17 +9364,16 @@ always @(*) begin 4'd11: begin end default: begin + litedramcore_steerer_sel3 = 1'd0; end endcase end always @(*) begin - litedramcore_steerer_sel0 = 2'd0; + litedramcore_en0 = 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 = 1'd0; end 2'd2: begin - litedramcore_steerer_sel0 = 2'd3; end 2'd3: begin end @@ -9397,17 +9394,17 @@ always @(*) begin 4'd11: begin end default: begin - litedramcore_steerer_sel0 = 1'd0; + litedramcore_en0 = 1'd1; end endcase end always @(*) begin - litedramcore_steerer_sel1 = 2'd0; + litedramcore_cmd_ready = 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 = 1'd0; end 2'd2: begin + litedramcore_cmd_ready = 1'd1; end 2'd3: begin end @@ -9428,15 +9425,17 @@ always @(*) begin 4'd11: begin end default: begin - litedramcore_steerer_sel1 = 1'd1; end endcase end always @(*) begin - litedramcore_steerer_sel2 = 2'd0; + litedramcore_choose_cmd_cmd_ready = 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 = 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -9459,18 +9458,17 @@ always @(*) begin 4'd11: begin end default: begin - litedramcore_steerer_sel2 = 2'd2; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates = 1'd0; + litedramcore_choose_req_want_reads = 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; - end end 2'd2: begin end @@ -9493,18 +9491,15 @@ always @(*) begin 4'd11: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; - end + litedramcore_choose_req_want_reads = 1'd1; end endcase end always @(*) begin - litedramcore_steerer_sel3 = 2'd0; + litedramcore_choose_req_want_writes = 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 = 2'd2; + litedramcore_choose_req_want_writes = 1'd1; end 2'd2: begin end @@ -9527,14 +9522,18 @@ always @(*) begin 4'd11: begin end default: begin - litedramcore_steerer_sel3 = 1'd0; end endcase end always @(*) begin - litedramcore_en0 = 1'd0; + litedramcore_choose_req_cmd_ready = 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + end end 2'd2: begin end @@ -9557,17 +9556,21 @@ always @(*) begin 4'd11: begin end default: begin - litedramcore_en0 = 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + end end endcase end always @(*) begin - litedramcore_cmd_ready = 1'd0; + litedramcore_en1 = 1'd0; case (multiplexer_state) 1'd1: begin + litedramcore_en1 = 1'd1; end 2'd2: begin - litedramcore_cmd_ready = 1'd1; end 2'd3: begin end @@ -9592,15 +9595,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready = 1'd0; + litedramcore_steerer_sel0 = 2'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_steerer_sel0 = 1'd0; end 2'd2: begin + litedramcore_steerer_sel0 = 2'd3; end 2'd3: begin end @@ -9621,17 +9622,15 @@ always @(*) begin 4'd11: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_steerer_sel0 = 1'd0; end endcase end always @(*) begin - litedramcore_choose_req_want_reads = 1'd0; + litedramcore_steerer_sel1 = 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel1 = 1'd0; end 2'd2: begin end @@ -9654,15 +9653,15 @@ always @(*) begin 4'd11: begin end default: begin - litedramcore_choose_req_want_reads = 1'd1; + litedramcore_steerer_sel1 = 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes = 1'd0; + litedramcore_steerer_sel2 = 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes = 1'd1; + litedramcore_steerer_sel2 = 1'd1; end 2'd2: begin end @@ -9685,6 +9684,7 @@ always @(*) begin 4'd11: begin end default: begin + litedramcore_steerer_sel2 = 2'd2; end endcase end