From d794cc70b13f7538a98beffee3069db4aa9ea758 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Mon, 23 Aug 2021 10:30:40 +0800 Subject: [PATCH] orangecrab: No BTC, LOG_LENGTH, dram NUM_LINES Reduce litedram NUM_LINES 64->8 This allows us to meet timing. Can probably be improved in future with better BRAM usage. Signed-off-by: Matt Johnston --- fpga/top-orangecrab0.2.vhdl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/fpga/top-orangecrab0.2.vhdl b/fpga/top-orangecrab0.2.vhdl index 523a82d..c3cd332 100644 --- a/fpga/top-orangecrab0.2.vhdl +++ b/fpga/top-orangecrab0.2.vhdl @@ -13,19 +13,19 @@ entity toplevel is CLK_INPUT : positive := 100000000; CLK_FREQUENCY : positive := 100000000; HAS_FPU : boolean := true; - HAS_BTC : boolean := true; + HAS_BTC : boolean := false; USE_LITEDRAM : boolean := true; NO_BRAM : boolean := true; SCLK_STARTUPE2 : boolean := false; SPI_FLASH_OFFSET : integer := 4194304; SPI_FLASH_DEF_CKDV : natural := 1; SPI_FLASH_DEF_QUAD : boolean := true; - LOG_LENGTH : natural := 512; + LOG_LENGTH : natural := 0; UART_IS_16550 : boolean := true; HAS_UART1 : boolean := true; USE_LITESDCARD : boolean := false; ICACHE_NUM_LINES : natural := 64; - NGPIO : natural := 32 + NGPIO : natural := 0 ); port( ext_clk : in std_ulogic; @@ -332,6 +332,7 @@ begin DRAM_ALINES => 14, DRAM_DLINES => 16, DRAM_PORT_WIDTH => 128, + NUM_LINES => 8, -- reduce from default of 64 to make smaller/timing PAYLOAD_FILE => RAM_INIT_FILE, PAYLOAD_SIZE => PAYLOAD_SIZE )