From d89a9929fd376637a92b294777cfd298a7a28f91 Mon Sep 17 00:00:00 2001
From: Anton Blanchard <anton@linux.ibm.com>
Date: Thu, 12 Sep 2019 12:25:18 +1000
Subject: [PATCH] Fix clk_gen_bypass

I broke clk_gen_bypass when updating the SOC reset code.

Fixes 03fd06deaf9f ("Rework SOC reset")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---
 fpga/clk_gen_bypass.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/clk_gen_bypass.vhd b/fpga/clk_gen_bypass.vhd
index b204329..d583159 100644
--- a/fpga/clk_gen_bypass.vhd
+++ b/fpga/clk_gen_bypass.vhd
@@ -14,7 +14,7 @@ architecture bypass of clock_generator is
 
 begin
 
-  pll_locked_out <= pll_rst_in;
+  pll_locked_out <= not pll_rst_in;
   pll_clk_out <= ext_clk;
 
 end architecture bypass;