diff --git a/Makefile b/Makefile
index 87b69a4..4c14453 100644
--- a/Makefile
+++ b/Makefile
@@ -171,7 +171,7 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
+	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gLOG_LENGTH=8 -gHAS_FPU=false
 
 clkgen=fpga/clk_gen_ecp5.vhd
 toplevel=fpga/top-generic.vhdl
diff --git a/core.vhdl b/core.vhdl
index bc32a8c..c812bbd 100644
--- a/core.vhdl
+++ b/core.vhdl
@@ -209,7 +209,7 @@ begin
         generic map(
             SIM => SIM,
             LINE_SIZE => 64,
-            NUM_LINES => 64,
+            NUM_LINES => 2,
 	    NUM_WAYS => 2,
             LOG_LENGTH => LOG_LENGTH
             )
@@ -387,7 +387,7 @@ begin
     dcache_0: entity work.dcache
         generic map(
             LINE_SIZE => 64,
-            NUM_LINES => 64,
+            NUM_LINES => 2,
 	    NUM_WAYS => 2,
             LOG_LENGTH => LOG_LENGTH
             )
diff --git a/dcache.vhdl b/dcache.vhdl
index e99d8f4..637cf44 100644
--- a/dcache.vhdl
+++ b/dcache.vhdl
@@ -27,7 +27,7 @@ entity dcache is
         -- Number of ways
         NUM_WAYS  : positive := 4;
         -- L1 DTLB entries per set
-        TLB_SET_SIZE : positive := 64;
+        TLB_SET_SIZE : positive := 2;
         -- L1 DTLB number of sets
         TLB_NUM_WAYS : positive := 2;
         -- L1 DTLB log_2(page_size)
diff --git a/icache.vhdl b/icache.vhdl
index 759c5c0..246c83f 100644
--- a/icache.vhdl
+++ b/icache.vhdl
@@ -43,7 +43,7 @@ entity icache is
         -- Number of ways
         NUM_WAYS  : positive := 4;
         -- L1 ITLB number of entries (direct mapped)
-        TLB_SIZE : positive := 64;
+        TLB_SIZE : positive := 4;
         -- L1 ITLB log_2(page_size)
         TLB_LG_PGSZ : positive := 12;
         -- Number of real address bits that we store