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fpu-init
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dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
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remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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1 Commits (1383bbb8bece5828f84f317795b15154ae6ed5f8)

Author SHA1 Message Date
Matt Johnston a9b467f43b orangecrab: add Orange Crab r0.2 target 
top-orangecrab0.2 is a copy of top-arty with various changes.
USRMCLK is added for the SPI clock
ethernet is removed

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 3 years ago