8 Commits (3349bdc79891364f702b8ce977d14abfda46ae01)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	b513f0fb48	dcache: Add a dcache ... This replaces loadstore2 with a dcache The dcache unit is losely based on the icache one (same basic cache layout), but has some significant logic additions to deal with stores, loads with update, non-cachable accesses and other differences due to operating in the execution part of the pipeline rather than the fetch part. The cache is store-through, though a hit with an existing line will update the line rather than invalidate it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	687051ecbb	Reformat loadstore1 ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	a061924a78	Move byte reversal of stores to first cycle ... We are seeing some timing issues with the second cycle of loadstore, and we aren't doing much in the first cycle, so move it here. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	7caf71ba71	Fix issue in loadstore1 ... We weren't using the register in this stage. Fixes: 819f820090 ("Register outputs on loadstore1") Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	819f820090	Register outputs on loadstore1 ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	a8f8c54b77	Move debug execute output into decode2 ... This covers all units, and we avoid double printing. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	aee5fded44	Remove some more loadstore debug ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago