Commit Graph

2 Commits (83faae4a865997fa5fbc819922207779298ca4db)

Author SHA1 Message Date
Anton Blanchard 5e8ba5acb0 First pass at an external JTAG port
The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 3e8a6a8fc2 Add yosys/verilator support
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago