6 Commits (d2762e70e5fb519d8fcca210b366c9c8bbdd696a)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	79101041d6	wishbone: Add stall signal ... Pipelined wishbone needs it Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	6dd0b514ac	Reduce wishbone address size to 32-bit ... For now ... it reduces the routing pressure on the FPGA This needs manual adjustment of the address decoder in soc.vhdl, at least until I can figure out how to deal with std_match Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> # Conflicts: # soc.vhdl # Conflicts: # soc.vhdl	5 years ago
Benjamin Herrenschmidt	b513f0fb48	dcache: Add a dcache ... This replaces loadstore2 with a dcache The dcache unit is losely based on the icache one (same basic cache layout), but has some significant logic additions to deal with stores, loads with update, non-cachable accesses and other differences due to operating in the execution part of the pipeline rather than the fetch part. The cache is store-through, though a hit with an existing line will update the line rather than invalidate it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	df1165bdfc	Reformat wishbone code ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	142a722ce4	Remove names from end record statements ... These are optional, and vhdlpp from iverilog barfs on them. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago