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Commit Graph

  • 17fc77cef2 core: Implement PVR register Jordan Niethe 2020-07-07 20:37:52 +1000
  • 1697f8a08f Use $(GHDL) rather than ghdl in Makefile Michael Neuling 2020-07-04 11:12:05 +1000
  • 8bfc6a21b9 Add yosys/nextpnr ecp5 and verilog build to CI Michael Neuling 2020-06-22 13:10:13 +1000
  • 10a1a86ba0 Add FPGA_TARGET=ECP5-EVN make option for synthesis build Michael Neuling 2020-06-23 17:05:23 +1000
  • ef0dcf3bc6 Add SYNTH_ECP5_FLAGS option for building Michael Neuling 2020-07-02 14:36:14 +1000
  • 45fd2354f2 Add ram file to synthesis build dependencies Michael Neuling 2020-07-02 15:55:30 +1000
  • 7347786b08 Add uart16550 files to yosys/nextpnr build Michael Neuling 2020-07-02 14:34:43 +1000
  • aae45583d7 Add uart16550 files from fusesoc Michael Neuling 2020-07-02 14:11:16 +1000
  • 3f6d48f2fc Build to tmp file so nextpnr errors don't confuse make Michael Neuling 2020-06-22 13:09:09 +1000
  • 3e0ac8c94c Fix building with yosys/nextpnr Michael Neuling 2020-06-22 13:09:09 +1000
  • 3460afb557 Add yosys builds files to gitignore Michael Neuling 2020-06-22 13:11:03 +1000
  • b1c260599f Send line feed if we get a carriage return in hello world. Michael Neuling 2020-06-23 17:07:12 +1000
  • ce0205b262
         Merge pull request #216 from paulusmack/cfar Michael Neuling 2020-06-30 15:47:36 +1000
  • 419c9a68e8
         Merge pull request #206 from Jbalkind/icachecleanup Paul Mackerras 2020-06-30 15:01:06 +1000
  • 74062195ca execute1: Do forwarding of the CR result to the next instruction Paul Mackerras 2020-06-19 20:00:16 +1000
  • 0f0573903b execute1: Add latch to redirect path Paul Mackerras 2020-06-19 18:00:37 +1000
  • 9b40b5a77b logical: Only do output inversion for OP_AND, OP_OR and OP_XOR Paul Mackerras 2020-06-19 17:13:06 +1000
  • c2da82764f core: Implement CFAR register Paul Mackerras 2020-06-15 17:45:55 +1000
  • 57604c1a6e
         Merge pull request #213 from ozbenh/uart16550 Michael Neuling 2020-06-29 12:19:06 +1000
  • 9bbef035a6
         Merge pull request #212 from ozbenh/liteeth Michael Neuling 2020-06-29 12:18:44 +1000
  • cc27e239f4
         Merge pull request #214 from shingarov/fix-ld-target Michael Neuling 2020-06-29 10:24:49 +1000
  • 49f1389a21 Fix ld error in elf maketarget Boris Shingarov 2020-06-25 05:31:45 -0400
  • 434962bc34 tests: Add updated micropython build with 16550 support Benjamin Herrenschmidt 2020-06-19 21:18:33 +1000
  • fc4e13ae67 sim_console: Fix polling to check for POLLIN Benjamin Herrenschmidt 2020-06-19 20:27:31 +1000
  • fb5c16d05e uart: Make 16550 the default Benjamin Herrenschmidt 2020-06-18 17:14:55 +1000
  • b230677e93 syscon: Add flag to indicate the timebase frequency Benjamin Herrenschmidt 2020-06-23 15:44:37 +1000
  • d654667304 console: Add support for the 16550 UART Benjamin Herrenschmidt 2020-06-18 17:14:41 +1000
  • cc10f6b289 uart: Add a simulation model for the 16550 compatible UART Benjamin Herrenschmidt 2020-06-18 14:00:28 +1000
  • 4eae29801b uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl Benjamin Herrenschmidt 2020-06-18 11:18:30 +1000
  • e3941109af console: Cleanup console API Benjamin Herrenschmidt 2020-06-18 11:06:33 +1000
  • 7575b1e0c2 uart: Import and hook up opencore 16550 compatible UART Benjamin Herrenschmidt 2020-06-16 22:42:15 +1000
  • 76e2c7d81c ex1: Add SPR_TBU support Benjamin Herrenschmidt 2020-06-18 19:41:00 +1000
  • 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller Benjamin Herrenschmidt 2020-06-13 10:04:31 +1000
  • 7566f04fe3
         Merge pull request #211 from shenki/spi-constraint Michael Neuling 2020-06-23 16:58:06 +1000
  • 60e5f7b958 spi: Fix dat_i_l constraints Joel Stanley 2020-06-22 18:33:14 +0930
  • 695e081c35
         Merge pull request #210 from ozbenh/xics Michael Neuling 2020-06-23 14:32:42 +1000
  • bb54af59de xics: Add support for reduced priority field size Benjamin Herrenschmidt 2020-06-22 23:38:34 +1000
  • 5c2fc47e2c xics: Add simple ICS Benjamin Herrenschmidt 2020-06-17 22:11:58 +1000
  • 8080168327 xics/icp: MFRR starts at 0xff not 0x00 Benjamin Herrenschmidt 2020-06-17 22:07:33 +1000
  • 0b82024b01 tests/xics: Ensure no compiler optimisations in delay() Benjamin Herrenschmidt 2020-06-17 22:06:28 +1000
  • 0fa14f6dec xics: ICP should be big endian ! Benjamin Herrenschmidt 2020-06-17 21:51:16 +1000
  • 311b653d80 tests: Fix Makefile.test to not allow host includes Benjamin Herrenschmidt 2020-06-17 14:00:04 +1000
  • b90a0a2139
         Merge pull request #208 from paulusmack/faster Michael Neuling 2020-06-19 11:50:47 +1000
  • 1fedc7a86a
         Merge pull request #207 from ozbenh/misc Paul Mackerras 2020-06-18 07:26:01 +1000
  • 64efd494e5 fpga: Add a xilinx_specific fileset to microwatt.core Paul Mackerras 2020-06-16 16:59:54 +1000
  • 78de4fef72 Make LOG_LENGTH configurable per FPGA variant Paul Mackerras 2020-06-16 11:37:25 +1000
  • ec2fa61792 execute1: Reduce width of the result mux to help timing Paul Mackerras 2020-06-15 16:59:08 +1000
  • 6687aae4d6 core: Implement a simple branch predictor Paul Mackerras 2020-06-15 15:43:05 +1000
  • 09ae2ce58d decode1: Improve timing for slow SPR decode path Paul Mackerras 2020-06-15 10:02:14 +1000
  • b3799c432b decode1: Add a stash buffer to the output Paul Mackerras 2020-06-15 09:28:03 +1000
  • 67b6117ebf soc: Slight cleanup of IRQ assignments Benjamin Herrenschmidt 2020-06-13 22:29:54 +1000
  • e07b3dd6fa soc: Rename uart_dat8 to uart0_dat8 Benjamin Herrenschmidt 2020-06-13 22:05:39 +1000
  • f9f18906a3 soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding Benjamin Herrenschmidt 2020-06-13 22:04:45 +1000
  • d9bda521aa Minor refactor of icache to make less dependent on wishbone Jonathan Balkind 2020-06-13 18:39:18 -0400
  • a4500c63a2 dcache: Reduce back-to-back store latency from 3 cycles to 2 Paul Mackerras 2020-06-13 23:00:13 +1000
  • bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel Benjamin Herrenschmidt 2020-06-13 22:19:33 +1000
  • 1ffc89e58b soc: Add defaults for some input signals Benjamin Herrenschmidt 2020-06-13 21:57:01 +1000
  • 4244b54984 soc: Remove unused RESET_LOW generic Benjamin Herrenschmidt 2020-06-13 21:51:31 +1000
  • aebd915f8f mmu: Take an extra cycle to do TLB invalidations Paul Mackerras 2020-06-13 20:27:50 +1000
  • b595963233 dcache: Reduce latencies and improve timing Paul Mackerras 2020-06-11 14:23:50 +1000
  • 65a36cc0fc decode: Work out ispr1/ispr2 in parallel with decode ROM lookup Paul Mackerras 2020-05-12 16:28:42 +1000
  • 209aa9ce3f loadstore1: Reduce busy cycles Paul Mackerras 2020-06-05 14:22:02 +1000
  • 1d09daae03 loadstore1: Complete mfspr/mtspr a cycle later Paul Mackerras 2020-06-05 13:29:34 +1000
  • 6701e7346b core: Use a busy signal rather than a stall Paul Mackerras 2020-06-04 20:58:32 +1000
  • 62b24a8dae icache: Improve latencies when reloading cache lines Paul Mackerras 2020-05-29 09:38:05 +1000
  • 0809bc898b multiply: Use DSP48 slices for multiplication on Xilinx FPGAs Paul Mackerras 2020-05-21 17:50:54 +1000
  • 9880fc7435 multiply: Move selection of result bits into execute1 Paul Mackerras 2020-05-21 13:42:46 +1000
  • f80da65799 core: Double the dcache and icache sizes Paul Mackerras 2020-06-03 11:26:33 +1000
  • b5a7dbb78d core: Remove fetch2 pipeline stage Paul Mackerras 2020-05-10 18:18:03 +1000
  • 49a4d9f67a Add core logging Paul Mackerras 2020-05-14 13:25:48 +1000
  • aab84acda8 scripts/mw_debug: Make progress counts display on one line Paul Mackerras 2020-06-13 19:59:17 +1000
  • 03f9d7a97e tests/xics: Fix assumption that interrupts happen immediately Paul Mackerras 2020-06-11 14:57:30 +1000
  • 5a00029519 register_file: Report value being written before asserting it's not X Paul Mackerras 2020-06-13 17:22:56 +1000
  • 12a257f01e
         Merge pull request #205 from ozbenh/timing Paul Mackerras 2020-06-13 12:36:16 +1000
  • bf6cc2a05a
         Merge pull request #204 from ozbenh/spi Paul Mackerras 2020-06-13 12:27:40 +1000
  • 176ae5c306 syscon: Remove combinational loop on ack and stall Benjamin Herrenschmidt 2020-06-12 21:48:01 +1000
  • 6c3a8bf417 bram: Remove combinational loop on stall Benjamin Herrenschmidt 2020-06-12 21:47:06 +1000
  • e5aa0e9dc9 uart: Remove combinational loops on ack and stall signal Benjamin Herrenschmidt 2020-06-12 21:46:37 +1000
  • 6aadad5a75 spi: Add booting from flash to litedram init Benjamin Herrenschmidt 2020-06-10 13:35:18 +1000
  • a89e1469ef spi: Add simulation support Benjamin Herrenschmidt 2020-06-10 13:35:10 +1000
  • 801bd3b8ee
         flash-arty: update error message (#203) Dan Horák 2020-06-13 00:46:28 +0200
  • 9b458a9aa6
         dmi: Add ASYNC_REG attribute on synchronizers (#200) Benjamin Herrenschmidt 2020-06-13 08:44:43 +1000
  • d266c9e67d
         icache: Latch PLRU victim output (#199) Benjamin Herrenschmidt 2020-06-13 08:43:47 +1000
  • 41d28bbdfc
         Merge pull request #198 from ozbenh/litedram Paul Mackerras 2020-06-13 08:01:55 +1000
  • cc4dcb3597 spi: Add SPI Flash controller Benjamin Herrenschmidt 2020-06-05 11:32:08 +1000
  • 15467fe536 litedram: L2 use latched refill_index Benjamin Herrenschmidt 2020-06-11 20:18:24 +1000
  • 05bbbf0772 litedram: Pipeline store acks in L2 Benjamin Herrenschmidt 2020-06-10 23:45:42 +1000
  • 5ae5f76558 arty/nexys-video: Update XDC Benjamin Herrenschmidt 2020-06-10 19:06:02 +1000
  • b58ff724f6 litedram: Add stash buffer to the L2 cache wishbone interface Benjamin Herrenschmidt 2020-06-10 16:47:18 +1000
  • b23fd6c5f1 litedram: Defer clearing of tags & valids to improve timing Benjamin Herrenschmidt 2020-06-10 18:00:12 +1000
  • 7192ee825f litedram: Improve dram_tb error output Benjamin Herrenschmidt 2020-06-10 17:58:27 +1000
  • 7577cb18fb
         Merge pull request #201 from mikey/github-actions Anton Blanchard 2020-06-12 10:25:09 +1000
  • 9653b2952f Move from travis to github workflow Michael Neuling 2020-06-10 09:57:15 +1000
  • 6bb3837b33
         Merge pull request #194 from ozbenh/misc Paul Mackerras 2020-06-10 19:37:01 +1000
  • 183d05de86 gitignore: Add more exlusions Benjamin Herrenschmidt 2020-06-10 13:14:00 +1000
  • 63f10450a6 litedram: Fix DRAM init mem using too many address bits Benjamin Herrenschmidt 2020-06-10 08:36:44 +1000
  • a93d9e77c9 litedram: Remove remnants of riscv-inits Benjamin Herrenschmidt 2020-06-05 22:28:30 +1000
  • 3c99e6c31f mw_debug: Add "save" function to save memory to a file Benjamin Herrenschmidt 2020-06-04 20:25:57 +1000
  • 3167515069 sw: Properly mask syscon register fields Benjamin Herrenschmidt 2020-06-04 11:56:47 +1000
  • 13da4caafb
         Merge pull request #196 from ozbenh/makefile-lib-fix Michael Neuling 2020-06-10 09:54:35 +1000