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microwatt
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  • 0739b55bc2
         Merge pull request #195 from shenki/nexys-video Michael Neuling 2020-06-10 09:22:50 +1000
  • 097d19fd32 Makefile: Improve unisim library generation Benjamin Herrenschmidt 2020-06-10 08:31:49 +1000
  • fcdc01aa05 flash-arty: Re-add support for running from any path Joel Stanley 2020-06-09 11:22:57 +0930
  • 002858ddde flash-arty: Support Nexys Video's a200 Joel Stanley 2020-06-09 10:12:42 +0930
  • e46c46ab5f
         Merge pull request #193 from paulusmack/master Michael Neuling 2020-06-05 20:17:01 +1000
  • cff40237c7
         Merge pull request #182 from mikey/travis Paul Mackerras 2020-06-05 18:02:33 +1000
  • b863791e38
         icache: Fix icbi potentially clobbering the icache (#192) Benjamin Herrenschmidt 2020-06-05 16:23:23 +1000
  • afa82bea9c decode2: Reformat to 4-space indentation Paul Mackerras 2020-06-05 11:16:56 +1000
  • d5c8c33bae decode1: Reformat to 4-space indentation Paul Mackerras 2020-06-05 11:16:07 +1000
  • af909840e6 decode1: Make ld/std and lwa not be single-issue Paul Mackerras 2020-06-01 16:42:05 +1000
  • a740c4b7af Improve Travis to run as a matrix job Michael Neuling 2020-05-23 17:00:24 +1000
  • 6323f27423 Add unit tests to check and check_light Michael Neuling 2020-05-24 12:09:11 +1000
  • 809933a567 Add unit tests make target Michael Neuling 2020-05-24 12:08:47 +1000
  • 560a6f6b18 Add tests_console make target Michael Neuling 2020-05-23 16:59:51 +1000
  • 983f4fefe1
         Merge pull request #191 from ozbenh/litedram Paul Mackerras 2020-06-05 13:16:56 +1000
  • b0e15f2fb5 litedram: Make the L2 twice as tall Benjamin Herrenschmidt 2020-06-05 11:45:00 +1000
  • 4a4a98d4b9
         core: Do addpcis using the main adder (#189) Paul Mackerras 2020-06-05 11:29:31 +1000
  • 599fad117b litedram: Remove old "VexRiscV" based initializations Benjamin Herrenschmidt 2020-06-05 11:15:35 +1000
  • f089f2145a
         Merge pull request #183 from shawnanastasio/addpcis Paul Mackerras 2020-06-05 10:54:00 +1000
  • eaf6883e57 litedram: Update to latest LiteX/LiteDRAM version Benjamin Herrenschmidt 2020-06-01 23:58:47 +1000
  • 6828e93113 litedram: Test bench Benjamin Herrenschmidt 2020-06-02 08:32:17 +1000
  • a3857aac94 litedram: Add an L2 cache with store queue Benjamin Herrenschmidt 2020-05-27 11:06:51 +1000
  • bf1b98b958 litedram: Add support for booting without BRAM Benjamin Herrenschmidt 2020-05-25 20:20:59 +1000
  • 6fe077910b litedram: Add simulation support Benjamin Herrenschmidt 2020-05-22 18:43:50 +1000
  • 42e138e539
         Merge pull request #185 from ozbenh/misc Paul Mackerras 2020-06-05 09:29:24 +1000
  • 831ffceec7
         Merge pull request #188 from ozbenh/openocd-tweaks Michael Neuling 2020-06-05 08:38:18 +1000
  • d3c274d01e flash-arty: Add support for specifying the file type Benjamin Herrenschmidt 2020-06-04 23:29:29 +1000
  • 3592be733e flash-arty: Support hex values for address Benjamin Herrenschmidt 2020-06-04 23:13:45 +1000
  • 62233eddd7
         Merge pull request #168 from shenki/flash-arty Paul Mackerras 2020-06-03 14:20:02 +1000
  • ecaa5e2fb2 dcache: Rework RAM wrapper to synthetize better on Xilinx Benjamin Herrenschmidt 2020-05-25 16:48:47 +1000
  • a9178ed0c1 bin2hex: Make sure to generate little endian files Benjamin Herrenschmidt 2020-06-01 18:24:15 +1000
  • b8df0647fd mw_debug: Fix memory overflow with "sim" backend Benjamin Herrenschmidt 2020-05-29 00:04:46 +1000
  • 84ab28b3d2
         Merge pull request #178 from antonblanchard/intercon Anton Blanchard 2020-06-02 11:54:00 +1000
  • 4c1a73131b
         Merge pull request #184 from antonblanchard/verific Anton Blanchard 2020-06-02 10:36:06 +1000
  • ad1c8e7e14 Delete bit rotted verific script Michael Neuling 2020-05-26 16:55:20 +1000
  • 8b161c6dc6 Add a new misc test suite with addpcis tests Shawn Anastasio 2020-05-25 20:08:59 -0500
  • e606772aeb Implement the addpcis instruction Shawn Anastasio 2020-05-25 20:03:02 -0500
  • 12f36b4a35 litedram: Split the init memory from the main wrapper Benjamin Herrenschmidt 2020-05-20 21:00:27 +1000
  • f86fb74bfe irq: Simplify xics->core irq input Benjamin Herrenschmidt 2020-05-17 15:04:23 +1000
  • 573b6b4bc4 soc: Rework interconnect Benjamin Herrenschmidt 2020-05-11 21:22:07 +1000
  • 8d64090a68 sw: Add full memory map to .h and use it for litedram .lds Benjamin Herrenschmidt 2020-05-15 17:43:51 +1000
  • bdb428a40b
         Merge pull request #181 from antonblanchard/Makefile-rework-2 Anton Blanchard 2020-05-23 16:50:12 +1000
  • 04c56a0c52 Pass clock frequency to UART sim wrapper Anton Blanchard 2020-05-23 13:46:43 +1000
  • cb25167220
         Merge pull request #180 from antonblanchard/Makefile-rework Anton Blanchard 2020-05-21 12:29:55 +1000
  • 7b14819dbb A little less shouting in the Makefile Anton Blanchard 2020-05-20 16:27:06 +1000
  • 01da807476 Fix the simulated DMI Anton Blanchard 2020-05-20 16:18:58 +1000
  • ab86b58d95 Exit cleanly from testbench on success Anton Blanchard 2020-05-20 16:07:13 +1000
  • a9e7194de5 Merge Makefile and Makefile.synth Anton Blanchard 2020-05-20 15:37:49 +1000
  • 6326efaca4 Add Makefile command line variables to enable docker and podman Anton Blanchard 2020-05-20 15:01:42 +1000
  • 224e7734a8 Rework Makefile Anton Blanchard 2020-05-20 14:29:50 +1000
  • b82d07c8d5
         Merge pull request #179 from antonblanchard/yosys-verilator Anton Blanchard 2020-05-19 15:53:54 +1000
  • 8c028f26f1 Improve make clean Anton Blanchard 2020-05-19 15:32:04 +1000
  • 3e8a6a8fc2 Add yosys/verilator support Anton Blanchard 2020-05-19 15:18:42 +1000
  • 354e0fbfea
         Merge pull request #171 from shenki/mw-debug-features Anton Blanchard 2020-05-19 14:27:42 +1000
  • 6692f0db4f
         Merge pull request #173 from Jbalkind/core-vcs-syntax Anton Blanchard 2020-05-19 14:04:19 +1000
  • 5860c2d1b6 mw_debug: Add README Joel Stanley 2020-05-11 13:52:41 +0930
  • 2bf5bf4bac mw_debug: Add usage text Joel Stanley 2020-05-10 13:30:26 +0930
  • fa90f0dbb1 mw_debug: Add CFLAGS and fix warnings Joel Stanley 2020-05-11 13:22:00 +0930
  • 6d36ef93d9
         Merge pull request #177 from antonblanchard/litedram Anton Blanchard 2020-05-19 13:32:33 +1000
  • 4e78b8078e
         Merge branch 'master' into litedram Anton Blanchard 2020-05-19 12:28:02 +1000
  • e9251544f4
         Merge pull request #176 from antonblanchard/console-improv Anton Blanchard 2020-05-19 11:53:34 +1000
  • 03369a137c
         Merge pull request #175 from antonblanchard/yosys-fixes-2 Anton Blanchard 2020-05-19 11:38:16 +1000
  • cc532dd065 Changes for compilation with VCS: - Changing use of others in core files to satisfy VCS - Adding workaround for VCS subtype constraint inconsistencies in common.vhdl Jonathan Balkind 2020-05-14 17:17:15 -0400
  • 2aae3bf7a4 Fix yosys build after MMU merge Anton Blanchard 2020-05-19 11:22:29 +1000
  • 9287e80711
         Merge pull request #174 from antonblanchard/yosys-fixes Anton Blanchard 2020-05-19 10:44:04 +1000
  • f96d179f66 Some yosys fixes Anton Blanchard 2020-05-18 10:15:03 +1000
  • 7c4dab7eb0
         Merge pull request #169 from paulusmack/mmu Anton Blanchard 2020-05-19 09:34:41 +1000
  • 6efb31c924 litedram: Regenerate Benjamin Herrenschmidt 2020-05-15 13:31:11 +1000
  • acbdd396a5 soc/core: Add reset latches Benjamin Herrenschmidt 2020-05-15 13:30:01 +1000
  • 7560e8f2ff arty/nexys: Rework reset with litedram Benjamin Herrenschmidt 2020-05-15 13:20:27 +1000
  • 3b603402d2 soc_reset: Use counters, add synchronizers Benjamin Herrenschmidt 2020-05-15 13:15:48 +1000
  • 30fd9aa298 litedram: Forward system reset signal Benjamin Herrenschmidt 2020-05-15 13:11:58 +1000
  • c0f537b845 litedram: Remove init delays Benjamin Herrenschmidt 2020-05-15 10:14:53 +1000
  • c19b5b8cc7 litedram: Update to new LiteX/LiteDRAM version Benjamin Herrenschmidt 2020-05-12 20:27:15 +1000
  • eca0fb5bf1 dcache: Fix bug in store hit after dcbz case Paul Mackerras 2020-05-15 22:01:02 +1000
  • 13e84b0bbb pp_soc_uart: Fix rx synchronizers and ensure stable tx init state Benjamin Herrenschmidt 2020-05-14 14:26:14 +1000
  • bd42580a42 pp_fifo: Fix full fifo losing all data on simultaneous push & pop Benjamin Herrenschmidt 2020-05-14 12:30:11 +1000
  • 803ee9ef35 Makefile: Improve clean a bit Benjamin Herrenschmidt 2020-05-14 10:12:44 +1000
  • edbbf9a125 console: Remove putstr() Benjamin Herrenschmidt 2020-05-14 12:03:39 +1000
  • 7bc118c7db console: Move console files Benjamin Herrenschmidt 2020-05-14 10:08:06 +1000
  • a87b86e54f console: Replace putstr with puts Benjamin Herrenschmidt 2020-05-14 12:03:01 +1000
  • 88b28a7b17 console: Improve putchar(), add puts() Benjamin Herrenschmidt 2020-05-14 10:09:36 +1000
  • 941499133e soc: Work around compile error with ghdl 0.37-dev Paul Mackerras 2020-05-14 15:43:33 +1000
  • c164a2f4ea Merge branch 'mmu' Paul Mackerras 2020-05-14 15:41:51 +1000
  • fcec66acf4
         Merge pull request #170 from antonblanchard/litedram Anton Blanchard 2020-05-14 15:08:33 +1000
  • 60d2b8ac1e Add script for writing to flash on arty Joel Stanley 2020-05-06 11:50:17 +0930
  • e3013f5754 litedram: Use 32-bit CSR bus Benjamin Herrenschmidt 2020-05-09 11:20:59 +1000
  • 7f1f6b8525 litedram: Add support for Microwatt-initialized controller Benjamin Herrenschmidt 2020-05-09 01:09:26 +1000
  • c5f5f50738 hello_world: Use new headers and frequency from syscon Benjamin Herrenschmidt 2020-05-08 10:42:01 +1000
  • 12e8b0952d litedram: Improve sdram init boot messages Benjamin Herrenschmidt 2019-09-24 16:19:29 +1000
  • 33de131384 Add microwatt_soc.h and io.h include file Benjamin Herrenschmidt 2020-05-08 10:27:33 +1000
  • 025cf5efe8 syscon: Add syscon registers Benjamin Herrenschmidt 2019-09-24 22:24:31 +1000
  • 2cef3005cd fpga: Hookup nexys-video to litedram Benjamin Herrenschmidt 2019-09-11 10:59:13 +0100
  • 3ac815823c fpga: Hookup Arty to litedram Benjamin Herrenschmidt 2019-09-10 18:24:06 +0100
  • 2843c99a71 MMU: Implement reading of the process table Paul Mackerras 2020-04-24 10:58:56 +1000
  • f3c6119cf6 tests/mmu: Add a test of PTE refetching on permission error Paul Mackerras 2020-05-07 20:12:46 +1000
  • 8ff8b2f256 tests/mmu: Add a test for dcbz with translation on Paul Mackerras 2020-05-04 08:57:05 +1000
  • a658766fcf Implement slbia as a dTLB/iTLB flush Paul Mackerras 2020-05-07 20:02:21 +1000
  • f54a65f8cf Decode tlbiel as tlbie Paul Mackerras 2020-05-02 14:23:14 +1000
  • bee0c94fb4 tests/privileged: Update for instruction translation Paul Mackerras 2020-05-07 12:08:43 +1000