//-------------------------------------------------------------------------------- // Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01 //-------------------------------------------------------------------------------- module liteeth_core( input wire sys_clock, input wire sys_reset, output wire rgmii_eth_clocks_tx, input wire rgmii_eth_clocks_rx, output wire rgmii_eth_rst_n, input wire rgmii_eth_int_n, inout wire rgmii_eth_mdio, output wire rgmii_eth_mdc, input wire rgmii_eth_rx_ctl, input wire [3:0] rgmii_eth_rx_data, output wire rgmii_eth_tx_ctl, output wire [3:0] rgmii_eth_tx_data, input wire [29:0] wishbone_adr, input wire [31:0] wishbone_dat_w, output wire [31:0] wishbone_dat_r, input wire [3:0] wishbone_sel, input wire wishbone_cyc, input wire wishbone_stb, output wire wishbone_ack, input wire wishbone_we, input wire [2:0] wishbone_cti, input wire [1:0] wishbone_bte, output wire wishbone_err, output wire interrupt ); reg main_maccore_maccore_soc_rst = 1'd0; wire main_maccore_maccore_cpu_rst; reg [1:0] main_maccore_maccore_reset_storage = 2'd0; reg main_maccore_maccore_reset_re = 1'd0; reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; reg main_maccore_maccore_scratch_re = 1'd0; wire [31:0] main_maccore_maccore_bus_errors_status; wire main_maccore_maccore_bus_errors_we; reg main_maccore_maccore_bus_errors_re = 1'd0; wire main_maccore_maccore_bus_error; reg [31:0] main_maccore_maccore_bus_errors = 32'd0; (* dont_touch = "true" *) wire sys_clk; wire sys_rst; wire por_clk; reg main_maccore_int_rst = 1'd1; reg main_maccore_ethphy_reset_storage = 1'd0; reg main_maccore_ethphy_reset_re = 1'd0; (* dont_touch = "true" *) wire eth_rx_clk; wire eth_rx_rst; wire main_maccore_ethphy_eth_rx_clk_ibuf; (* dont_touch = "true" *) wire eth_tx_clk; wire eth_tx_rst; wire eth_tx_delayed_clk; reg main_maccore_ethphy_reset0 = 1'd0; reg main_maccore_ethphy_power_down = 1'd0; wire main_maccore_ethphy_locked; wire main_maccore_ethphy_clkin; wire main_maccore_ethphy_clkout0; wire main_maccore_ethphy_clkout_buf0; wire main_maccore_ethphy_clkout1; wire main_maccore_ethphy_clkout_buf1; wire main_maccore_ethphy_eth_tx_clk_obuf; wire main_maccore_ethphy_reset1; wire main_maccore_ethphy_sink_valid; wire main_maccore_ethphy_sink_ready; wire main_maccore_ethphy_sink_first; wire main_maccore_ethphy_sink_last; wire [7:0] main_maccore_ethphy_sink_payload_data; wire main_maccore_ethphy_sink_payload_last_be; wire main_maccore_ethphy_sink_payload_error; wire main_maccore_ethphy_tx_ctl_obuf; wire [3:0] main_maccore_ethphy_tx_data_obuf; reg main_maccore_ethphy_liteethphyrgmiirx_source_valid = 1'd0; wire main_maccore_ethphy_liteethphyrgmiirx_source_ready; reg main_maccore_ethphy_liteethphyrgmiirx_source_first = 1'd0; wire main_maccore_ethphy_liteethphyrgmiirx_source_last; reg [7:0] main_maccore_ethphy_liteethphyrgmiirx_source_payload_data = 8'd0; reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be = 1'd0; reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_error = 1'd0; wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf; wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay; wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf; wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay; wire [7:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data; wire main_maccore_ethphy_liteethphyrgmiirx; reg main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d = 1'd0; wire main_maccore_ethphy_liteethphyrgmiirx_last; wire main_maccore_ethphy_mdc; wire main_maccore_ethphy_oe; wire main_maccore_ethphy_w; reg [2:0] main_maccore_ethphy__w_storage = 3'd0; reg main_maccore_ethphy__w_re = 1'd0; reg main_maccore_ethphy_r = 1'd0; reg main_maccore_ethphy__r_status = 1'd0; wire main_maccore_ethphy__r_we; reg main_maccore_ethphy__r_re = 1'd0; wire main_maccore_ethphy_data_w; wire main_maccore_ethphy_data_oe; wire main_maccore_ethphy_data_r; wire main_tx_gap_inserter_sink_valid; reg main_tx_gap_inserter_sink_ready = 1'd0; wire main_tx_gap_inserter_sink_first; wire main_tx_gap_inserter_sink_last; wire [7:0] main_tx_gap_inserter_sink_payload_data; wire main_tx_gap_inserter_sink_payload_last_be; wire main_tx_gap_inserter_sink_payload_error; reg main_tx_gap_inserter_source_valid = 1'd0; wire main_tx_gap_inserter_source_ready; reg main_tx_gap_inserter_source_first = 1'd0; reg main_tx_gap_inserter_source_last = 1'd0; reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0; reg main_tx_gap_inserter_source_payload_last_be = 1'd0; reg main_tx_gap_inserter_source_payload_error = 1'd0; reg [3:0] main_tx_gap_inserter_counter = 4'd0; reg main_preamble_crc_status = 1'd1; wire main_preamble_crc_we; reg main_preamble_crc_re = 1'd0; reg [31:0] main_preamble_errors_status = 32'd0; wire main_preamble_errors_we; reg main_preamble_errors_re = 1'd0; reg [31:0] main_crc_errors_status = 32'd0; wire main_crc_errors_we; reg main_crc_errors_re = 1'd0; wire main_preamble_inserter_sink_valid; reg main_preamble_inserter_sink_ready = 1'd0; wire main_preamble_inserter_sink_first; wire main_preamble_inserter_sink_last; wire [7:0] main_preamble_inserter_sink_payload_data; wire main_preamble_inserter_sink_payload_last_be; wire main_preamble_inserter_sink_payload_error; reg main_preamble_inserter_source_valid = 1'd0; wire main_preamble_inserter_source_ready; reg main_preamble_inserter_source_first = 1'd0; reg main_preamble_inserter_source_last = 1'd0; reg [7:0] main_preamble_inserter_source_payload_data = 8'd0; wire main_preamble_inserter_source_payload_last_be; reg main_preamble_inserter_source_payload_error = 1'd0; reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013; reg [2:0] main_preamble_inserter_count = 3'd0; wire main_preamble_checker_sink_valid; reg main_preamble_checker_sink_ready = 1'd0; wire main_preamble_checker_sink_first; wire main_preamble_checker_sink_last; wire [7:0] main_preamble_checker_sink_payload_data; wire main_preamble_checker_sink_payload_last_be; wire main_preamble_checker_sink_payload_error; reg main_preamble_checker_source_valid = 1'd0; wire main_preamble_checker_source_ready; reg main_preamble_checker_source_first = 1'd0; reg main_preamble_checker_source_last = 1'd0; wire [7:0] main_preamble_checker_source_payload_data; wire main_preamble_checker_source_payload_last_be; reg main_preamble_checker_source_payload_error = 1'd0; reg main_preamble_checker_error = 1'd0; wire main_liteethmaccrc32inserter_sink_valid; reg main_liteethmaccrc32inserter_sink_ready = 1'd0; wire main_liteethmaccrc32inserter_sink_first; wire main_liteethmaccrc32inserter_sink_last; wire [7:0] main_liteethmaccrc32inserter_sink_payload_data; wire main_liteethmaccrc32inserter_sink_payload_last_be; wire main_liteethmaccrc32inserter_sink_payload_error; reg main_liteethmaccrc32inserter_source_valid = 1'd0; wire main_liteethmaccrc32inserter_source_ready; reg main_liteethmaccrc32inserter_source_first = 1'd0; reg main_liteethmaccrc32inserter_source_last = 1'd0; reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0; reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0; reg main_liteethmaccrc32inserter_source_payload_error = 1'd0; reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0; wire [31:0] main_liteethmaccrc32inserter_value; wire main_liteethmaccrc32inserter_error; wire [7:0] main_liteethmaccrc32inserter_data1; wire [31:0] main_liteethmaccrc32inserter_last; reg [31:0] main_liteethmaccrc32inserter_next = 32'd0; reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295; reg main_liteethmaccrc32inserter_ce = 1'd0; reg main_liteethmaccrc32inserter_reset = 1'd0; reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3; wire main_liteethmaccrc32inserter_cnt_done; reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0; reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0; wire main_crc32_inserter_sink_valid; wire main_crc32_inserter_sink_ready; wire main_crc32_inserter_sink_first; wire main_crc32_inserter_sink_last; wire [7:0] main_crc32_inserter_sink_payload_data; wire main_crc32_inserter_sink_payload_last_be; wire main_crc32_inserter_sink_payload_error; reg main_crc32_inserter_source_valid = 1'd0; wire main_crc32_inserter_source_ready; reg main_crc32_inserter_source_first = 1'd0; reg main_crc32_inserter_source_last = 1'd0; reg [7:0] main_crc32_inserter_source_payload_data = 8'd0; reg main_crc32_inserter_source_payload_last_be = 1'd0; reg main_crc32_inserter_source_payload_error = 1'd0; wire main_liteethmaccrc32checker_sink_sink_valid; reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; wire main_liteethmaccrc32checker_sink_sink_first; wire main_liteethmaccrc32checker_sink_sink_last; wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; wire main_liteethmaccrc32checker_sink_sink_payload_last_be; wire main_liteethmaccrc32checker_sink_sink_payload_error; wire main_liteethmaccrc32checker_source_source_valid; wire main_liteethmaccrc32checker_source_source_ready; reg main_liteethmaccrc32checker_source_source_first = 1'd0; wire main_liteethmaccrc32checker_source_source_last; wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; wire main_liteethmaccrc32checker_source_source_payload_last_be; reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; wire main_liteethmaccrc32checker_error; wire [7:0] main_liteethmaccrc32checker_crc_data0; wire [31:0] main_liteethmaccrc32checker_crc_value; wire main_liteethmaccrc32checker_crc_error; wire [7:0] main_liteethmaccrc32checker_crc_data1; wire [31:0] main_liteethmaccrc32checker_crc_last; reg [31:0] main_liteethmaccrc32checker_crc_next = 32'd0; reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; reg main_liteethmaccrc32checker_crc_ce = 1'd0; reg main_liteethmaccrc32checker_crc_reset = 1'd0; reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; wire main_liteethmaccrc32checker_syncfifo_sink_ready; wire main_liteethmaccrc32checker_syncfifo_sink_first; wire main_liteethmaccrc32checker_syncfifo_sink_last; wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; wire main_liteethmaccrc32checker_syncfifo_source_valid; wire main_liteethmaccrc32checker_syncfifo_source_ready; wire main_liteethmaccrc32checker_syncfifo_source_first; wire main_liteethmaccrc32checker_syncfifo_source_last; wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; wire main_liteethmaccrc32checker_syncfifo_source_payload_error; wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; wire main_liteethmaccrc32checker_syncfifo_wrport_we; wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; wire main_liteethmaccrc32checker_syncfifo_do_read; wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; reg main_liteethmaccrc32checker_fifo_reset = 1'd0; wire main_liteethmaccrc32checker_fifo_in; wire main_liteethmaccrc32checker_fifo_out; wire main_liteethmaccrc32checker_fifo_full; wire main_crc32_checker_sink_valid; wire main_crc32_checker_sink_ready; wire main_crc32_checker_sink_first; wire main_crc32_checker_sink_last; wire [7:0] main_crc32_checker_sink_payload_data; wire main_crc32_checker_sink_payload_last_be; wire main_crc32_checker_sink_payload_error; reg main_crc32_checker_source_valid = 1'd0; wire main_crc32_checker_source_ready; reg main_crc32_checker_source_first = 1'd0; reg main_crc32_checker_source_last = 1'd0; reg [7:0] main_crc32_checker_source_payload_data = 8'd0; reg main_crc32_checker_source_payload_last_be = 1'd0; reg main_crc32_checker_source_payload_error = 1'd0; wire main_ps_preamble_error_i; wire main_ps_preamble_error_o; reg main_ps_preamble_error_toggle_i = 1'd0; wire main_ps_preamble_error_toggle_o; reg main_ps_preamble_error_toggle_o_r = 1'd0; wire main_ps_crc_error_i; wire main_ps_crc_error_o; reg main_ps_crc_error_toggle_i = 1'd0; wire main_ps_crc_error_toggle_o; reg main_ps_crc_error_toggle_o_r = 1'd0; wire main_padding_inserter_sink_valid; reg main_padding_inserter_sink_ready = 1'd0; wire main_padding_inserter_sink_first; wire main_padding_inserter_sink_last; wire [7:0] main_padding_inserter_sink_payload_data; wire main_padding_inserter_sink_payload_last_be; wire main_padding_inserter_sink_payload_error; reg main_padding_inserter_source_valid = 1'd0; wire main_padding_inserter_source_ready; reg main_padding_inserter_source_first = 1'd0; reg main_padding_inserter_source_last = 1'd0; reg [7:0] main_padding_inserter_source_payload_data = 8'd0; reg main_padding_inserter_source_payload_last_be = 1'd0; reg main_padding_inserter_source_payload_error = 1'd0; reg [15:0] main_padding_inserter_counter = 16'd0; wire main_padding_inserter_counter_done; wire main_padding_checker_sink_valid; wire main_padding_checker_sink_ready; wire main_padding_checker_sink_first; wire main_padding_checker_sink_last; wire [7:0] main_padding_checker_sink_payload_data; wire main_padding_checker_sink_payload_last_be; wire main_padding_checker_sink_payload_error; wire main_padding_checker_source_valid; wire main_padding_checker_source_ready; wire main_padding_checker_source_first; wire main_padding_checker_source_last; wire [7:0] main_padding_checker_source_payload_data; wire main_padding_checker_source_payload_last_be; wire main_padding_checker_source_payload_error; wire main_tx_last_be_sink_valid; reg main_tx_last_be_sink_ready = 1'd0; wire main_tx_last_be_sink_first; wire main_tx_last_be_sink_last; wire [7:0] main_tx_last_be_sink_payload_data; wire main_tx_last_be_sink_payload_last_be; wire main_tx_last_be_sink_payload_error; reg main_tx_last_be_source_valid = 1'd0; wire main_tx_last_be_source_ready; reg main_tx_last_be_source_first = 1'd0; reg main_tx_last_be_source_last = 1'd0; reg [7:0] main_tx_last_be_source_payload_data = 8'd0; reg main_tx_last_be_source_payload_last_be = 1'd0; reg main_tx_last_be_source_payload_error = 1'd0; wire main_rx_last_be_sink_valid; wire main_rx_last_be_sink_ready; wire main_rx_last_be_sink_first; wire main_rx_last_be_sink_last; wire [7:0] main_rx_last_be_sink_payload_data; wire main_rx_last_be_sink_payload_last_be; wire main_rx_last_be_sink_payload_error; wire main_rx_last_be_source_valid; wire main_rx_last_be_source_ready; wire main_rx_last_be_source_first; wire main_rx_last_be_source_last; wire [7:0] main_rx_last_be_source_payload_data; reg main_rx_last_be_source_payload_last_be = 1'd0; wire main_rx_last_be_source_payload_error; wire main_tx_converter_sink_valid; wire main_tx_converter_sink_ready; wire main_tx_converter_sink_first; wire main_tx_converter_sink_last; wire [31:0] main_tx_converter_sink_payload_data; wire [3:0] main_tx_converter_sink_payload_last_be; wire [3:0] main_tx_converter_sink_payload_error; wire main_tx_converter_source_valid; wire main_tx_converter_source_ready; wire main_tx_converter_source_first; wire main_tx_converter_source_last; wire [7:0] main_tx_converter_source_payload_data; wire main_tx_converter_source_payload_last_be; wire main_tx_converter_source_payload_error; wire main_tx_converter_converter_sink_valid; wire main_tx_converter_converter_sink_ready; wire main_tx_converter_converter_sink_first; wire main_tx_converter_converter_sink_last; reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; wire main_tx_converter_converter_source_valid; wire main_tx_converter_converter_source_ready; wire main_tx_converter_converter_source_first; wire main_tx_converter_converter_source_last; reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; wire main_tx_converter_converter_source_payload_valid_token_count; reg [1:0] main_tx_converter_converter_mux = 2'd0; wire main_tx_converter_converter_first; wire main_tx_converter_converter_last; wire main_tx_converter_source_source_valid; wire main_tx_converter_source_source_ready; wire main_tx_converter_source_source_first; wire main_tx_converter_source_source_last; wire [9:0] main_tx_converter_source_source_payload_data; wire main_rx_converter_sink_valid; wire main_rx_converter_sink_ready; wire main_rx_converter_sink_first; wire main_rx_converter_sink_last; wire [7:0] main_rx_converter_sink_payload_data; wire main_rx_converter_sink_payload_last_be; wire main_rx_converter_sink_payload_error; wire main_rx_converter_source_valid; wire main_rx_converter_source_ready; wire main_rx_converter_source_first; wire main_rx_converter_source_last; reg [31:0] main_rx_converter_source_payload_data = 32'd0; reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; reg [3:0] main_rx_converter_source_payload_error = 4'd0; wire main_rx_converter_converter_sink_valid; wire main_rx_converter_converter_sink_ready; wire main_rx_converter_converter_sink_first; wire main_rx_converter_converter_sink_last; wire [9:0] main_rx_converter_converter_sink_payload_data; wire main_rx_converter_converter_source_valid; wire main_rx_converter_converter_source_ready; reg main_rx_converter_converter_source_first = 1'd0; reg main_rx_converter_converter_source_last = 1'd0; reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; reg [1:0] main_rx_converter_converter_demux = 2'd0; wire main_rx_converter_converter_load_part; reg main_rx_converter_converter_strobe_all = 1'd0; wire main_rx_converter_source_source_valid; wire main_rx_converter_source_source_ready; wire main_rx_converter_source_source_first; wire main_rx_converter_source_source_last; wire [39:0] main_rx_converter_source_source_payload_data; wire main_tx_cdc_sink_sink_valid; wire main_tx_cdc_sink_sink_ready; wire main_tx_cdc_sink_sink_first; wire main_tx_cdc_sink_sink_last; wire [31:0] main_tx_cdc_sink_sink_payload_data; wire [3:0] main_tx_cdc_sink_sink_payload_last_be; wire [3:0] main_tx_cdc_sink_sink_payload_error; wire main_tx_cdc_source_source_valid; wire main_tx_cdc_source_source_ready; wire main_tx_cdc_source_source_first; wire main_tx_cdc_source_source_last; wire [31:0] main_tx_cdc_source_source_payload_data; wire [3:0] main_tx_cdc_source_source_payload_last_be; wire [3:0] main_tx_cdc_source_source_payload_error; wire main_tx_cdc_cdc_sink_valid; wire main_tx_cdc_cdc_sink_ready; wire main_tx_cdc_cdc_sink_first; wire main_tx_cdc_cdc_sink_last; wire [31:0] main_tx_cdc_cdc_sink_payload_data; wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; wire [3:0] main_tx_cdc_cdc_sink_payload_error; wire main_tx_cdc_cdc_source_valid; wire main_tx_cdc_cdc_source_ready; wire main_tx_cdc_cdc_source_first; wire main_tx_cdc_cdc_source_last; wire [31:0] main_tx_cdc_cdc_source_payload_data; wire [3:0] main_tx_cdc_cdc_source_payload_last_be; wire [3:0] main_tx_cdc_cdc_source_payload_error; wire main_tx_cdc_cdc_asyncfifo_we; wire main_tx_cdc_cdc_asyncfifo_writable; wire main_tx_cdc_cdc_asyncfifo_re; wire main_tx_cdc_cdc_asyncfifo_readable; wire [41:0] main_tx_cdc_cdc_asyncfifo_din; wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; wire main_tx_cdc_cdc_graycounter0_ce; (* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; wire main_tx_cdc_cdc_graycounter1_ce; (* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; wire [5:0] main_tx_cdc_cdc_produce_rdomain; wire [5:0] main_tx_cdc_cdc_consume_wdomain; wire [4:0] main_tx_cdc_cdc_wrport_adr; wire [41:0] main_tx_cdc_cdc_wrport_dat_r; wire main_tx_cdc_cdc_wrport_we; wire [41:0] main_tx_cdc_cdc_wrport_dat_w; wire [4:0] main_tx_cdc_cdc_rdport_adr; wire [41:0] main_tx_cdc_cdc_rdport_dat_r; wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; wire main_tx_cdc_cdc_fifo_in_first; wire main_tx_cdc_cdc_fifo_in_last; wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; wire main_tx_cdc_cdc_fifo_out_first; wire main_tx_cdc_cdc_fifo_out_last; wire main_rx_cdc_sink_sink_valid; wire main_rx_cdc_sink_sink_ready; wire main_rx_cdc_sink_sink_first; wire main_rx_cdc_sink_sink_last; wire [31:0] main_rx_cdc_sink_sink_payload_data; wire [3:0] main_rx_cdc_sink_sink_payload_last_be; wire [3:0] main_rx_cdc_sink_sink_payload_error; wire main_rx_cdc_source_source_valid; wire main_rx_cdc_source_source_ready; wire main_rx_cdc_source_source_first; wire main_rx_cdc_source_source_last; wire [31:0] main_rx_cdc_source_source_payload_data; wire [3:0] main_rx_cdc_source_source_payload_last_be; wire [3:0] main_rx_cdc_source_source_payload_error; wire main_rx_cdc_cdc_sink_valid; wire main_rx_cdc_cdc_sink_ready; wire main_rx_cdc_cdc_sink_first; wire main_rx_cdc_cdc_sink_last; wire [31:0] main_rx_cdc_cdc_sink_payload_data; wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; wire [3:0] main_rx_cdc_cdc_sink_payload_error; wire main_rx_cdc_cdc_source_valid; wire main_rx_cdc_cdc_source_ready; wire main_rx_cdc_cdc_source_first; wire main_rx_cdc_cdc_source_last; wire [31:0] main_rx_cdc_cdc_source_payload_data; wire [3:0] main_rx_cdc_cdc_source_payload_last_be; wire [3:0] main_rx_cdc_cdc_source_payload_error; wire main_rx_cdc_cdc_asyncfifo_we; wire main_rx_cdc_cdc_asyncfifo_writable; wire main_rx_cdc_cdc_asyncfifo_re; wire main_rx_cdc_cdc_asyncfifo_readable; wire [41:0] main_rx_cdc_cdc_asyncfifo_din; wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; wire main_rx_cdc_cdc_graycounter0_ce; (* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; wire main_rx_cdc_cdc_graycounter1_ce; (* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; wire [5:0] main_rx_cdc_cdc_produce_rdomain; wire [5:0] main_rx_cdc_cdc_consume_wdomain; wire [4:0] main_rx_cdc_cdc_wrport_adr; wire [41:0] main_rx_cdc_cdc_wrport_dat_r; wire main_rx_cdc_cdc_wrport_we; wire [41:0] main_rx_cdc_cdc_wrport_dat_w; wire [4:0] main_rx_cdc_cdc_rdport_adr; wire [41:0] main_rx_cdc_cdc_rdport_dat_r; wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; wire main_rx_cdc_cdc_fifo_in_first; wire main_rx_cdc_cdc_fifo_in_last; wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; wire main_rx_cdc_cdc_fifo_out_first; wire main_rx_cdc_cdc_fifo_out_last; wire main_sink_valid; wire main_sink_ready; wire main_sink_first; wire main_sink_last; wire [31:0] main_sink_payload_data; wire [3:0] main_sink_payload_last_be; wire [3:0] main_sink_payload_error; wire main_source_valid; wire main_source_ready; wire main_source_first; wire main_source_last; wire [31:0] main_source_payload_data; wire [3:0] main_source_payload_last_be; wire [3:0] main_source_payload_error; wire [29:0] main_bus_adr; wire [31:0] main_bus_dat_w; wire [31:0] main_bus_dat_r; wire [3:0] main_bus_sel; wire main_bus_cyc; wire main_bus_stb; wire main_bus_ack; wire main_bus_we; wire [2:0] main_bus_cti; wire [1:0] main_bus_bte; wire main_bus_err; wire main_writer_sink_sink_valid; reg main_writer_sink_sink_ready = 1'd1; wire main_writer_sink_sink_first; wire main_writer_sink_sink_last; wire [31:0] main_writer_sink_sink_payload_data; wire [3:0] main_writer_sink_sink_payload_last_be; wire [3:0] main_writer_sink_sink_payload_error; wire main_writer_slot_status; wire main_writer_slot_we; reg main_writer_slot_re = 1'd0; wire [31:0] main_writer_length_status; wire main_writer_length_we; reg main_writer_length_re = 1'd0; reg [31:0] main_writer_errors_status = 32'd0; wire main_writer_errors_we; reg main_writer_errors_re = 1'd0; wire main_writer_irq; wire main_writer_available_status; wire main_writer_available_pending; wire main_writer_available_trigger; reg main_writer_available_clear = 1'd0; wire main_writer_available0; wire main_writer_status_status; wire main_writer_status_we; reg main_writer_status_re = 1'd0; wire main_writer_available1; wire main_writer_pending_status; wire main_writer_pending_we; reg main_writer_pending_re = 1'd0; reg main_writer_pending_r = 1'd0; wire main_writer_available2; reg main_writer_enable_storage = 1'd0; reg main_writer_enable_re = 1'd0; reg [2:0] main_writer_inc = 3'd0; reg [31:0] main_writer_counter = 32'd0; reg main_writer_slot = 1'd0; reg main_writer_slot_ce = 1'd0; reg main_writer_start = 1'd0; reg main_writer_ongoing = 1'd0; reg main_writer_stat_fifo_sink_valid = 1'd0; wire main_writer_stat_fifo_sink_ready; reg main_writer_stat_fifo_sink_first = 1'd0; reg main_writer_stat_fifo_sink_last = 1'd0; wire main_writer_stat_fifo_sink_payload_slot; wire [31:0] main_writer_stat_fifo_sink_payload_length; wire main_writer_stat_fifo_source_valid; wire main_writer_stat_fifo_source_ready; wire main_writer_stat_fifo_source_first; wire main_writer_stat_fifo_source_last; wire main_writer_stat_fifo_source_payload_slot; wire [31:0] main_writer_stat_fifo_source_payload_length; wire main_writer_stat_fifo_syncfifo_we; wire main_writer_stat_fifo_syncfifo_writable; wire main_writer_stat_fifo_syncfifo_re; wire main_writer_stat_fifo_syncfifo_readable; wire [34:0] main_writer_stat_fifo_syncfifo_din; wire [34:0] main_writer_stat_fifo_syncfifo_dout; reg [1:0] main_writer_stat_fifo_level = 2'd0; reg main_writer_stat_fifo_replace = 1'd0; reg main_writer_stat_fifo_produce = 1'd0; reg main_writer_stat_fifo_consume = 1'd0; reg main_writer_stat_fifo_wrport_adr = 1'd0; wire [34:0] main_writer_stat_fifo_wrport_dat_r; wire main_writer_stat_fifo_wrport_we; wire [34:0] main_writer_stat_fifo_wrport_dat_w; wire main_writer_stat_fifo_do_read; wire main_writer_stat_fifo_rdport_adr; wire [34:0] main_writer_stat_fifo_rdport_dat_r; wire main_writer_stat_fifo_fifo_in_payload_slot; wire [31:0] main_writer_stat_fifo_fifo_in_payload_length; wire main_writer_stat_fifo_fifo_in_first; wire main_writer_stat_fifo_fifo_in_last; wire main_writer_stat_fifo_fifo_out_payload_slot; wire [31:0] main_writer_stat_fifo_fifo_out_payload_length; wire main_writer_stat_fifo_fifo_out_first; wire main_writer_stat_fifo_fifo_out_last; reg [8:0] main_writer_memory0_adr = 9'd0; wire [31:0] main_writer_memory0_dat_r; reg main_writer_memory0_we = 1'd0; reg [31:0] main_writer_memory0_dat_w = 32'd0; reg [8:0] main_writer_memory1_adr = 9'd0; wire [31:0] main_writer_memory1_dat_r; reg main_writer_memory1_we = 1'd0; reg [31:0] main_writer_memory1_dat_w = 32'd0; reg main_reader_source_source_valid = 1'd0; wire main_reader_source_source_ready; reg main_reader_source_source_first = 1'd0; reg main_reader_source_source_last = 1'd0; reg [31:0] main_reader_source_source_payload_data = 32'd0; reg [3:0] main_reader_source_source_payload_last_be = 4'd0; reg [3:0] main_reader_source_source_payload_error = 4'd0; reg main_reader_start_start_re = 1'd0; wire main_reader_start_start_r; reg main_reader_start_start_we = 1'd0; reg main_reader_start_start_w = 1'd0; wire main_reader_ready_status; wire main_reader_ready_we; reg main_reader_ready_re = 1'd0; wire [1:0] main_reader_level_status; wire main_reader_level_we; reg main_reader_level_re = 1'd0; reg main_reader_slot_storage = 1'd0; reg main_reader_slot_re = 1'd0; reg [10:0] main_reader_length_storage = 11'd0; reg main_reader_length_re = 1'd0; wire main_reader_irq; wire main_reader_eventsourcepulse_status; reg main_reader_eventsourcepulse_pending = 1'd0; reg main_reader_eventsourcepulse_trigger = 1'd0; reg main_reader_eventsourcepulse_clear = 1'd0; wire main_reader_event00; wire main_reader_status_status; wire main_reader_status_we; reg main_reader_status_re = 1'd0; wire main_reader_event01; wire main_reader_pending_status; wire main_reader_pending_we; reg main_reader_pending_re = 1'd0; reg main_reader_pending_r = 1'd0; wire main_reader_event02; reg main_reader_enable_storage = 1'd0; reg main_reader_enable_re = 1'd0; reg main_reader_start = 1'd0; wire main_reader_cmd_fifo_sink_valid; wire main_reader_cmd_fifo_sink_ready; reg main_reader_cmd_fifo_sink_first = 1'd0; reg main_reader_cmd_fifo_sink_last = 1'd0; wire main_reader_cmd_fifo_sink_payload_slot; wire [10:0] main_reader_cmd_fifo_sink_payload_length; wire main_reader_cmd_fifo_source_valid; reg main_reader_cmd_fifo_source_ready = 1'd0; wire main_reader_cmd_fifo_source_first; wire main_reader_cmd_fifo_source_last; wire main_reader_cmd_fifo_source_payload_slot; wire [10:0] main_reader_cmd_fifo_source_payload_length; wire main_reader_cmd_fifo_syncfifo_we; wire main_reader_cmd_fifo_syncfifo_writable; wire main_reader_cmd_fifo_syncfifo_re; wire main_reader_cmd_fifo_syncfifo_readable; wire [13:0] main_reader_cmd_fifo_syncfifo_din; wire [13:0] main_reader_cmd_fifo_syncfifo_dout; reg [1:0] main_reader_cmd_fifo_level = 2'd0; reg main_reader_cmd_fifo_replace = 1'd0; reg main_reader_cmd_fifo_produce = 1'd0; reg main_reader_cmd_fifo_consume = 1'd0; reg main_reader_cmd_fifo_wrport_adr = 1'd0; wire [13:0] main_reader_cmd_fifo_wrport_dat_r; wire main_reader_cmd_fifo_wrport_we; wire [13:0] main_reader_cmd_fifo_wrport_dat_w; wire main_reader_cmd_fifo_do_read; wire main_reader_cmd_fifo_rdport_adr; wire [13:0] main_reader_cmd_fifo_rdport_dat_r; wire main_reader_cmd_fifo_fifo_in_payload_slot; wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length; wire main_reader_cmd_fifo_fifo_in_first; wire main_reader_cmd_fifo_fifo_in_last; wire main_reader_cmd_fifo_fifo_out_payload_slot; wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length; wire main_reader_cmd_fifo_fifo_out_first; wire main_reader_cmd_fifo_fifo_out_last; reg [10:0] main_reader_read_address = 11'd0; reg [10:0] main_reader_counter = 11'd0; wire [8:0] main_reader_memory0_adr; wire [31:0] main_reader_memory0_dat_r; wire [8:0] main_reader_memory1_adr; wire [31:0] main_reader_memory1_dat_r; wire main_ev_irq; wire [29:0] main_sram0_bus_adr0; wire [31:0] main_sram0_bus_dat_w0; wire [31:0] main_sram0_bus_dat_r0; wire [3:0] main_sram0_bus_sel0; wire main_sram0_bus_cyc0; wire main_sram0_bus_stb0; reg main_sram0_bus_ack0 = 1'd0; wire main_sram0_bus_we0; wire [2:0] main_sram0_bus_cti0; wire [1:0] main_sram0_bus_bte0; reg main_sram0_bus_err0 = 1'd0; wire [8:0] main_sram0_adr0; wire [31:0] main_sram0_dat_r0; wire [29:0] main_sram1_bus_adr0; wire [31:0] main_sram1_bus_dat_w0; wire [31:0] main_sram1_bus_dat_r0; wire [3:0] main_sram1_bus_sel0; wire main_sram1_bus_cyc0; wire main_sram1_bus_stb0; reg main_sram1_bus_ack0 = 1'd0; wire main_sram1_bus_we0; wire [2:0] main_sram1_bus_cti0; wire [1:0] main_sram1_bus_bte0; reg main_sram1_bus_err0 = 1'd0; wire [8:0] main_sram1_adr0; wire [31:0] main_sram1_dat_r0; wire [29:0] main_sram0_bus_adr1; wire [31:0] main_sram0_bus_dat_w1; wire [31:0] main_sram0_bus_dat_r1; wire [3:0] main_sram0_bus_sel1; wire main_sram0_bus_cyc1; wire main_sram0_bus_stb1; reg main_sram0_bus_ack1 = 1'd0; wire main_sram0_bus_we1; wire [2:0] main_sram0_bus_cti1; wire [1:0] main_sram0_bus_bte1; reg main_sram0_bus_err1 = 1'd0; wire [8:0] main_sram0_adr1; wire [31:0] main_sram0_dat_r1; reg [3:0] main_sram0_we = 4'd0; wire [31:0] main_sram0_dat_w; wire [29:0] main_sram1_bus_adr1; wire [31:0] main_sram1_bus_dat_w1; wire [31:0] main_sram1_bus_dat_r1; wire [3:0] main_sram1_bus_sel1; wire main_sram1_bus_cyc1; wire main_sram1_bus_stb1; reg main_sram1_bus_ack1 = 1'd0; wire main_sram1_bus_we1; wire [2:0] main_sram1_bus_cti1; wire [1:0] main_sram1_bus_bte1; reg main_sram1_bus_err1 = 1'd0; wire [8:0] main_sram1_adr1; wire [31:0] main_sram1_dat_r1; reg [3:0] main_sram1_we = 4'd0; wire [31:0] main_sram1_dat_w; reg [3:0] main_slave_sel = 4'd0; reg [3:0] main_slave_sel_r = 4'd0; wire [29:0] main_wb_bus_adr; wire [31:0] main_wb_bus_dat_w; wire [31:0] main_wb_bus_dat_r; wire [3:0] main_wb_bus_sel; wire main_wb_bus_cyc; wire main_wb_bus_stb; wire main_wb_bus_ack; wire main_wb_bus_we; wire [2:0] main_wb_bus_cti; wire [1:0] main_wb_bus_bte; wire main_wb_bus_err; wire builder_reset0; wire builder_reset1; wire builder_reset2; wire builder_reset3; wire builder_reset4; wire builder_reset5; wire builder_reset6; wire builder_reset7; wire builder_pll_fb; reg builder_liteethmacgap_state = 1'd0; reg builder_liteethmacgap_next_state = 1'd0; reg [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; reg main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0; reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0; reg [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; reg main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; reg builder_liteethmacpreamblechecker_state = 1'd0; reg builder_liteethmacpreamblechecker_next_state = 1'd0; reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0; reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0; reg [1:0] builder_liteethmaccrc32checker_state = 2'd0; reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0; reg builder_liteethmacpaddinginserter_state = 1'd0; reg builder_liteethmacpaddinginserter_next_state = 1'd0; reg [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; reg main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; reg builder_liteethmactxlastbe_state = 1'd0; reg builder_liteethmactxlastbe_next_state = 1'd0; reg [2:0] builder_liteethmacsramwriter_state = 3'd0; reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; reg [31:0] main_writer_counter_t_next_value = 32'd0; reg main_writer_counter_t_next_value_ce = 1'd0; reg [31:0] main_writer_errors_status_f_next_value = 32'd0; reg main_writer_errors_status_f_next_value_ce = 1'd0; reg [1:0] builder_liteethmacsramreader_state = 2'd0; reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; reg [10:0] main_reader_counter_next_value = 11'd0; reg main_reader_counter_next_value_ce = 1'd0; reg [13:0] builder_maccore_adr = 14'd0; reg builder_maccore_we = 1'd0; reg [31:0] builder_maccore_dat_w = 32'd0; wire [31:0] builder_maccore_dat_r; wire [29:0] builder_maccore_wishbone_adr; wire [31:0] builder_maccore_wishbone_dat_w; reg [31:0] builder_maccore_wishbone_dat_r = 32'd0; wire [3:0] builder_maccore_wishbone_sel; wire builder_maccore_wishbone_cyc; wire builder_maccore_wishbone_stb; reg builder_maccore_wishbone_ack = 1'd0; wire builder_maccore_wishbone_we; wire [2:0] builder_maccore_wishbone_cti; wire [1:0] builder_maccore_wishbone_bte; reg builder_maccore_wishbone_err = 1'd0; wire [29:0] builder_shared_adr; wire [31:0] builder_shared_dat_w; reg [31:0] builder_shared_dat_r = 32'd0; wire [3:0] builder_shared_sel; wire builder_shared_cyc; wire builder_shared_stb; reg builder_shared_ack = 1'd0; wire builder_shared_we; wire [2:0] builder_shared_cti; wire [1:0] builder_shared_bte; wire builder_shared_err; wire builder_request; wire builder_grant; reg [1:0] builder_slave_sel = 2'd0; reg [1:0] builder_slave_sel_r = 2'd0; reg builder_error = 1'd0; wire builder_wait; wire builder_done; reg [19:0] builder_count = 20'd1000000; wire [13:0] builder_interface0_bank_bus_adr; wire builder_interface0_bank_bus_we; wire [31:0] builder_interface0_bank_bus_dat_w; reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; reg builder_csrbank0_reset0_re = 1'd0; wire [1:0] builder_csrbank0_reset0_r; reg builder_csrbank0_reset0_we = 1'd0; wire [1:0] builder_csrbank0_reset0_w; reg builder_csrbank0_scratch0_re = 1'd0; wire [31:0] builder_csrbank0_scratch0_r; reg builder_csrbank0_scratch0_we = 1'd0; wire [31:0] builder_csrbank0_scratch0_w; reg builder_csrbank0_bus_errors_re = 1'd0; wire [31:0] builder_csrbank0_bus_errors_r; reg builder_csrbank0_bus_errors_we = 1'd0; wire [31:0] builder_csrbank0_bus_errors_w; wire builder_csrbank0_sel; wire [13:0] builder_interface1_bank_bus_adr; wire builder_interface1_bank_bus_we; wire [31:0] builder_interface1_bank_bus_dat_w; reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; reg builder_csrbank1_sram_writer_slot_re = 1'd0; wire builder_csrbank1_sram_writer_slot_r; reg builder_csrbank1_sram_writer_slot_we = 1'd0; wire builder_csrbank1_sram_writer_slot_w; reg builder_csrbank1_sram_writer_length_re = 1'd0; wire [31:0] builder_csrbank1_sram_writer_length_r; reg builder_csrbank1_sram_writer_length_we = 1'd0; wire [31:0] builder_csrbank1_sram_writer_length_w; reg builder_csrbank1_sram_writer_errors_re = 1'd0; wire [31:0] builder_csrbank1_sram_writer_errors_r; reg builder_csrbank1_sram_writer_errors_we = 1'd0; wire [31:0] builder_csrbank1_sram_writer_errors_w; reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; wire builder_csrbank1_sram_writer_ev_status_r; reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; wire builder_csrbank1_sram_writer_ev_status_w; reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; wire builder_csrbank1_sram_writer_ev_pending_r; reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; wire builder_csrbank1_sram_writer_ev_pending_w; reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; wire builder_csrbank1_sram_writer_ev_enable0_r; reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; wire builder_csrbank1_sram_writer_ev_enable0_w; reg builder_csrbank1_sram_reader_ready_re = 1'd0; wire builder_csrbank1_sram_reader_ready_r; reg builder_csrbank1_sram_reader_ready_we = 1'd0; wire builder_csrbank1_sram_reader_ready_w; reg builder_csrbank1_sram_reader_level_re = 1'd0; wire [1:0] builder_csrbank1_sram_reader_level_r; reg builder_csrbank1_sram_reader_level_we = 1'd0; wire [1:0] builder_csrbank1_sram_reader_level_w; reg builder_csrbank1_sram_reader_slot0_re = 1'd0; wire builder_csrbank1_sram_reader_slot0_r; reg builder_csrbank1_sram_reader_slot0_we = 1'd0; wire builder_csrbank1_sram_reader_slot0_w; reg builder_csrbank1_sram_reader_length0_re = 1'd0; wire [10:0] builder_csrbank1_sram_reader_length0_r; reg builder_csrbank1_sram_reader_length0_we = 1'd0; wire [10:0] builder_csrbank1_sram_reader_length0_w; reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; wire builder_csrbank1_sram_reader_ev_status_r; reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; wire builder_csrbank1_sram_reader_ev_status_w; reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; wire builder_csrbank1_sram_reader_ev_pending_r; reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; wire builder_csrbank1_sram_reader_ev_pending_w; reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; wire builder_csrbank1_sram_reader_ev_enable0_r; reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; wire builder_csrbank1_sram_reader_ev_enable0_w; reg builder_csrbank1_preamble_crc_re = 1'd0; wire builder_csrbank1_preamble_crc_r; reg builder_csrbank1_preamble_crc_we = 1'd0; wire builder_csrbank1_preamble_crc_w; reg builder_csrbank1_preamble_errors_re = 1'd0; wire [31:0] builder_csrbank1_preamble_errors_r; reg builder_csrbank1_preamble_errors_we = 1'd0; wire [31:0] builder_csrbank1_preamble_errors_w; reg builder_csrbank1_crc_errors_re = 1'd0; wire [31:0] builder_csrbank1_crc_errors_r; reg builder_csrbank1_crc_errors_we = 1'd0; wire [31:0] builder_csrbank1_crc_errors_w; wire builder_csrbank1_sel; wire [13:0] builder_interface2_bank_bus_adr; wire builder_interface2_bank_bus_we; wire [31:0] builder_interface2_bank_bus_dat_w; reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; reg builder_csrbank2_crg_reset0_re = 1'd0; wire builder_csrbank2_crg_reset0_r; reg builder_csrbank2_crg_reset0_we = 1'd0; wire builder_csrbank2_crg_reset0_w; reg builder_csrbank2_mdio_w0_re = 1'd0; wire [2:0] builder_csrbank2_mdio_w0_r; reg builder_csrbank2_mdio_w0_we = 1'd0; wire [2:0] builder_csrbank2_mdio_w0_w; reg builder_csrbank2_mdio_r_re = 1'd0; wire builder_csrbank2_mdio_r_r; reg builder_csrbank2_mdio_r_we = 1'd0; wire builder_csrbank2_mdio_r_w; wire builder_csrbank2_sel; wire [13:0] builder_csr_interconnect_adr; wire builder_csr_interconnect_we; wire [31:0] builder_csr_interconnect_dat_w; wire [31:0] builder_csr_interconnect_dat_r; reg builder_state = 1'd0; reg builder_next_state = 1'd0; reg [29:0] builder_array_muxed0 = 30'd0; reg [31:0] builder_array_muxed1 = 32'd0; reg [3:0] builder_array_muxed2 = 4'd0; reg builder_array_muxed3 = 1'd0; reg builder_array_muxed4 = 1'd0; reg builder_array_muxed5 = 1'd0; reg [2:0] builder_array_muxed6 = 3'd0; reg [1:0] builder_array_muxed7 = 2'd0; wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl0_expr; wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs0 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs1 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs0 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs1 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs0 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs1 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs0 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs1 = 6'd0; assign main_wb_bus_adr = wishbone_adr; assign main_wb_bus_dat_w = wishbone_dat_w; assign wishbone_dat_r = main_wb_bus_dat_r; assign main_wb_bus_sel = wishbone_sel; assign main_wb_bus_cyc = wishbone_cyc; assign main_wb_bus_stb = wishbone_stb; assign wishbone_ack = main_wb_bus_ack; assign main_wb_bus_we = wishbone_we; assign main_wb_bus_cti = wishbone_cti; assign main_wb_bus_bte = wishbone_bte; assign wishbone_err = main_wb_bus_err; assign interrupt = main_ev_irq; assign main_maccore_maccore_bus_error = builder_error; assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; assign sys_rst = main_maccore_int_rst; assign main_maccore_ethphy_reset1 = main_maccore_ethphy_reset_storage; assign rgmii_eth_rst_n = (~main_maccore_ethphy_reset1); assign main_maccore_ethphy_clkin = eth_rx_clk; assign eth_tx_clk = main_maccore_ethphy_clkout_buf0; assign eth_tx_delayed_clk = main_maccore_ethphy_clkout_buf1; assign main_maccore_ethphy_sink_ready = 1'd1; assign main_maccore_ethphy_liteethphyrgmiirx_last = ((~main_maccore_ethphy_liteethphyrgmiirx_rx_ctl) & main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d); assign main_maccore_ethphy_liteethphyrgmiirx_source_last = main_maccore_ethphy_liteethphyrgmiirx_last; assign rgmii_eth_mdc = main_maccore_ethphy__w_storage[0]; assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; assign main_tx_cdc_sink_sink_valid = main_source_valid; assign main_source_ready = main_tx_cdc_sink_sink_ready; assign main_tx_cdc_sink_sink_first = main_source_first; assign main_tx_cdc_sink_sink_last = main_source_last; assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data; assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be; assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error; assign main_sink_valid = main_rx_cdc_source_source_valid; assign main_rx_cdc_source_source_ready = main_sink_ready; assign main_sink_first = main_rx_cdc_source_source_first; assign main_sink_last = main_rx_cdc_source_source_last; assign main_sink_payload_data = main_rx_cdc_source_source_payload_data; assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be; assign main_sink_payload_error = main_rx_cdc_source_source_payload_error; assign main_ps_preamble_error_i = main_preamble_checker_error; assign main_ps_crc_error_i = main_liteethmaccrc32checker_error; always @(*) begin main_tx_gap_inserter_source_payload_last_be <= 1'd0; main_tx_gap_inserter_source_payload_error <= 1'd0; main_tx_gap_inserter_sink_ready <= 1'd0; main_tx_gap_inserter_source_valid <= 1'd0; builder_liteethmacgap_next_state <= 1'd0; main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; main_tx_gap_inserter_source_first <= 1'd0; main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; main_tx_gap_inserter_source_last <= 1'd0; main_tx_gap_inserter_source_payload_data <= 8'd0; builder_liteethmacgap_next_state <= builder_liteethmacgap_state; case (builder_liteethmacgap_state) 1'd1: begin main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1); main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; if ((main_tx_gap_inserter_counter == 4'd11)) begin builder_liteethmacgap_next_state <= 1'd0; end end default: begin main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid; main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready; main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first; main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last; main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data; main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be; main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error; if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin builder_liteethmacgap_next_state <= 1'd1; end end endcase end assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be; always @(*) begin main_preamble_inserter_sink_ready <= 1'd0; builder_liteethmacpreambleinserter_next_state <= 2'd0; main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; main_preamble_inserter_source_valid <= 1'd0; main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; main_preamble_inserter_source_first <= 1'd0; main_preamble_inserter_source_last <= 1'd0; main_preamble_inserter_source_payload_data <= 8'd0; main_preamble_inserter_source_payload_error <= 1'd0; main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data; builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state; case (builder_liteethmacpreambleinserter_state) 1'd1: begin main_preamble_inserter_source_valid <= 1'd1; case (main_preamble_inserter_count) 1'd0: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0]; end 1'd1: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8]; end 2'd2: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16]; end 2'd3: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24]; end 3'd4: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32]; end 3'd5: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40]; end 3'd6: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48]; end default: begin main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56]; end endcase if (main_preamble_inserter_source_ready) begin if ((main_preamble_inserter_count == 3'd7)) begin builder_liteethmacpreambleinserter_next_state <= 2'd2; end else begin main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1); main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; end end end 2'd2: begin main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid; main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready; main_preamble_inserter_source_first <= main_preamble_inserter_sink_first; main_preamble_inserter_source_last <= main_preamble_inserter_sink_last; main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error; if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin builder_liteethmacpreambleinserter_next_state <= 1'd0; end end default: begin main_preamble_inserter_sink_ready <= 1'd1; main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; if (main_preamble_inserter_sink_valid) begin main_preamble_inserter_sink_ready <= 1'd0; builder_liteethmacpreambleinserter_next_state <= 1'd1; end end endcase end assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data; assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be; always @(*) begin main_preamble_checker_source_payload_error <= 1'd0; main_preamble_checker_error <= 1'd0; main_preamble_checker_source_valid <= 1'd0; main_preamble_checker_sink_ready <= 1'd0; builder_liteethmacpreamblechecker_next_state <= 1'd0; main_preamble_checker_source_first <= 1'd0; main_preamble_checker_source_last <= 1'd0; builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state; case (builder_liteethmacpreamblechecker_state) 1'd1: begin main_preamble_checker_source_valid <= main_preamble_checker_sink_valid; main_preamble_checker_sink_ready <= main_preamble_checker_source_ready; main_preamble_checker_source_first <= main_preamble_checker_sink_first; main_preamble_checker_source_last <= main_preamble_checker_sink_last; main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error; if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin builder_liteethmacpreamblechecker_next_state <= 1'd0; end end default: begin main_preamble_checker_sink_ready <= 1'd1; if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin builder_liteethmacpreamblechecker_next_state <= 1'd1; end if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin main_preamble_checker_error <= 1'd1; end end endcase end assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0); assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid; assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready; assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first; assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last; assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data; assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be; assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error; assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0; assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg; assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]}); assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827); always @(*) begin main_liteethmaccrc32inserter_next <= 32'd0; main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); end always @(*) begin main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0; main_liteethmaccrc32inserter_sink_ready <= 1'd0; main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0; main_liteethmaccrc32inserter_ce <= 1'd0; main_liteethmaccrc32inserter_reset <= 1'd0; main_liteethmaccrc32inserter_source_valid <= 1'd0; main_liteethmaccrc32inserter_source_first <= 1'd0; main_liteethmaccrc32inserter_source_last <= 1'd0; main_liteethmaccrc32inserter_source_payload_data <= 8'd0; main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; main_liteethmaccrc32inserter_source_payload_error <= 1'd0; builder_liteethmaccrc32inserter_next_state <= 2'd0; main_liteethmaccrc32inserter_data0 <= 8'd0; builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state; case (builder_liteethmaccrc32inserter_state) 1'd1: begin main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready); main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data; main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid; main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready; main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first; main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last; main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data; main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be; main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error; main_liteethmaccrc32inserter_source_last <= 1'd0; if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin builder_liteethmaccrc32inserter_next_state <= 2'd2; end end 2'd2: begin main_liteethmaccrc32inserter_source_valid <= 1'd1; case (main_liteethmaccrc32inserter_cnt) 1'd0: begin main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24]; end 1'd1: begin main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16]; end 2'd2: begin main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8]; end default: begin main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0]; end endcase if (main_liteethmaccrc32inserter_cnt_done) begin main_liteethmaccrc32inserter_source_last <= 1'd1; if (main_liteethmaccrc32inserter_source_ready) begin builder_liteethmaccrc32inserter_next_state <= 1'd0; end end main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1; end default: begin main_liteethmaccrc32inserter_reset <= 1'd1; main_liteethmaccrc32inserter_sink_ready <= 1'd1; if (main_liteethmaccrc32inserter_sink_valid) begin main_liteethmaccrc32inserter_sink_ready <= 1'd0; builder_liteethmaccrc32inserter_next_state <= 1'd1; end main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1; end endcase end assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready); assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; end always @(*) begin main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; end assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last; assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out; assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be; always @(*) begin main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error); end assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error); assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid; assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready; assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first; assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last; assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data; assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be; assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error; assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0; assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg; assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]}); assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827); always @(*) begin main_liteethmaccrc32checker_crc_next <= 32'd0; main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); end assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; if (main_liteethmaccrc32checker_syncfifo_replace) begin main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); end else begin main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; end end assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin builder_liteethmaccrc32checker_next_state <= 2'd0; main_liteethmaccrc32checker_crc_ce <= 1'd0; main_liteethmaccrc32checker_crc_reset <= 1'd0; main_liteethmaccrc32checker_fifo_reset <= 1'd0; builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state; case (builder_liteethmaccrc32checker_state) 1'd1: begin if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin main_liteethmaccrc32checker_crc_ce <= 1'd1; builder_liteethmaccrc32checker_next_state <= 2'd2; end end 2'd2: begin if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin main_liteethmaccrc32checker_crc_ce <= 1'd1; if (main_liteethmaccrc32checker_sink_sink_last) begin builder_liteethmaccrc32checker_next_state <= 1'd0; end end end default: begin main_liteethmaccrc32checker_crc_reset <= 1'd1; main_liteethmaccrc32checker_fifo_reset <= 1'd1; builder_liteethmaccrc32checker_next_state <= 1'd1; end endcase end assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready); assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r); assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r); assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59); always @(*) begin builder_liteethmacpaddinginserter_next_state <= 1'd0; main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; main_padding_inserter_sink_ready <= 1'd0; main_padding_inserter_source_valid <= 1'd0; main_padding_inserter_source_first <= 1'd0; main_padding_inserter_source_last <= 1'd0; main_padding_inserter_source_payload_data <= 8'd0; main_padding_inserter_source_payload_last_be <= 1'd0; main_padding_inserter_source_payload_error <= 1'd0; builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state; case (builder_liteethmacpaddinginserter_state) 1'd1: begin main_padding_inserter_source_valid <= 1'd1; main_padding_inserter_source_last <= main_padding_inserter_counter_done; main_padding_inserter_source_payload_data <= 1'd0; if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; if (main_padding_inserter_counter_done) begin main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; builder_liteethmacpaddinginserter_next_state <= 1'd0; end end end default: begin main_padding_inserter_source_valid <= main_padding_inserter_sink_valid; main_padding_inserter_sink_ready <= main_padding_inserter_source_ready; main_padding_inserter_source_first <= main_padding_inserter_sink_first; main_padding_inserter_source_last <= main_padding_inserter_sink_last; main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data; main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be; main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error; if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; if (main_padding_inserter_sink_last) begin if ((~main_padding_inserter_counter_done)) begin main_padding_inserter_source_last <= 1'd0; builder_liteethmacpaddinginserter_next_state <= 1'd1; end else begin main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; end end end end endcase end assign main_padding_checker_source_valid = main_padding_checker_sink_valid; assign main_padding_checker_sink_ready = main_padding_checker_source_ready; assign main_padding_checker_source_first = main_padding_checker_sink_first; assign main_padding_checker_source_last = main_padding_checker_sink_last; assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data; assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be; assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error; always @(*) begin main_tx_last_be_source_last <= 1'd0; main_tx_last_be_source_payload_data <= 8'd0; main_tx_last_be_source_payload_error <= 1'd0; builder_liteethmactxlastbe_next_state <= 1'd0; main_tx_last_be_source_first <= 1'd0; main_tx_last_be_source_valid <= 1'd0; main_tx_last_be_sink_ready <= 1'd0; builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state; case (builder_liteethmactxlastbe_state) 1'd1: begin main_tx_last_be_sink_ready <= 1'd1; if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin builder_liteethmactxlastbe_next_state <= 1'd0; end end default: begin main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; main_tx_last_be_source_first <= main_tx_last_be_sink_first; main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be; if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin builder_liteethmactxlastbe_next_state <= 1'd1; end end end endcase end assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; assign main_rx_last_be_source_first = main_rx_last_be_sink_first; assign main_rx_last_be_source_last = main_rx_last_be_sink_last; assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; always @(*) begin main_rx_last_be_source_payload_last_be <= 1'd0; main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; end assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; always @(*) begin main_tx_converter_converter_sink_payload_data <= 40'd0; main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; end assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; assign main_tx_converter_source_first = main_tx_converter_source_source_first; assign main_tx_converter_source_last = main_tx_converter_source_source_last; assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); always @(*) begin main_tx_converter_converter_source_payload_data <= 10'd0; case (main_tx_converter_converter_mux) 1'd0: begin main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; end 1'd1: begin main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; end 2'd2: begin main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; end default: begin main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; end endcase end assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; assign main_rx_converter_source_first = main_rx_converter_source_source_first; assign main_rx_converter_source_last = main_rx_converter_source_source_last; assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; always @(*) begin main_rx_converter_source_payload_data <= 32'd0; main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; end always @(*) begin main_rx_converter_source_payload_last_be <= 4'd0; main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; end always @(*) begin main_rx_converter_source_payload_error <= 4'd0; main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; end assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; always @(*) begin main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; if (main_tx_cdc_cdc_graycounter0_ce) begin main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; end end assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; if (main_tx_cdc_cdc_graycounter1_ce) begin main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; end end assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; always @(*) begin main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; if (main_rx_cdc_cdc_graycounter0_ce) begin main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; end end assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; if (main_rx_cdc_cdc_graycounter1_ce) begin main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; end end assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; assign main_tx_last_be_sink_first = main_tx_converter_source_first; assign main_tx_last_be_sink_last = main_tx_converter_source_last; assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid; assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready; assign main_padding_inserter_sink_first = main_tx_last_be_source_first; assign main_padding_inserter_sink_last = main_tx_last_be_source_last; assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data; assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be; assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error; assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid; assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready; assign main_crc32_inserter_sink_first = main_padding_inserter_source_first; assign main_crc32_inserter_sink_last = main_padding_inserter_source_last; assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data; assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be; assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error; assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid; assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready; assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first; assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last; assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data; assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be; assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error; assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid; assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready; assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first; assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last; assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data; assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be; assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error; assign main_maccore_ethphy_sink_valid = main_tx_gap_inserter_source_valid; assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_sink_ready; assign main_maccore_ethphy_sink_first = main_tx_gap_inserter_source_first; assign main_maccore_ethphy_sink_last = main_tx_gap_inserter_source_last; assign main_maccore_ethphy_sink_payload_data = main_tx_gap_inserter_source_payload_data; assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be; assign main_maccore_ethphy_sink_payload_error = main_tx_gap_inserter_source_payload_error; assign main_preamble_checker_sink_valid = main_maccore_ethphy_liteethphyrgmiirx_source_valid; assign main_maccore_ethphy_liteethphyrgmiirx_source_ready = main_preamble_checker_sink_ready; assign main_preamble_checker_sink_first = main_maccore_ethphy_liteethphyrgmiirx_source_first; assign main_preamble_checker_sink_last = main_maccore_ethphy_liteethphyrgmiirx_source_last; assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_liteethphyrgmiirx_source_payload_data; assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be; assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_liteethphyrgmiirx_source_payload_error; assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid; assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready; assign main_crc32_checker_sink_first = main_preamble_checker_source_first; assign main_crc32_checker_sink_last = main_preamble_checker_source_last; assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data; assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be; assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error; assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid; assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready; assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first; assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last; assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; assign main_rx_last_be_sink_valid = main_padding_checker_source_valid; assign main_padding_checker_source_ready = main_rx_last_be_sink_ready; assign main_rx_last_be_sink_first = main_padding_checker_source_first; assign main_rx_last_be_sink_last = main_padding_checker_source_last; assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data; assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be; assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error; assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; assign main_rx_converter_sink_first = main_rx_last_be_source_first; assign main_rx_converter_sink_last = main_rx_last_be_source_last; assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; assign main_writer_sink_sink_valid = main_sink_valid; assign main_sink_ready = main_writer_sink_sink_ready; assign main_writer_sink_sink_first = main_sink_first; assign main_writer_sink_sink_last = main_sink_last; assign main_writer_sink_sink_payload_data = main_sink_payload_data; assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be; assign main_writer_sink_sink_payload_error = main_sink_payload_error; assign main_source_valid = main_reader_source_source_valid; assign main_reader_source_source_ready = main_source_ready; assign main_source_first = main_reader_source_source_first; assign main_source_last = main_reader_source_source_last; assign main_source_payload_data = main_reader_source_source_payload_data; assign main_source_payload_last_be = main_reader_source_source_payload_last_be; assign main_source_payload_error = main_reader_source_source_payload_error; always @(*) begin main_writer_inc <= 3'd0; case (main_writer_sink_sink_payload_last_be) 1'd1: begin main_writer_inc <= 1'd1; end 2'd2: begin main_writer_inc <= 2'd2; end 3'd4: begin main_writer_inc <= 2'd3; end default: begin main_writer_inc <= 3'd4; end endcase end assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot; assign main_writer_stat_fifo_sink_payload_length = main_writer_counter; assign main_writer_stat_fifo_source_ready = main_writer_available_clear; assign main_writer_available_trigger = main_writer_stat_fifo_source_valid; assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot; assign main_writer_length_status = main_writer_stat_fifo_source_payload_length; always @(*) begin main_writer_memory1_adr <= 9'd0; main_writer_memory1_we <= 1'd0; main_writer_memory0_adr <= 9'd0; main_writer_memory1_dat_w <= 32'd0; main_writer_memory0_we <= 1'd0; main_writer_memory0_dat_w <= 32'd0; case (main_writer_slot) 1'd0: begin main_writer_memory0_adr <= main_writer_counter[31:2]; main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data; if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin main_writer_memory0_we <= 4'd15; end end 1'd1: begin main_writer_memory1_adr <= main_writer_counter[31:2]; main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data; if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin main_writer_memory1_we <= 4'd15; end end endcase end assign main_writer_available0 = main_writer_available_status; assign main_writer_available1 = main_writer_available_pending; always @(*) begin main_writer_available_clear <= 1'd0; if ((main_writer_pending_re & main_writer_pending_r)) begin main_writer_available_clear <= 1'd1; end end assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage); assign main_writer_available_status = main_writer_available_trigger; assign main_writer_available_pending = main_writer_available_trigger; assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot}; assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout; assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable; assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid; assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first; assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last; assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot; assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length; assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable; assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first; assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last; assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot; assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length; assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready; always @(*) begin main_writer_stat_fifo_wrport_adr <= 1'd0; if (main_writer_stat_fifo_replace) begin main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1); end else begin main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce; end end assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din; assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace)); assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re); assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume; assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r; assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2); assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0); always @(*) begin builder_liteethmacsramwriter_next_state <= 3'd0; main_writer_slot_ce <= 1'd0; main_writer_counter_t_next_value <= 32'd0; main_writer_counter_t_next_value_ce <= 1'd0; main_writer_start <= 1'd0; main_writer_ongoing <= 1'd0; main_writer_errors_status_f_next_value <= 32'd0; main_writer_stat_fifo_sink_valid <= 1'd0; main_writer_errors_status_f_next_value_ce <= 1'd0; builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; case (builder_liteethmacsramwriter_state) 1'd1: begin if (main_writer_sink_sink_valid) begin if ((main_writer_counter == 11'd1530)) begin builder_liteethmacsramwriter_next_state <= 2'd3; end else begin main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); main_writer_counter_t_next_value_ce <= 1'd1; main_writer_ongoing <= 1'd1; end if (main_writer_sink_sink_last) begin if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin builder_liteethmacsramwriter_next_state <= 2'd2; end else begin builder_liteethmacsramwriter_next_state <= 3'd4; end end end end 2'd2: begin main_writer_counter_t_next_value <= 1'd0; main_writer_counter_t_next_value_ce <= 1'd1; builder_liteethmacsramwriter_next_state <= 1'd0; end 2'd3: begin if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin builder_liteethmacsramwriter_next_state <= 3'd4; end end 3'd4: begin main_writer_counter_t_next_value <= 1'd0; main_writer_counter_t_next_value_ce <= 1'd1; main_writer_slot_ce <= 1'd1; main_writer_stat_fifo_sink_valid <= 1'd1; builder_liteethmacsramwriter_next_state <= 1'd0; end default: begin if (main_writer_sink_sink_valid) begin if (main_writer_stat_fifo_sink_ready) begin main_writer_start <= 1'd1; main_writer_ongoing <= 1'd1; main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); main_writer_counter_t_next_value_ce <= 1'd1; builder_liteethmacsramwriter_next_state <= 1'd1; end else begin main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1); main_writer_errors_status_f_next_value_ce <= 1'd1; builder_liteethmacsramwriter_next_state <= 2'd3; end end end endcase end assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re; assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage; assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage; assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready; assign main_reader_level_status = main_reader_cmd_fifo_level; always @(*) begin main_reader_source_source_payload_last_be <= 4'd0; if (main_reader_source_source_last) begin case (main_reader_cmd_fifo_source_payload_length[1:0]) 1'd0: begin main_reader_source_source_payload_last_be <= 4'd8; end 1'd1: begin main_reader_source_source_payload_last_be <= 1'd1; end 2'd2: begin main_reader_source_source_payload_last_be <= 2'd2; end 2'd3: begin main_reader_source_source_payload_last_be <= 3'd4; end endcase end end assign main_reader_memory0_adr = main_reader_read_address[10:2]; assign main_reader_memory1_adr = main_reader_read_address[10:2]; always @(*) begin main_reader_source_source_payload_data <= 32'd0; case (main_reader_cmd_fifo_source_payload_slot) 1'd0: begin main_reader_source_source_payload_data <= main_reader_memory0_dat_r; end 1'd1: begin main_reader_source_source_payload_data <= main_reader_memory1_dat_r; end endcase end assign main_reader_event00 = main_reader_eventsourcepulse_status; assign main_reader_event01 = main_reader_eventsourcepulse_pending; always @(*) begin main_reader_eventsourcepulse_clear <= 1'd0; if ((main_reader_pending_re & main_reader_pending_r)) begin main_reader_eventsourcepulse_clear <= 1'd1; end end assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage); assign main_reader_eventsourcepulse_status = 1'd0; assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot}; assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout; assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable; assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid; assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first; assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last; assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot; assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length; assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable; assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first; assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last; assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot; assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length; assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready; always @(*) begin main_reader_cmd_fifo_wrport_adr <= 1'd0; if (main_reader_cmd_fifo_replace) begin main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1); end else begin main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce; end end assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din; assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace)); assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re); assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume; assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r; assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2); assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0); always @(*) begin main_reader_source_source_valid <= 1'd0; main_reader_start <= 1'd0; main_reader_source_source_last <= 1'd0; builder_liteethmacsramreader_next_state <= 2'd0; main_reader_counter_next_value <= 11'd0; main_reader_read_address <= 11'd0; main_reader_counter_next_value_ce <= 1'd0; main_reader_cmd_fifo_source_ready <= 1'd0; main_reader_eventsourcepulse_trigger <= 1'd0; builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; case (builder_liteethmacsramreader_state) 1'd1: begin main_reader_source_source_valid <= 1'd1; main_reader_source_source_last <= (main_reader_counter >= (main_reader_cmd_fifo_source_payload_length - 3'd4)); main_reader_read_address <= main_reader_counter; if (main_reader_source_source_ready) begin main_reader_read_address <= (main_reader_counter + 3'd4); main_reader_counter_next_value <= (main_reader_counter + 3'd4); main_reader_counter_next_value_ce <= 1'd1; if (main_reader_source_source_last) begin builder_liteethmacsramreader_next_state <= 2'd2; end end end 2'd2: begin main_reader_eventsourcepulse_trigger <= 1'd1; main_reader_cmd_fifo_source_ready <= 1'd1; builder_liteethmacsramreader_next_state <= 1'd0; end default: begin main_reader_counter_next_value <= 1'd0; main_reader_counter_next_value_ce <= 1'd1; if (main_reader_cmd_fifo_source_valid) begin main_reader_start <= 1'd1; builder_liteethmacsramreader_next_state <= 1'd1; end end endcase end assign main_ev_irq = (main_writer_irq | main_reader_irq); assign main_sram0_adr0 = main_sram0_bus_adr0[8:0]; assign main_sram0_bus_dat_r0 = main_sram0_dat_r0; assign main_sram1_adr0 = main_sram1_bus_adr0[8:0]; assign main_sram1_bus_dat_r0 = main_sram1_dat_r0; always @(*) begin main_sram0_we <= 4'd0; main_sram0_we[0] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[0]); main_sram0_we[1] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[1]); main_sram0_we[2] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[2]); main_sram0_we[3] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[3]); end assign main_sram0_adr1 = main_sram0_bus_adr1[8:0]; assign main_sram0_bus_dat_r1 = main_sram0_dat_r1; assign main_sram0_dat_w = main_sram0_bus_dat_w1; always @(*) begin main_sram1_we <= 4'd0; main_sram1_we[0] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[0]); main_sram1_we[1] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[1]); main_sram1_we[2] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[2]); main_sram1_we[3] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[3]); end assign main_sram1_adr1 = main_sram1_bus_adr1[8:0]; assign main_sram1_bus_dat_r1 = main_sram1_dat_r1; assign main_sram1_dat_w = main_sram1_bus_dat_w1; always @(*) begin main_slave_sel <= 4'd0; main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); end assign main_sram0_bus_adr0 = main_bus_adr; assign main_sram0_bus_dat_w0 = main_bus_dat_w; assign main_sram0_bus_sel0 = main_bus_sel; assign main_sram0_bus_stb0 = main_bus_stb; assign main_sram0_bus_we0 = main_bus_we; assign main_sram0_bus_cti0 = main_bus_cti; assign main_sram0_bus_bte0 = main_bus_bte; assign main_sram1_bus_adr0 = main_bus_adr; assign main_sram1_bus_dat_w0 = main_bus_dat_w; assign main_sram1_bus_sel0 = main_bus_sel; assign main_sram1_bus_stb0 = main_bus_stb; assign main_sram1_bus_we0 = main_bus_we; assign main_sram1_bus_cti0 = main_bus_cti; assign main_sram1_bus_bte0 = main_bus_bte; assign main_sram0_bus_adr1 = main_bus_adr; assign main_sram0_bus_dat_w1 = main_bus_dat_w; assign main_sram0_bus_sel1 = main_bus_sel; assign main_sram0_bus_stb1 = main_bus_stb; assign main_sram0_bus_we1 = main_bus_we; assign main_sram0_bus_cti1 = main_bus_cti; assign main_sram0_bus_bte1 = main_bus_bte; assign main_sram1_bus_adr1 = main_bus_adr; assign main_sram1_bus_dat_w1 = main_bus_dat_w; assign main_sram1_bus_sel1 = main_bus_sel; assign main_sram1_bus_stb1 = main_bus_stb; assign main_sram1_bus_we1 = main_bus_we; assign main_sram1_bus_cti1 = main_bus_cti; assign main_sram1_bus_bte1 = main_bus_bte; assign main_sram0_bus_cyc0 = (main_bus_cyc & main_slave_sel[0]); assign main_sram1_bus_cyc0 = (main_bus_cyc & main_slave_sel[1]); assign main_sram0_bus_cyc1 = (main_bus_cyc & main_slave_sel[2]); assign main_sram1_bus_cyc1 = (main_bus_cyc & main_slave_sel[3]); assign main_bus_ack = (((main_sram0_bus_ack0 | main_sram1_bus_ack0) | main_sram0_bus_ack1) | main_sram1_bus_ack1); assign main_bus_err = (((main_sram0_bus_err0 | main_sram1_bus_err0) | main_sram0_bus_err1) | main_sram1_bus_err1); assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) | ({32{main_slave_sel_r[1]}} & main_sram1_bus_dat_r0)) | ({32{main_slave_sel_r[2]}} & main_sram0_bus_dat_r1)) | ({32{main_slave_sel_r[3]}} & main_sram1_bus_dat_r1)); always @(*) begin builder_maccore_adr <= 14'd0; builder_maccore_we <= 1'd0; builder_maccore_dat_w <= 32'd0; builder_maccore_wishbone_ack <= 1'd0; builder_next_state <= 1'd0; builder_maccore_wishbone_dat_r <= 32'd0; builder_next_state <= builder_state; case (builder_state) 1'd1: begin builder_maccore_wishbone_ack <= 1'd1; builder_maccore_wishbone_dat_r <= builder_maccore_dat_r; builder_next_state <= 1'd0; end default: begin builder_maccore_dat_w <= builder_maccore_wishbone_dat_w; if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin builder_maccore_adr <= builder_maccore_wishbone_adr; builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0)); builder_next_state <= 1'd1; end end endcase end assign builder_shared_adr = builder_array_muxed0; assign builder_shared_dat_w = builder_array_muxed1; assign builder_shared_sel = builder_array_muxed2; assign builder_shared_cyc = builder_array_muxed3; assign builder_shared_stb = builder_array_muxed4; assign builder_shared_we = builder_array_muxed5; assign builder_shared_cti = builder_array_muxed6; assign builder_shared_bte = builder_array_muxed7; assign main_wb_bus_dat_r = builder_shared_dat_r; assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); assign builder_request = {main_wb_bus_cyc}; assign builder_grant = 1'd0; always @(*) begin builder_slave_sel <= 2'd0; builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); end assign main_bus_adr = builder_shared_adr; assign main_bus_dat_w = builder_shared_dat_w; assign main_bus_sel = builder_shared_sel; assign main_bus_stb = builder_shared_stb; assign main_bus_we = builder_shared_we; assign main_bus_cti = builder_shared_cti; assign main_bus_bte = builder_shared_bte; assign builder_maccore_wishbone_adr = builder_shared_adr; assign builder_maccore_wishbone_dat_w = builder_shared_dat_w; assign builder_maccore_wishbone_sel = builder_shared_sel; assign builder_maccore_wishbone_stb = builder_shared_stb; assign builder_maccore_wishbone_we = builder_shared_we; assign builder_maccore_wishbone_cti = builder_shared_cti; assign builder_maccore_wishbone_bte = builder_shared_bte; assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]); assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err); assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); always @(*) begin builder_shared_ack <= 1'd0; builder_error <= 1'd0; builder_shared_dat_r <= 32'd0; builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack); builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r)); if (builder_done) begin builder_shared_dat_r <= 32'd4294967295; builder_shared_ack <= 1'd1; builder_error <= 1'd1; end end assign builder_done = (builder_count == 1'd0); assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; always @(*) begin builder_csrbank0_reset0_we <= 1'd0; builder_csrbank0_reset0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); end end assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank0_scratch0_re <= 1'd0; builder_csrbank0_scratch0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); end end assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank0_bus_errors_re <= 1'd0; builder_csrbank0_bus_errors_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); end end always @(*) begin main_maccore_maccore_soc_rst <= 1'd0; if (main_maccore_maccore_reset_re) begin main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; end end assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_writer_slot_re <= 1'd0; builder_csrbank1_sram_writer_slot_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank1_sram_writer_length_re <= 1'd0; builder_csrbank1_sram_writer_length_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank1_sram_writer_errors_we <= 1'd0; builder_csrbank1_sram_writer_errors_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_writer_ev_status_we <= 1'd0; builder_csrbank1_sram_writer_ev_status_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); end end assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin main_reader_start_start_we <= 1'd0; main_reader_start_start_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin main_reader_start_start_re <= builder_interface1_bank_bus_we; main_reader_start_start_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_reader_ready_we <= 1'd0; builder_csrbank1_sram_reader_ready_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin builder_csrbank1_sram_reader_level_re <= 1'd0; builder_csrbank1_sram_reader_level_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_reader_slot0_re <= 1'd0; builder_csrbank1_sram_reader_slot0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin builder_csrbank1_sram_reader_length0_we <= 1'd0; builder_csrbank1_sram_reader_length0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_reader_ev_status_re <= 1'd0; builder_csrbank1_sram_reader_ev_status_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_preamble_crc_re <= 1'd0; builder_csrbank1_preamble_crc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank1_preamble_errors_re <= 1'd0; builder_csrbank1_preamble_errors_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we; builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank1_crc_errors_we <= 1'd0; builder_csrbank1_crc_errors_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin builder_csrbank1_crc_errors_re <= builder_interface1_bank_bus_we; builder_csrbank1_crc_errors_we <= (~builder_interface1_bank_bus_we); end end assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status; assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we; assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0]; assign main_writer_length_we = builder_csrbank1_sram_writer_length_we; assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0]; assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we; assign main_writer_status_status = main_writer_available0; assign builder_csrbank1_sram_writer_ev_status_w = main_writer_status_status; assign main_writer_status_we = builder_csrbank1_sram_writer_ev_status_we; assign main_writer_pending_status = main_writer_available1; assign builder_csrbank1_sram_writer_ev_pending_w = main_writer_pending_status; assign main_writer_pending_we = builder_csrbank1_sram_writer_ev_pending_we; assign main_writer_available2 = main_writer_enable_storage; assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_enable_storage; assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status; assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we; assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0]; assign main_reader_level_we = builder_csrbank1_sram_reader_level_we; assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage; assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0]; assign main_reader_status_status = main_reader_event00; assign builder_csrbank1_sram_reader_ev_status_w = main_reader_status_status; assign main_reader_status_we = builder_csrbank1_sram_reader_ev_status_we; assign main_reader_pending_status = main_reader_event01; assign builder_csrbank1_sram_reader_ev_pending_w = main_reader_pending_status; assign main_reader_pending_we = builder_csrbank1_sram_reader_ev_pending_we; assign main_reader_event02 = main_reader_enable_storage; assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_enable_storage; assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status; assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we; assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0]; assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we; assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0]; assign main_crc_errors_we = builder_csrbank1_crc_errors_we; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin builder_csrbank2_crg_reset0_we <= 1'd0; builder_csrbank2_crg_reset0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); end end assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_mdio_w0_re <= 1'd0; builder_csrbank2_mdio_w0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); end end assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin builder_csrbank2_mdio_r_re <= 1'd0; builder_csrbank2_mdio_r_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); end end assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; assign builder_csr_interconnect_adr = builder_maccore_adr; assign builder_csr_interconnect_we = builder_maccore_we; assign builder_csr_interconnect_dat_w = builder_maccore_dat_w; assign builder_maccore_dat_r = builder_csr_interconnect_dat_r; assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); always @(*) begin builder_array_muxed0 <= 30'd0; case (builder_grant) default: begin builder_array_muxed0 <= main_wb_bus_adr; end endcase end always @(*) begin builder_array_muxed1 <= 32'd0; case (builder_grant) default: begin builder_array_muxed1 <= main_wb_bus_dat_w; end endcase end always @(*) begin builder_array_muxed2 <= 4'd0; case (builder_grant) default: begin builder_array_muxed2 <= main_wb_bus_sel; end endcase end always @(*) begin builder_array_muxed3 <= 1'd0; case (builder_grant) default: begin builder_array_muxed3 <= main_wb_bus_cyc; end endcase end always @(*) begin builder_array_muxed4 <= 1'd0; case (builder_grant) default: begin builder_array_muxed4 <= main_wb_bus_stb; end endcase end always @(*) begin builder_array_muxed5 <= 1'd0; case (builder_grant) default: begin builder_array_muxed5 <= main_wb_bus_we; end endcase end always @(*) begin builder_array_muxed6 <= 3'd0; case (builder_grant) default: begin builder_array_muxed6 <= main_wb_bus_cti; end endcase end always @(*) begin builder_array_muxed7 <= 2'd0; case (builder_grant) default: begin builder_array_muxed7 <= main_wb_bus_bte; end endcase end assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_maccore_ethphy_locked); always @(*) begin main_maccore_ethphy__r_status <= 1'd0; main_maccore_ethphy__r_status <= main_maccore_ethphy_r; main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl0_regs1; end assign main_ps_preamble_error_toggle_o = builder_xilinxmultiregimpl1_regs1; assign main_ps_crc_error_toggle_o = builder_xilinxmultiregimpl2_regs1; assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl3_regs1; assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl4_regs1; assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl5_regs1; assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl6_regs1; always @(posedge eth_rx_clk) begin main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; main_maccore_ethphy_liteethphyrgmiirx_source_valid <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= main_maccore_ethphy_liteethphyrgmiirx_rx_data; builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state; if (main_liteethmaccrc32checker_crc_ce) begin main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_next; end if (main_liteethmaccrc32checker_crc_reset) begin main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; end if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; end else begin main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); end end if (main_liteethmaccrc32checker_syncfifo_do_read) begin if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; end else begin main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); end end if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); end end else begin if (main_liteethmaccrc32checker_syncfifo_do_read) begin main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); end end if (main_liteethmaccrc32checker_fifo_reset) begin main_liteethmaccrc32checker_syncfifo_level <= 3'd0; main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; end builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state; if (((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready)) begin main_crc32_checker_source_valid <= main_crc32_checker_sink_valid; main_crc32_checker_source_first <= main_crc32_checker_sink_first; main_crc32_checker_source_last <= main_crc32_checker_sink_last; main_crc32_checker_source_payload_data <= main_crc32_checker_sink_payload_data; main_crc32_checker_source_payload_last_be <= main_crc32_checker_sink_payload_last_be; main_crc32_checker_source_payload_error <= main_crc32_checker_sink_payload_error; end if (main_ps_preamble_error_i) begin main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i); end if (main_ps_crc_error_i) begin main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i); end if (main_rx_converter_converter_source_ready) begin main_rx_converter_converter_strobe_all <= 1'd0; end if (main_rx_converter_converter_load_part) begin if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin main_rx_converter_converter_demux <= 1'd0; main_rx_converter_converter_strobe_all <= 1'd1; end else begin main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); end end if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; end else begin main_rx_converter_converter_source_first <= 1'd0; main_rx_converter_converter_source_last <= 1'd0; end end else begin if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); end end if (main_rx_converter_converter_load_part) begin case (main_rx_converter_converter_demux) 1'd0: begin main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; end 1'd1: begin main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; end 2'd2: begin main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; end 2'd3: begin main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; end endcase end if (main_rx_converter_converter_load_part) begin main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); end main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; if (eth_rx_rst) begin main_maccore_ethphy_liteethphyrgmiirx_source_valid <= 1'd0; main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= 8'd0; main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= 1'd0; main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; main_liteethmaccrc32checker_syncfifo_level <= 3'd0; main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; main_crc32_checker_source_valid <= 1'd0; main_crc32_checker_source_payload_data <= 8'd0; main_crc32_checker_source_payload_last_be <= 1'd0; main_crc32_checker_source_payload_error <= 1'd0; main_rx_converter_converter_source_payload_data <= 40'd0; main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; main_rx_converter_converter_demux <= 2'd0; main_rx_converter_converter_strobe_all <= 1'd0; main_rx_cdc_cdc_graycounter0_q <= 6'd0; main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; builder_liteethmacpreamblechecker_state <= 1'd0; builder_liteethmaccrc32checker_state <= 2'd0; end builder_xilinxmultiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q; builder_xilinxmultiregimpl6_regs1 <= builder_xilinxmultiregimpl6_regs0; end always @(posedge eth_tx_clk) begin builder_liteethmacgap_state <= builder_liteethmacgap_next_state; if (main_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin main_tx_gap_inserter_counter <= main_tx_gap_inserter_counter_liteethmacgap_next_value; end builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state; if (main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin main_preamble_inserter_count <= main_preamble_inserter_count_liteethmacpreambleinserter_next_value; end if (main_liteethmaccrc32inserter_is_ongoing0) begin main_liteethmaccrc32inserter_cnt <= 2'd3; end else begin if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready); end end if (main_liteethmaccrc32inserter_ce) begin main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next; end if (main_liteethmaccrc32inserter_reset) begin main_liteethmaccrc32inserter_reg <= 32'd4294967295; end builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state; if (((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready)) begin main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid; main_crc32_inserter_source_first <= main_crc32_inserter_sink_first; main_crc32_inserter_source_last <= main_crc32_inserter_sink_last; main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data; main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be; main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error; end builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state; if (main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin main_padding_inserter_counter <= main_padding_inserter_counter_liteethmacpaddinginserter_next_value; end builder_liteethmactxlastbe_state <= builder_liteethmactxlastbe_next_state; if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin if (main_tx_converter_converter_last) begin main_tx_converter_converter_mux <= 1'd0; end else begin main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); end end main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; if (eth_tx_rst) begin main_liteethmaccrc32inserter_reg <= 32'd4294967295; main_liteethmaccrc32inserter_cnt <= 2'd3; main_crc32_inserter_source_valid <= 1'd0; main_crc32_inserter_source_payload_data <= 8'd0; main_crc32_inserter_source_payload_last_be <= 1'd0; main_crc32_inserter_source_payload_error <= 1'd0; main_padding_inserter_counter <= 16'd0; main_tx_converter_converter_mux <= 2'd0; main_tx_cdc_cdc_graycounter1_q <= 6'd0; main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; builder_liteethmacgap_state <= 1'd0; builder_liteethmacpreambleinserter_state <= 2'd0; builder_liteethmaccrc32inserter_state <= 2'd0; builder_liteethmacpaddinginserter_state <= 1'd0; builder_liteethmactxlastbe_state <= 1'd0; end builder_xilinxmultiregimpl3_regs0 <= main_tx_cdc_cdc_graycounter0_q; builder_xilinxmultiregimpl3_regs1 <= builder_xilinxmultiregimpl3_regs0; end always @(posedge por_clk) begin main_maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin if (main_maccore_maccore_bus_error) begin main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); end end if (main_ps_preamble_error_o) begin main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); end if (main_ps_crc_error_o) begin main_crc_errors_status <= (main_crc_errors_status + 1'd1); end main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o; main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o; main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; if (main_writer_slot_ce) begin main_writer_slot <= (main_writer_slot + 1'd1); end if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin main_writer_stat_fifo_produce <= (main_writer_stat_fifo_produce + 1'd1); end if (main_writer_stat_fifo_do_read) begin main_writer_stat_fifo_consume <= (main_writer_stat_fifo_consume + 1'd1); end if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin if ((~main_writer_stat_fifo_do_read)) begin main_writer_stat_fifo_level <= (main_writer_stat_fifo_level + 1'd1); end end else begin if (main_writer_stat_fifo_do_read) begin main_writer_stat_fifo_level <= (main_writer_stat_fifo_level - 1'd1); end end builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; if (main_writer_counter_t_next_value_ce) begin main_writer_counter <= main_writer_counter_t_next_value; end if (main_writer_errors_status_f_next_value_ce) begin main_writer_errors_status <= main_writer_errors_status_f_next_value; end if (main_reader_eventsourcepulse_clear) begin main_reader_eventsourcepulse_pending <= 1'd0; end if (main_reader_eventsourcepulse_trigger) begin main_reader_eventsourcepulse_pending <= 1'd1; end if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin main_reader_cmd_fifo_produce <= (main_reader_cmd_fifo_produce + 1'd1); end if (main_reader_cmd_fifo_do_read) begin main_reader_cmd_fifo_consume <= (main_reader_cmd_fifo_consume + 1'd1); end if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin if ((~main_reader_cmd_fifo_do_read)) begin main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level + 1'd1); end end else begin if (main_reader_cmd_fifo_do_read) begin main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level - 1'd1); end end builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; if (main_reader_counter_next_value_ce) begin main_reader_counter <= main_reader_counter_next_value; end main_sram0_bus_ack0 <= 1'd0; if (((main_sram0_bus_cyc0 & main_sram0_bus_stb0) & (~main_sram0_bus_ack0))) begin main_sram0_bus_ack0 <= 1'd1; end main_sram1_bus_ack0 <= 1'd0; if (((main_sram1_bus_cyc0 & main_sram1_bus_stb0) & (~main_sram1_bus_ack0))) begin main_sram1_bus_ack0 <= 1'd1; end main_sram0_bus_ack1 <= 1'd0; if (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & (~main_sram0_bus_ack1))) begin main_sram0_bus_ack1 <= 1'd1; end main_sram1_bus_ack1 <= 1'd0; if (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & (~main_sram1_bus_ack1))) begin main_sram1_bus_ack1 <= 1'd1; end main_slave_sel_r <= main_slave_sel; builder_state <= builder_next_state; builder_slave_sel_r <= builder_slave_sel; if (builder_wait) begin if ((~builder_done)) begin builder_count <= (builder_count - 1'd1); end end else begin builder_count <= 20'd1000000; end builder_interface0_bank_bus_dat_r <= 1'd0; if (builder_csrbank0_sel) begin case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; end 1'd1: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; end 2'd2: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; end endcase end if (builder_csrbank0_reset0_re) begin main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; end main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; if (builder_csrbank0_scratch0_re) begin main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; end main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; builder_interface1_bank_bus_dat_r <= 1'd0; if (builder_csrbank1_sel) begin case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; end 1'd1: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; end 2'd2: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; end 2'd3: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; end 3'd4: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; end 3'd5: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; end 3'd6: begin builder_interface1_bank_bus_dat_r <= main_reader_start_start_w; end 3'd7: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; end 4'd8: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; end 4'd9: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; end 4'd10: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; end 4'd11: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; end 4'd12: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; end 4'd13: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; end 4'd14: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; end 4'd15: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w; end 5'd16: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w; end endcase end main_writer_slot_re <= builder_csrbank1_sram_writer_slot_re; main_writer_length_re <= builder_csrbank1_sram_writer_length_re; main_writer_errors_re <= builder_csrbank1_sram_writer_errors_re; main_writer_status_re <= builder_csrbank1_sram_writer_ev_status_re; if (builder_csrbank1_sram_writer_ev_pending_re) begin main_writer_pending_r <= builder_csrbank1_sram_writer_ev_pending_r; end main_writer_pending_re <= builder_csrbank1_sram_writer_ev_pending_re; if (builder_csrbank1_sram_writer_ev_enable0_re) begin main_writer_enable_storage <= builder_csrbank1_sram_writer_ev_enable0_r; end main_writer_enable_re <= builder_csrbank1_sram_writer_ev_enable0_re; main_reader_ready_re <= builder_csrbank1_sram_reader_ready_re; main_reader_level_re <= builder_csrbank1_sram_reader_level_re; if (builder_csrbank1_sram_reader_slot0_re) begin main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r; end main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re; if (builder_csrbank1_sram_reader_length0_re) begin main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; end main_reader_length_re <= builder_csrbank1_sram_reader_length0_re; main_reader_status_re <= builder_csrbank1_sram_reader_ev_status_re; if (builder_csrbank1_sram_reader_ev_pending_re) begin main_reader_pending_r <= builder_csrbank1_sram_reader_ev_pending_r; end main_reader_pending_re <= builder_csrbank1_sram_reader_ev_pending_re; if (builder_csrbank1_sram_reader_ev_enable0_re) begin main_reader_enable_storage <= builder_csrbank1_sram_reader_ev_enable0_r; end main_reader_enable_re <= builder_csrbank1_sram_reader_ev_enable0_re; main_preamble_crc_re <= builder_csrbank1_preamble_crc_re; main_preamble_errors_re <= builder_csrbank1_preamble_errors_re; main_crc_errors_re <= builder_csrbank1_crc_errors_re; builder_interface2_bank_bus_dat_r <= 1'd0; if (builder_csrbank2_sel) begin case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; end 1'd1: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; end 2'd2: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; end endcase end if (builder_csrbank2_crg_reset0_re) begin main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; end main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; if (builder_csrbank2_mdio_w0_re) begin main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; end main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; if (sys_rst) begin main_maccore_maccore_reset_storage <= 2'd0; main_maccore_maccore_reset_re <= 1'd0; main_maccore_maccore_scratch_storage <= 32'd305419896; main_maccore_maccore_scratch_re <= 1'd0; main_maccore_maccore_bus_errors_re <= 1'd0; main_maccore_maccore_bus_errors <= 32'd0; main_maccore_ethphy_reset_storage <= 1'd0; main_maccore_ethphy_reset_re <= 1'd0; main_maccore_ethphy__w_storage <= 3'd0; main_maccore_ethphy__w_re <= 1'd0; main_maccore_ethphy__r_re <= 1'd0; main_preamble_crc_re <= 1'd0; main_preamble_errors_status <= 32'd0; main_preamble_errors_re <= 1'd0; main_crc_errors_status <= 32'd0; main_crc_errors_re <= 1'd0; main_tx_cdc_cdc_graycounter0_q <= 6'd0; main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; main_rx_cdc_cdc_graycounter1_q <= 6'd0; main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; main_writer_slot_re <= 1'd0; main_writer_length_re <= 1'd0; main_writer_errors_status <= 32'd0; main_writer_errors_re <= 1'd0; main_writer_status_re <= 1'd0; main_writer_pending_re <= 1'd0; main_writer_pending_r <= 1'd0; main_writer_enable_storage <= 1'd0; main_writer_enable_re <= 1'd0; main_writer_counter <= 32'd0; main_writer_slot <= 1'd0; main_writer_stat_fifo_level <= 2'd0; main_writer_stat_fifo_produce <= 1'd0; main_writer_stat_fifo_consume <= 1'd0; main_reader_ready_re <= 1'd0; main_reader_level_re <= 1'd0; main_reader_slot_re <= 1'd0; main_reader_length_re <= 1'd0; main_reader_eventsourcepulse_pending <= 1'd0; main_reader_status_re <= 1'd0; main_reader_pending_re <= 1'd0; main_reader_pending_r <= 1'd0; main_reader_enable_storage <= 1'd0; main_reader_enable_re <= 1'd0; main_reader_cmd_fifo_level <= 2'd0; main_reader_cmd_fifo_produce <= 1'd0; main_reader_cmd_fifo_consume <= 1'd0; main_reader_counter <= 11'd0; main_sram0_bus_ack0 <= 1'd0; main_sram1_bus_ack0 <= 1'd0; main_sram0_bus_ack1 <= 1'd0; main_sram1_bus_ack1 <= 1'd0; main_slave_sel_r <= 4'd0; builder_liteethmacsramwriter_state <= 3'd0; builder_liteethmacsramreader_state <= 2'd0; builder_slave_sel_r <= 2'd0; builder_count <= 20'd1000000; builder_state <= 1'd0; end builder_xilinxmultiregimpl0_regs0 <= main_maccore_ethphy_data_r; builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0; builder_xilinxmultiregimpl1_regs0 <= main_ps_preamble_error_toggle_i; builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0; builder_xilinxmultiregimpl2_regs0 <= main_ps_crc_error_toggle_i; builder_xilinxmultiregimpl2_regs1 <= builder_xilinxmultiregimpl2_regs0; builder_xilinxmultiregimpl4_regs0 <= main_tx_cdc_cdc_graycounter1_q; builder_xilinxmultiregimpl4_regs1 <= builder_xilinxmultiregimpl4_regs0; builder_xilinxmultiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q; builder_xilinxmultiregimpl5_regs1 <= builder_xilinxmultiregimpl5_regs0; end IBUF IBUF( .I(rgmii_eth_clocks_rx), .O(main_maccore_ethphy_eth_rx_clk_ibuf) ); BUFG BUFG( .I(main_maccore_ethphy_eth_rx_clk_ibuf), .O(eth_rx_clk) ); BUFG BUFG_1( .I(main_maccore_ethphy_clkout0), .O(main_maccore_ethphy_clkout_buf0) ); BUFG BUFG_2( .I(main_maccore_ethphy_clkout1), .O(main_maccore_ethphy_clkout_buf1) ); ODDR #( .DDR_CLK_EDGE("SAME_EDGE") ) ODDR ( .C(eth_tx_delayed_clk), .CE(1'd1), .D1(1'd1), .D2(1'd0), .R(1'd0), .S(1'd0), .Q(main_maccore_ethphy_eth_tx_clk_obuf) ); OBUF OBUF( .I(main_maccore_ethphy_eth_tx_clk_obuf), .O(rgmii_eth_clocks_tx) ); ODDR #( .DDR_CLK_EDGE("SAME_EDGE") ) ODDR_1 ( .C(eth_tx_clk), .CE(1'd1), .D1(main_maccore_ethphy_sink_valid), .D2(main_maccore_ethphy_sink_valid), .R(1'd0), .S(1'd0), .Q(main_maccore_ethphy_tx_ctl_obuf) ); OBUF OBUF_1( .I(main_maccore_ethphy_tx_ctl_obuf), .O(rgmii_eth_tx_ctl) ); ODDR #( .DDR_CLK_EDGE("SAME_EDGE") ) ODDR_2 ( .C(eth_tx_clk), .CE(1'd1), .D1(main_maccore_ethphy_sink_payload_data[0]), .D2(main_maccore_ethphy_sink_payload_data[4]), .R(1'd0), .S(1'd0), .Q(main_maccore_ethphy_tx_data_obuf[0]) ); OBUF OBUF_2( .I(main_maccore_ethphy_tx_data_obuf[0]), .O(rgmii_eth_tx_data[0]) ); ODDR #( .DDR_CLK_EDGE("SAME_EDGE") ) ODDR_3 ( .C(eth_tx_clk), .CE(1'd1), .D1(main_maccore_ethphy_sink_payload_data[1]), .D2(main_maccore_ethphy_sink_payload_data[5]), .R(1'd0), .S(1'd0), .Q(main_maccore_ethphy_tx_data_obuf[1]) ); OBUF OBUF_3( .I(main_maccore_ethphy_tx_data_obuf[1]), .O(rgmii_eth_tx_data[1]) ); ODDR #( .DDR_CLK_EDGE("SAME_EDGE") ) ODDR_4 ( .C(eth_tx_clk), .CE(1'd1), .D1(main_maccore_ethphy_sink_payload_data[2]), .D2(main_maccore_ethphy_sink_payload_data[6]), .R(1'd0), .S(1'd0), .Q(main_maccore_ethphy_tx_data_obuf[2]) ); OBUF OBUF_4( .I(main_maccore_ethphy_tx_data_obuf[2]), .O(rgmii_eth_tx_data[2]) ); ODDR #( .DDR_CLK_EDGE("SAME_EDGE") ) ODDR_5 ( .C(eth_tx_clk), .CE(1'd1), .D1(main_maccore_ethphy_sink_payload_data[3]), .D2(main_maccore_ethphy_sink_payload_data[7]), .R(1'd0), .S(1'd0), .Q(main_maccore_ethphy_tx_data_obuf[3]) ); OBUF OBUF_5( .I(main_maccore_ethphy_tx_data_obuf[3]), .O(rgmii_eth_tx_data[3]) ); IBUF IBUF_1( .I(rgmii_eth_rx_ctl), .O(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf) ); IDELAYE2 #( .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(5'd26), .REFCLK_FREQUENCY(200.0) ) IDELAYE2 ( .C(1'd0), .CE(1'd0), .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf), .INC(1'd0), .LD(1'd0), .LDPIPEEN(1'd0), .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay) ); IDDR #( .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") ) IDDR ( .C(eth_rx_clk), .CE(1'd1), .D(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay), .R(1'd0), .S(1'd0), .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl), .Q2(main_maccore_ethphy_liteethphyrgmiirx) ); IBUF IBUF_2( .I(rgmii_eth_rx_data[0]), .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]) ); IDELAYE2 #( .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(5'd26), .REFCLK_FREQUENCY(200.0) ) IDELAYE2_1 ( .C(1'd0), .CE(1'd0), .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]), .INC(1'd0), .LD(1'd0), .LDPIPEEN(1'd0), .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]) ); IDDR #( .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") ) IDDR_1 ( .C(eth_rx_clk), .CE(1'd1), .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]), .R(1'd0), .S(1'd0), .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[0]), .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[4]) ); IBUF IBUF_3( .I(rgmii_eth_rx_data[1]), .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]) ); IDELAYE2 #( .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(5'd26), .REFCLK_FREQUENCY(200.0) ) IDELAYE2_2 ( .C(1'd0), .CE(1'd0), .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]), .INC(1'd0), .LD(1'd0), .LDPIPEEN(1'd0), .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]) ); IDDR #( .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") ) IDDR_2 ( .C(eth_rx_clk), .CE(1'd1), .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]), .R(1'd0), .S(1'd0), .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[1]), .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[5]) ); IBUF IBUF_4( .I(rgmii_eth_rx_data[2]), .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]) ); IDELAYE2 #( .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(5'd26), .REFCLK_FREQUENCY(200.0) ) IDELAYE2_3 ( .C(1'd0), .CE(1'd0), .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]), .INC(1'd0), .LD(1'd0), .LDPIPEEN(1'd0), .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]) ); IDDR #( .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") ) IDDR_3 ( .C(eth_rx_clk), .CE(1'd1), .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]), .R(1'd0), .S(1'd0), .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[2]), .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[6]) ); IBUF IBUF_5( .I(rgmii_eth_rx_data[3]), .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]) ); IDELAYE2 #( .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(5'd26), .REFCLK_FREQUENCY(200.0) ) IDELAYE2_4 ( .C(1'd0), .CE(1'd0), .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]), .INC(1'd0), .LD(1'd0), .LDPIPEEN(1'd0), .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]) ); IDDR #( .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") ) IDDR_4 ( .C(eth_rx_clk), .CE(1'd1), .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]), .R(1'd0), .S(1'd0), .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[3]), .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[7]) ); assign rgmii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; assign main_maccore_ethphy_data_r = rgmii_eth_mdio; reg [11:0] storage[0:4]; reg [11:0] memdat; always @(posedge eth_rx_clk) begin if (main_liteethmaccrc32checker_syncfifo_wrport_we) storage[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; memdat <= storage[main_liteethmaccrc32checker_syncfifo_wrport_adr]; end always @(posedge eth_rx_clk) begin end assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat; assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[main_liteethmaccrc32checker_syncfifo_rdport_adr]; reg [41:0] storage_1[0:31]; reg [4:0] memadr; reg [4:0] memadr_1; always @(posedge sys_clk) begin if (main_tx_cdc_cdc_wrport_we) storage_1[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; memadr <= main_tx_cdc_cdc_wrport_adr; end always @(posedge eth_tx_clk) begin memadr_1 <= main_tx_cdc_cdc_rdport_adr; end assign main_tx_cdc_cdc_wrport_dat_r = storage_1[memadr]; assign main_tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1]; reg [41:0] storage_2[0:31]; reg [4:0] memadr_2; reg [4:0] memadr_3; always @(posedge eth_rx_clk) begin if (main_rx_cdc_cdc_wrport_we) storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; memadr_2 <= main_rx_cdc_cdc_wrport_adr; end always @(posedge sys_clk) begin memadr_3 <= main_rx_cdc_cdc_rdport_adr; end assign main_rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2]; assign main_rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3]; reg [34:0] storage_3[0:1]; reg [34:0] memdat_1; always @(posedge sys_clk) begin if (main_writer_stat_fifo_wrport_we) storage_3[main_writer_stat_fifo_wrport_adr] <= main_writer_stat_fifo_wrport_dat_w; memdat_1 <= storage_3[main_writer_stat_fifo_wrport_adr]; end always @(posedge sys_clk) begin end assign main_writer_stat_fifo_wrport_dat_r = memdat_1; assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr]; reg [31:0] mem[0:381]; reg [8:0] memadr_4; reg [31:0] memdat_2; always @(posedge sys_clk) begin if (main_writer_memory0_we) mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w; memadr_4 <= main_writer_memory0_adr; end always @(posedge sys_clk) begin memdat_2 <= mem[main_sram0_adr0]; end assign main_writer_memory0_dat_r = mem[memadr_4]; assign main_sram0_dat_r0 = memdat_2; reg [31:0] mem_1[0:381]; reg [8:0] memadr_5; reg [31:0] memdat_3; always @(posedge sys_clk) begin if (main_writer_memory1_we) mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w; memadr_5 <= main_writer_memory1_adr; end always @(posedge sys_clk) begin memdat_3 <= mem_1[main_sram1_adr0]; end assign main_writer_memory1_dat_r = mem_1[memadr_5]; assign main_sram1_dat_r0 = memdat_3; reg [13:0] storage_4[0:1]; reg [13:0] memdat_4; always @(posedge sys_clk) begin if (main_reader_cmd_fifo_wrport_we) storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w; memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr]; end always @(posedge sys_clk) begin end assign main_reader_cmd_fifo_wrport_dat_r = memdat_4; assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr]; reg [31:0] mem_2[0:381]; reg [8:0] memadr_6; reg [8:0] memadr_7; always @(posedge sys_clk) begin memadr_6 <= main_reader_memory0_adr; end always @(posedge sys_clk) begin if (main_sram0_we[0]) mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0]; if (main_sram0_we[1]) mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8]; if (main_sram0_we[2]) mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16]; if (main_sram0_we[3]) mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24]; memadr_7 <= main_sram0_adr1; end assign main_reader_memory0_dat_r = mem_2[memadr_6]; assign main_sram0_dat_r1 = mem_2[memadr_7]; reg [31:0] mem_3[0:381]; reg [8:0] memadr_8; reg [8:0] memadr_9; always @(posedge sys_clk) begin memadr_8 <= main_reader_memory1_adr; end always @(posedge sys_clk) begin if (main_sram1_we[0]) mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0]; if (main_sram1_we[1]) mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8]; if (main_sram1_we[2]) mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16]; if (main_sram1_we[3]) mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24]; memadr_9 <= main_sram1_adr1; end assign main_reader_memory1_dat_r = mem_3[memadr_8]; assign main_sram1_dat_r1 = mem_3[memadr_9]; FD FD( .C(main_maccore_ethphy_clkin), .D(main_maccore_ethphy_reset0), .Q(builder_reset0) ); FD FD_1( .C(main_maccore_ethphy_clkin), .D(builder_reset0), .Q(builder_reset1) ); FD FD_2( .C(main_maccore_ethphy_clkin), .D(builder_reset1), .Q(builder_reset2) ); FD FD_3( .C(main_maccore_ethphy_clkin), .D(builder_reset2), .Q(builder_reset3) ); FD FD_4( .C(main_maccore_ethphy_clkin), .D(builder_reset3), .Q(builder_reset4) ); FD FD_5( .C(main_maccore_ethphy_clkin), .D(builder_reset4), .Q(builder_reset5) ); FD FD_6( .C(main_maccore_ethphy_clkin), .D(builder_reset5), .Q(builder_reset6) ); FD FD_7( .C(main_maccore_ethphy_clkin), .D(builder_reset6), .Q(builder_reset7) ); PLLE2_ADV #( .CLKFBOUT_MULT(4'd12), .CLKIN1_PERIOD(8.0), .CLKOUT0_DIVIDE(4'd12), .CLKOUT0_PHASE(1'd0), .CLKOUT1_DIVIDE(4'd12), .CLKOUT1_PHASE(90.0), .DIVCLK_DIVIDE(1'd1), .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( .CLKFBIN(builder_pll_fb), .CLKIN1(main_maccore_ethphy_clkin), .PWRDWN(main_maccore_ethphy_power_down), .RST(builder_reset7), .CLKFBOUT(builder_pll_fb), .CLKOUT0(main_maccore_ethphy_clkout0), .CLKOUT1(main_maccore_ethphy_clkout1), .LOCKED(main_maccore_ethphy_locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE ( .C(eth_tx_delayed_clk), .CE(1'd1), .D(1'd0), .PRE(builder_xilinxasyncresetsynchronizerimpl0), .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(eth_tx_delayed_clk), .CE(1'd1), .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), .PRE(builder_xilinxasyncresetsynchronizerimpl0), .Q(builder_xilinxasyncresetsynchronizerimpl0_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(eth_tx_clk), .CE(1'd1), .D(1'd0), .PRE(main_maccore_ethphy_reset1), .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(eth_tx_clk), .CE(1'd1), .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), .PRE(main_maccore_ethphy_reset1), .Q(eth_tx_rst) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(eth_rx_clk), .CE(1'd1), .D(1'd0), .PRE(main_maccore_ethphy_reset1), .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(eth_rx_clk), .CE(1'd1), .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), .PRE(main_maccore_ethphy_reset1), .Q(eth_rx_rst) ); endmodule