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1320 lines
33 KiB
Verilog
1320 lines
33 KiB
Verilog
/* Generated by Yosys 0.15+31 (git sha1 a502570c2, gcc 11.2.1 -fPIC -Os) */
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module bridge(wb__dat_w, wb__dat_r, wb__sel, wb__cyc, wb__stb, wb__we, wb__ack, rst, clk, csr__addr, csr__r_stb, csr__w_stb, csr__w_data, csr__r_data, wb__adr);
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reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
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wire \$1 ;
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wire \$11 ;
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wire \$13 ;
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wire \$15 ;
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wire \$17 ;
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wire \$3 ;
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wire \$5 ;
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wire \$7 ;
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wire \$9 ;
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input clk;
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wire clk;
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output csr__addr;
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wire csr__addr;
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input [31:0] csr__r_data;
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wire [31:0] csr__r_data;
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output csr__r_stb;
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reg csr__r_stb;
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output [31:0] csr__w_data;
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reg [31:0] csr__w_data;
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output csr__w_stb;
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reg csr__w_stb;
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reg cycle = 1'h0;
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reg \cycle$next ;
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input rst;
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wire rst;
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output wb__ack;
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reg wb__ack = 1'h0;
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reg \wb__ack$next ;
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input wb__adr;
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wire wb__adr;
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input wb__cyc;
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wire wb__cyc;
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output [31:0] wb__dat_r;
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reg [31:0] wb__dat_r = 32'd0;
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reg [31:0] \wb__dat_r$next ;
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input [31:0] wb__dat_w;
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wire [31:0] wb__dat_w;
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input wb__sel;
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wire wb__sel;
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input wb__stb;
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wire wb__stb;
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input wb__we;
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wire wb__we;
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assign \$9 = wb__cyc & wb__stb;
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assign \$11 = wb__sel & wb__we;
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assign \$13 = wb__cyc & wb__stb;
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assign \$15 = wb__cyc & wb__stb;
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assign \$17 = wb__cyc & wb__stb;
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always @(posedge clk)
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cycle <= \cycle$next ;
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assign \$1 = wb__cyc & wb__stb;
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always @(posedge clk)
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wb__dat_r <= \wb__dat_r$next ;
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always @(posedge clk)
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wb__ack <= \wb__ack$next ;
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assign \$3 = ~ wb__we;
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assign \$5 = wb__sel & \$3 ;
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assign \$7 = wb__cyc & wb__stb;
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
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csr__r_stb = 1'h0;
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casez (\$1 )
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1'h1:
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casez (cycle)
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1'h0:
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csr__r_stb = \$5 ;
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endcase
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endcase
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end
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
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csr__w_data = 32'd0;
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casez (\$7 )
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1'h1:
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casez (cycle)
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1'h0:
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csr__w_data = wb__dat_w;
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endcase
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endcase
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end
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
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csr__w_stb = 1'h0;
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casez (\$9 )
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1'h1:
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casez (cycle)
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1'h0:
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csr__w_stb = \$11 ;
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endcase
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endcase
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end
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
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\cycle$next = cycle;
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casez (\$13 )
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1'h1:
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casez (cycle)
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1'h0:
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\cycle$next = 1'h1;
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endcase
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endcase
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casez (wb__ack)
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1'h1:
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\cycle$next = 1'h0;
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endcase
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casez (rst)
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1'h1:
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\cycle$next = 1'h0;
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endcase
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end
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
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\wb__dat_r$next = wb__dat_r;
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casez (\$15 )
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1'h1:
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(* full_case = 32'd1 *)
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casez (cycle)
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1'h0:
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/* empty */;
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default:
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\wb__dat_r$next = csr__r_data;
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endcase
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endcase
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casez (rst)
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1'h1:
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\wb__dat_r$next = 32'd0;
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endcase
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end
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
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\wb__ack$next = wb__ack;
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casez (\$17 )
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1'h1:
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(* full_case = 32'd1 *)
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casez (cycle)
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1'h0:
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/* empty */;
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default:
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\wb__ack$next = 1'h1;
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endcase
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endcase
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casez (wb__ack)
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1'h1:
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\wb__ack$next = 1'h0;
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endcase
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casez (rst)
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1'h1:
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\wb__ack$next = 1'h0;
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endcase
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end
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assign csr__addr = wb__adr;
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endmodule
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module mux(bus_out, parity_out, clk_out, enabled, wb__adr, wb__dat_w, wb__sel, wb__cyc, wb__stb, wb__we, wb__dat_r, wb__ack, wb__stall, wb_ctrl__adr, wb_ctrl__dat_w, wb_ctrl__sel, wb_ctrl__cyc, wb_ctrl__stb, wb_ctrl__we, wb_ctrl__dat_r, wb_ctrl__ack
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, wb_ctrl_stall, rst, clk, bus_in);
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reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
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wire [8:0] \$1 ;
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wire \$10 ;
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wire [4:0] \$100 ;
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wire \$102 ;
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wire [4:0] \$104 ;
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wire [4:0] \$105 ;
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wire \$107 ;
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wire [4:0] \$109 ;
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wire [4:0] \$110 ;
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wire \$112 ;
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wire \$114 ;
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wire [4:0] \$116 ;
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wire [4:0] \$117 ;
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wire \$119 ;
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wire \$12 ;
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wire \$120 ;
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wire \$14 ;
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wire \$16 ;
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wire \$18 ;
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wire [8:0] \$2 ;
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wire \$20 ;
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wire \$22 ;
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wire \$24 ;
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wire \$26 ;
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wire \$28 ;
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wire \$30 ;
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wire \$32 ;
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wire \$34 ;
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wire \$36 ;
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wire \$38 ;
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wire \$4 ;
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wire \$40 ;
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wire \$42 ;
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wire \$44 ;
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wire \$46 ;
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wire \$48 ;
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wire \$50 ;
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wire [34:0] \$52 ;
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wire [31:0] \$53 ;
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wire [31:0] \$57 ;
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wire [31:0] \$59 ;
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wire \$6 ;
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wire \$61 ;
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wire [31:0] \$63 ;
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wire \$65 ;
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wire [31:0] \$67 ;
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wire [63:0] \$69 ;
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wire [63:0] \$71 ;
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wire \$73 ;
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wire [63:0] \$75 ;
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wire \$77 ;
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wire \$79 ;
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wire \$8 ;
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wire \$81 ;
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wire \$83 ;
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wire \$85 ;
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wire \$87 ;
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wire \$89 ;
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wire \$91 ;
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wire [34:0] \$93 ;
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wire [31:0] \$94 ;
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wire \$97 ;
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wire [4:0] \$99 ;
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reg [31:0] addr = 32'd0;
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reg [31:0] \addr$next ;
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wire bridge_wb__ack;
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wire bridge_wb__adr;
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wire bridge_wb__cyc;
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wire [31:0] bridge_wb__dat_r;
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wire [31:0] bridge_wb__dat_w;
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wire bridge_wb__sel;
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wire bridge_wb__stb;
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wire bridge_wb__we;
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input [7:0] bus_in;
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wire [7:0] bus_in;
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output [7:0] bus_out;
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reg [7:0] bus_out = 8'h00;
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reg [7:0] \bus_out$next ;
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input clk;
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wire clk;
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output clk_out;
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reg clk_out;
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wire clk_strobe;
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reg [7:0] clock_counter = 8'h00;
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reg [7:0] \clock_counter$next ;
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wire [2:0] clock_divisor;
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wire clock_strobe;
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reg [31:0] \config = 32'd1;
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reg [31:0] \config$next ;
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reg [3:0] count = 4'h0;
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reg [3:0] \count$next ;
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reg [63:0] data = 64'h0000000000000000;
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reg [63:0] \data$next ;
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output enabled;
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wire enabled;
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wire is_read;
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wire is_write;
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wire [31:0] mux_config_csr__r_data;
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wire [31:0] mux_config_csr__w_data;
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wire mux_config_csr__w_stb;
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wire mux_csr__addr;
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wire [31:0] mux_csr__r_data;
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wire mux_csr__r_stb;
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wire [31:0] mux_csr__w_data;
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wire mux_csr__w_stb;
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wire [31:0] mux_status_csr__r_data;
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wire [31:0] mux_status_csr__w_data;
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wire mux_status_csr__w_stb;
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output parity_out;
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wire parity_out;
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reg prev_clk = 1'h0;
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reg \prev_clk$next ;
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input rst;
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wire rst;
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reg [34:0] s;
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reg [34:0] \s$56 ;
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reg [7:0] sel = 8'h00;
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reg [7:0] \sel$next ;
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(* enum_base_type = "StateEnum" *)
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(* enum_value_0000 = "IDLE" *)
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(* enum_value_0001 = "WRITE_CMD" *)
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(* enum_value_0010 = "READ_CMD" *)
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(* enum_value_0011 = "WRITE_ADDR" *)
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(* enum_value_0100 = "READ_ADDR" *)
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(* enum_value_0101 = "WRITE_SEL" *)
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(* enum_value_0110 = "READ_SEL" *)
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(* enum_value_0111 = "WRITE_DATA" *)
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(* enum_value_1000 = "READ_DATA" *)
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(* enum_value_1001 = "WRITE_ACK" *)
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(* enum_value_1010 = "READ_ACK" *)
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(* enum_value_1011 = "WISHBONE_ACK" *)
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reg [3:0] state = 4'h0;
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reg [3:0] \state$next ;
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reg [31:0] status = 32'd0;
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reg [31:0] \status$next ;
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output wb__ack;
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reg wb__ack = 1'h0;
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reg \wb__ack$next ;
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input [28:0] wb__adr;
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wire [28:0] wb__adr;
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input wb__cyc;
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wire wb__cyc;
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output [63:0] wb__dat_r;
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wire [63:0] wb__dat_r;
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input [63:0] wb__dat_w;
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wire [63:0] wb__dat_w;
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input [7:0] wb__sel;
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wire [7:0] wb__sel;
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output wb__stall;
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reg wb__stall;
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input wb__stb;
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wire wb__stb;
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input wb__we;
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wire wb__we;
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output wb_ctrl__ack;
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wire wb_ctrl__ack;
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input [29:0] wb_ctrl__adr;
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wire [29:0] wb_ctrl__adr;
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input wb_ctrl__cyc;
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wire wb_ctrl__cyc;
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output [31:0] wb_ctrl__dat_r;
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wire [31:0] wb_ctrl__dat_r;
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input [31:0] wb_ctrl__dat_w;
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wire [31:0] wb_ctrl__dat_w;
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input [3:0] wb_ctrl__sel;
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wire [3:0] wb_ctrl__sel;
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input wb_ctrl__stb;
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wire wb_ctrl__stb;
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input wb_ctrl__we;
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wire wb_ctrl__we;
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output wb_ctrl_stall;
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reg wb_ctrl_stall;
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assign \$100 = count - 1'h1;
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assign \$102 = | count;
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assign \$105 = count - 1'h1;
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assign \$107 = | count;
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assign \$10 = clock_divisor == 2'h3;
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assign \$110 = count - 1'h1;
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assign \$112 = bus_in == 8'h82;
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assign \$114 = | count;
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assign \$117 = count - 1'h1;
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assign \$120 = ^ bus_out;
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assign \$119 = ~ \$120 ;
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always @(posedge clk)
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clock_counter <= \clock_counter$next ;
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always @(posedge clk)
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prev_clk <= \prev_clk$next ;
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always @(posedge clk)
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bus_out <= \bus_out$next ;
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always @(posedge clk)
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wb__ack <= \wb__ack$next ;
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always @(posedge clk)
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addr <= \addr$next ;
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always @(posedge clk)
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data <= \data$next ;
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always @(posedge clk)
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sel <= \sel$next ;
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assign \$12 = clock_divisor == 3'h4;
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always @(posedge clk)
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state <= \state$next ;
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always @(posedge clk)
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count <= \count$next ;
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always @(posedge clk)
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\config <= \config$next ;
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always @(posedge clk)
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status <= \status$next ;
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assign \$14 = clock_divisor == 3'h5;
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assign \$16 = clock_divisor == 3'h6;
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assign \$18 = clock_divisor == 3'h7;
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assign \$20 = ~ prev_clk;
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assign \$22 = \$20 & clk_out;
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assign \$24 = wb__stb & wb__cyc;
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assign \$26 = \$24 & wb__we;
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assign \$28 = wb__stb & wb__cyc;
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assign \$2 = clock_counter + 1'h1;
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assign \$30 = ~ wb__we;
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assign \$32 = \$28 & \$30 ;
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assign \$34 = ~ wb__cyc;
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assign \$36 = ~ wb__ack;
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assign \$38 = ~ wb_ctrl__cyc;
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assign \$40 = ~ wb_ctrl__ack;
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assign \$42 = | count;
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assign \$44 = | count;
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assign \$46 = | count;
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assign \$48 = bus_in == 8'h83;
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assign \$4 = ! clock_divisor;
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assign \$50 = | count;
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assign \$52 = + \$53 ;
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assign \$57 = + addr[31:8];
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assign \$59 = + addr[31:8];
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assign \$61 = | count;
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assign \$63 = + addr[31:8];
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assign \$65 = | count;
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assign \$67 = + addr[31:8];
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assign \$6 = clock_divisor == 1'h1;
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assign \$69 = + data[63:8];
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assign \$71 = + data[63:8];
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assign \$73 = | count;
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assign \$75 = + data[63:8];
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assign \$77 = bus_in == 8'h82;
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assign \$79 = | count;
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assign \$81 = | count;
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assign \$83 = | count;
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assign \$85 = | count;
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assign \$87 = bus_in == 8'h83;
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assign \$8 = clock_divisor == 2'h2;
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assign \$89 = bus_in == 8'h82;
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assign \$91 = | count;
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assign \$93 = + \$94 ;
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assign \$97 = | count;
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bridge bridge (
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.clk(clk),
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.csr__addr(mux_csr__addr),
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.csr__r_data(mux_csr__r_data),
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.csr__r_stb(mux_csr__r_stb),
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.csr__w_data(mux_csr__w_data),
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.csr__w_stb(mux_csr__w_stb),
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.rst(rst),
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.wb__ack(bridge_wb__ack),
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.wb__adr(bridge_wb__adr),
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.wb__cyc(bridge_wb__cyc),
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.wb__dat_r(bridge_wb__dat_r),
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.wb__dat_w(bridge_wb__dat_w),
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.wb__sel(bridge_wb__sel),
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.wb__stb(bridge_wb__stb),
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.wb__we(bridge_wb__we)
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);
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\mux$1 mux (
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.clk(clk),
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.config_csr__r_data(mux_config_csr__r_data),
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.config_csr__w_data(mux_config_csr__w_data),
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.config_csr__w_stb(mux_config_csr__w_stb),
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.csr__addr(mux_csr__addr),
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.csr__r_data(mux_csr__r_data),
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.csr__r_stb(mux_csr__r_stb),
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.csr__w_data(mux_csr__w_data),
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.csr__w_stb(mux_csr__w_stb),
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.rst(rst),
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.status_csr__r_data(mux_status_csr__r_data),
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.status_csr__w_data(mux_status_csr__w_data),
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.status_csr__w_stb(mux_status_csr__w_stb)
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);
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
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(* full_case = 32'd1 *)
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casez (\$34 )
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1'h1:
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wb__stall = 1'h0;
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default:
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wb__stall = \$36 ;
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endcase
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end
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
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(* full_case = 32'd1 *)
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casez (\$38 )
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1'h1:
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wb_ctrl_stall = 1'h0;
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default:
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wb_ctrl_stall = \$40 ;
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endcase
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end
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always @* begin
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if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
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\bus_out$next = bus_out;
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casez (state)
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4'h0:
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begin
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\bus_out$next = 8'h00;
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez ({ is_read, is_write })
|
|
2'b?1:
|
|
\bus_out$next = 8'h03;
|
|
2'b1?:
|
|
\bus_out$next = 8'h02;
|
|
endcase
|
|
endcase
|
|
end
|
|
4'h1:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\bus_out$next = addr[7:0];
|
|
endcase
|
|
4'h2:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\bus_out$next = addr[7:0];
|
|
endcase
|
|
4'h3:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$42 )
|
|
1'h1:
|
|
\bus_out$next = addr[7:0];
|
|
default:
|
|
\bus_out$next = sel;
|
|
endcase
|
|
endcase
|
|
4'h4:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$44 )
|
|
1'h1:
|
|
\bus_out$next = addr[7:0];
|
|
default:
|
|
\bus_out$next = sel;
|
|
endcase
|
|
endcase
|
|
4'h5:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\bus_out$next = data[7:0];
|
|
endcase
|
|
4'h6:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\bus_out$next = 8'h00;
|
|
endcase
|
|
4'h7:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$46 )
|
|
1'h1:
|
|
\bus_out$next = data[7:0];
|
|
default:
|
|
\bus_out$next = 8'h00;
|
|
endcase
|
|
endcase
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\bus_out$next = 8'h00;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\wb__ack$next = wb__ack;
|
|
casez (state)
|
|
4'h0:
|
|
\wb__ack$next = 1'h0;
|
|
4'h1:
|
|
/* empty */;
|
|
4'h2:
|
|
/* empty */;
|
|
4'h3:
|
|
/* empty */;
|
|
4'h4:
|
|
/* empty */;
|
|
4'h5:
|
|
/* empty */;
|
|
4'h6:
|
|
/* empty */;
|
|
4'h7:
|
|
/* empty */;
|
|
4'h9:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$48 )
|
|
1'h1:
|
|
\wb__ack$next = 1'h1;
|
|
endcase
|
|
endcase
|
|
4'ha:
|
|
/* empty */;
|
|
4'h8:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$50 )
|
|
1'h1:
|
|
/* empty */;
|
|
default:
|
|
\wb__ack$next = 1'h1;
|
|
endcase
|
|
endcase
|
|
4'hb:
|
|
\wb__ack$next = 1'h0;
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\wb__ack$next = 1'h0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
s = 35'h000000000;
|
|
casez (state)
|
|
4'h0:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez ({ is_read, is_write })
|
|
2'b?1:
|
|
s = \$52 ;
|
|
endcase
|
|
endcase
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\addr$next = addr;
|
|
casez (state)
|
|
4'h0:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez ({ is_read, is_write })
|
|
2'b?1:
|
|
\addr$next = s[31:0];
|
|
2'b1?:
|
|
\addr$next = \s$56 [31:0];
|
|
endcase
|
|
endcase
|
|
4'h1:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\addr$next = \$57 ;
|
|
endcase
|
|
4'h2:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\addr$next = \$59 ;
|
|
endcase
|
|
4'h3:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$61 )
|
|
1'h1:
|
|
\addr$next = \$63 ;
|
|
endcase
|
|
endcase
|
|
4'h4:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$65 )
|
|
1'h1:
|
|
\addr$next = \$67 ;
|
|
endcase
|
|
endcase
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\data$next = data;
|
|
casez (state)
|
|
4'h0:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez ({ is_read, is_write })
|
|
2'b?1:
|
|
\data$next = wb__dat_w;
|
|
endcase
|
|
endcase
|
|
4'h1:
|
|
/* empty */;
|
|
4'h2:
|
|
/* empty */;
|
|
4'h3:
|
|
/* empty */;
|
|
4'h4:
|
|
/* empty */;
|
|
4'h5:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\data$next = \$69 ;
|
|
endcase
|
|
4'h6:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\data$next = \$71 ;
|
|
endcase
|
|
4'h7:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$73 )
|
|
1'h1:
|
|
\data$next = \$75 ;
|
|
endcase
|
|
endcase
|
|
4'h9:
|
|
/* empty */;
|
|
4'ha:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$77 )
|
|
1'h1:
|
|
\data$next = 64'h0000000000000000;
|
|
endcase
|
|
endcase
|
|
4'h8:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$79 )
|
|
1'h1:
|
|
\data$next = { bus_in, data[63:8] };
|
|
endcase
|
|
endcase
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\sel$next = sel;
|
|
casez (state)
|
|
4'h0:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez ({ is_read, is_write })
|
|
2'b?1:
|
|
\sel$next = wb__sel;
|
|
endcase
|
|
endcase
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\state$next = state;
|
|
casez (state)
|
|
4'h0:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez ({ is_read, is_write })
|
|
2'b?1:
|
|
\state$next = 4'h1;
|
|
2'b1?:
|
|
\state$next = 4'h2;
|
|
endcase
|
|
endcase
|
|
4'h1:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\state$next = 4'h3;
|
|
endcase
|
|
4'h2:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\state$next = 4'h4;
|
|
endcase
|
|
4'h3:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$81 )
|
|
1'h1:
|
|
/* empty */;
|
|
default:
|
|
\state$next = 4'h5;
|
|
endcase
|
|
endcase
|
|
4'h4:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$83 )
|
|
1'h1:
|
|
/* empty */;
|
|
default:
|
|
\state$next = 4'h6;
|
|
endcase
|
|
endcase
|
|
4'h5:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\state$next = 4'h7;
|
|
endcase
|
|
4'h6:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\state$next = 4'ha;
|
|
endcase
|
|
4'h7:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$85 )
|
|
1'h1:
|
|
/* empty */;
|
|
default:
|
|
\state$next = 4'h9;
|
|
endcase
|
|
endcase
|
|
4'h9:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$87 )
|
|
1'h1:
|
|
\state$next = 4'hb;
|
|
endcase
|
|
endcase
|
|
4'ha:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$89 )
|
|
1'h1:
|
|
\state$next = 4'h8;
|
|
endcase
|
|
endcase
|
|
4'h8:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
(* full_case = 32'd1 *)
|
|
casez (\$91 )
|
|
1'h1:
|
|
/* empty */;
|
|
default:
|
|
\state$next = 4'hb;
|
|
endcase
|
|
endcase
|
|
4'hb:
|
|
\state$next = 4'h0;
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\state$next = 4'h0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\s$56 = 35'h000000000;
|
|
casez (state)
|
|
4'h0:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez ({ is_read, is_write })
|
|
2'b?1:
|
|
/* empty */;
|
|
2'b1?:
|
|
\s$56 = \$93 ;
|
|
endcase
|
|
endcase
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\clock_counter$next = \$2 [7:0];
|
|
casez (rst)
|
|
1'h1:
|
|
\clock_counter$next = 8'h00;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\count$next = count;
|
|
casez (state)
|
|
4'h0:
|
|
/* empty */;
|
|
4'h1:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\count$next = 4'h3;
|
|
endcase
|
|
4'h2:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\count$next = 4'h3;
|
|
endcase
|
|
4'h3:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$97 )
|
|
1'h1:
|
|
\count$next = \$100 [3:0];
|
|
endcase
|
|
endcase
|
|
4'h4:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$102 )
|
|
1'h1:
|
|
\count$next = \$105 [3:0];
|
|
endcase
|
|
endcase
|
|
4'h5:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\count$next = 4'h7;
|
|
endcase
|
|
4'h6:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
\count$next = 4'h7;
|
|
endcase
|
|
4'h7:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$107 )
|
|
1'h1:
|
|
\count$next = \$110 [3:0];
|
|
endcase
|
|
endcase
|
|
4'h9:
|
|
/* empty */;
|
|
4'ha:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$112 )
|
|
1'h1:
|
|
\count$next = 4'h8;
|
|
endcase
|
|
endcase
|
|
4'h8:
|
|
casez (clock_strobe)
|
|
1'h1:
|
|
casez (\$114 )
|
|
1'h1:
|
|
\count$next = \$117 [3:0];
|
|
endcase
|
|
endcase
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\count$next = 4'h0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
clk_out = 1'h0;
|
|
casez (\$4 )
|
|
1'h1:
|
|
clk_out = clock_counter[0];
|
|
endcase
|
|
casez (\$6 )
|
|
1'h1:
|
|
clk_out = clock_counter[1];
|
|
endcase
|
|
casez (\$8 )
|
|
1'h1:
|
|
clk_out = clock_counter[2];
|
|
endcase
|
|
casez (\$10 )
|
|
1'h1:
|
|
clk_out = clock_counter[3];
|
|
endcase
|
|
casez (\$12 )
|
|
1'h1:
|
|
clk_out = clock_counter[4];
|
|
endcase
|
|
casez (\$14 )
|
|
1'h1:
|
|
clk_out = clock_counter[5];
|
|
endcase
|
|
casez (\$16 )
|
|
1'h1:
|
|
clk_out = clock_counter[6];
|
|
endcase
|
|
casez (\$18 )
|
|
1'h1:
|
|
clk_out = clock_counter[7];
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\config$next = \config ;
|
|
casez (mux_config_csr__w_stb)
|
|
1'h1:
|
|
\config$next = mux_config_csr__w_data;
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\config$next = 32'd1;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\status$next = status;
|
|
casez (mux_status_csr__w_stb)
|
|
1'h1:
|
|
\status$next = mux_status_csr__w_data;
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\status$next = 32'd0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
|
|
\prev_clk$next = clk_out;
|
|
casez (rst)
|
|
1'h1:
|
|
\prev_clk$next = 1'h0;
|
|
endcase
|
|
end
|
|
assign \$1 = \$2 ;
|
|
assign \$99 = \$100 ;
|
|
assign \$104 = \$105 ;
|
|
assign \$109 = \$110 ;
|
|
assign \$116 = \$117 ;
|
|
assign mux_status_csr__r_data = status;
|
|
assign mux_config_csr__r_data = \config ;
|
|
assign wb_ctrl__ack = bridge_wb__ack;
|
|
assign bridge_wb__we = wb_ctrl__we;
|
|
assign bridge_wb__stb = wb_ctrl__stb;
|
|
assign bridge_wb__cyc = wb_ctrl__cyc;
|
|
assign bridge_wb__sel = wb_ctrl__sel[0];
|
|
assign wb_ctrl__dat_r = bridge_wb__dat_r;
|
|
assign bridge_wb__dat_w = wb_ctrl__dat_w;
|
|
assign bridge_wb__adr = wb_ctrl__adr[0];
|
|
assign parity_out = \$119 ;
|
|
assign is_read = \$32 ;
|
|
assign is_write = \$26 ;
|
|
assign wb__dat_r = data;
|
|
assign clk_strobe = clock_strobe;
|
|
assign clock_strobe = \$22 ;
|
|
assign enabled = \config [3];
|
|
assign clock_divisor = \config [2:0];
|
|
assign \$53 = { wb__adr, 3'h0 };
|
|
assign \$94 = { wb__adr, 3'h0 };
|
|
endmodule
|
|
|
|
module \mux$1 (status_csr__r_data, config_csr__w_stb, config_csr__w_data, status_csr__w_stb, status_csr__w_data, rst, clk, csr__addr, csr__r_stb, csr__w_stb, csr__w_data, csr__r_data, config_csr__r_data);
|
|
reg \$auto$verilog_backend.cc:2083:dump_module$3 = 0;
|
|
wire [1:0] \$1 ;
|
|
wire [31:0] \$11 ;
|
|
wire [31:0] \$13 ;
|
|
wire [1:0] \$2 ;
|
|
wire [1:0] \$4 ;
|
|
wire [1:0] \$5 ;
|
|
wire [31:0] \$7 ;
|
|
wire [31:0] \$9 ;
|
|
input clk;
|
|
wire clk;
|
|
input [31:0] config_csr__r_data;
|
|
wire [31:0] config_csr__r_data;
|
|
reg config_csr__r_stb;
|
|
reg [31:0] config_csr__shadow = 32'd0;
|
|
reg [31:0] \config_csr__shadow$next ;
|
|
reg config_csr__shadow_en = 1'h0;
|
|
reg \config_csr__shadow_en$next ;
|
|
output [31:0] config_csr__w_data;
|
|
wire [31:0] config_csr__w_data;
|
|
output config_csr__w_stb;
|
|
reg config_csr__w_stb = 1'h0;
|
|
reg \config_csr__w_stb$next ;
|
|
input csr__addr;
|
|
wire csr__addr;
|
|
output [31:0] csr__r_data;
|
|
wire [31:0] csr__r_data;
|
|
input csr__r_stb;
|
|
wire csr__r_stb;
|
|
input [31:0] csr__w_data;
|
|
wire [31:0] csr__w_data;
|
|
input csr__w_stb;
|
|
wire csr__w_stb;
|
|
input rst;
|
|
wire rst;
|
|
input [31:0] status_csr__r_data;
|
|
wire [31:0] status_csr__r_data;
|
|
reg status_csr__r_stb;
|
|
reg [31:0] status_csr__shadow = 32'd0;
|
|
reg [31:0] \status_csr__shadow$next ;
|
|
reg status_csr__shadow_en = 1'h0;
|
|
reg \status_csr__shadow_en$next ;
|
|
output [31:0] status_csr__w_data;
|
|
wire [31:0] status_csr__w_data;
|
|
output status_csr__w_stb;
|
|
reg status_csr__w_stb = 1'h0;
|
|
reg \status_csr__w_stb$next ;
|
|
assign \$9 = 1'h0 | \$7 ;
|
|
assign \$11 = status_csr__shadow_en ? status_csr__shadow : 32'd0;
|
|
assign \$13 = \$9 | \$11 ;
|
|
always @(posedge clk)
|
|
config_csr__shadow_en <= \config_csr__shadow_en$next ;
|
|
always @(posedge clk)
|
|
config_csr__w_stb <= \config_csr__w_stb$next ;
|
|
always @(posedge clk)
|
|
config_csr__shadow <= \config_csr__shadow$next ;
|
|
always @(posedge clk)
|
|
status_csr__shadow_en <= \status_csr__shadow_en$next ;
|
|
always @(posedge clk)
|
|
status_csr__w_stb <= \status_csr__w_stb$next ;
|
|
always @(posedge clk)
|
|
status_csr__shadow <= \status_csr__shadow$next ;
|
|
assign \$7 = config_csr__shadow_en ? config_csr__shadow : 32'd0;
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
\config_csr__shadow_en$next = 1'h0;
|
|
casez (csr__addr)
|
|
1'h0:
|
|
\config_csr__shadow_en$next = \$2 [0];
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\config_csr__shadow_en$next = 1'h0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
\config_csr__w_stb$next = 1'h0;
|
|
casez (csr__addr)
|
|
1'h0:
|
|
\config_csr__w_stb$next = csr__w_stb;
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\config_csr__w_stb$next = 1'h0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
config_csr__r_stb = 1'h0;
|
|
casez (csr__addr)
|
|
1'h0:
|
|
config_csr__r_stb = csr__r_stb;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
\config_csr__shadow$next = config_csr__shadow;
|
|
casez (csr__addr)
|
|
1'h0:
|
|
begin
|
|
casez (csr__r_stb)
|
|
1'h1:
|
|
\config_csr__shadow$next = config_csr__r_data;
|
|
endcase
|
|
casez (csr__w_stb)
|
|
1'h1:
|
|
\config_csr__shadow$next = csr__w_data;
|
|
endcase
|
|
end
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\config_csr__shadow$next = 32'd0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
\status_csr__shadow_en$next = 1'h0;
|
|
casez (csr__addr)
|
|
1'h1:
|
|
\status_csr__shadow_en$next = \$5 [0];
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\status_csr__shadow_en$next = 1'h0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
\status_csr__w_stb$next = 1'h0;
|
|
casez (csr__addr)
|
|
1'h1:
|
|
\status_csr__w_stb$next = csr__w_stb;
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\status_csr__w_stb$next = 1'h0;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
status_csr__r_stb = 1'h0;
|
|
casez (csr__addr)
|
|
1'h1:
|
|
status_csr__r_stb = csr__r_stb;
|
|
endcase
|
|
end
|
|
always @* begin
|
|
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
|
|
\status_csr__shadow$next = status_csr__shadow;
|
|
casez (csr__addr)
|
|
1'h1:
|
|
begin
|
|
casez (csr__r_stb)
|
|
1'h1:
|
|
\status_csr__shadow$next = status_csr__r_data;
|
|
endcase
|
|
casez (csr__w_stb)
|
|
1'h1:
|
|
\status_csr__shadow$next = csr__w_data;
|
|
endcase
|
|
end
|
|
endcase
|
|
casez (rst)
|
|
1'h1:
|
|
\status_csr__shadow$next = 32'd0;
|
|
endcase
|
|
end
|
|
assign \$1 = \$2 ;
|
|
assign \$4 = \$5 ;
|
|
assign csr__r_data = \$13 ;
|
|
assign status_csr__w_data = status_csr__shadow;
|
|
assign config_csr__w_data = config_csr__shadow;
|
|
assign \$2 = { 1'h0, csr__r_stb };
|
|
assign \$5 = { 1'h0, csr__r_stb };
|
|
endmodule
|
|
|
|
module simplebus_host(bus_in, parity_in, bus_out, parity_out, enabled, wb_adr, wb_dat_w, wb_dat_r, wb_sel, wb_cyc, wb_stb, wb_we, wb_ack, wb_stall, wb_ctrl_adr, wb_ctrl_dat_w, wb_ctrl_dat_r, wb_ctrl_sel, wb_ctrl_cyc, wb_ctrl_stb, wb_ctrl_we
|
|
, wb_ctrl_ack, wb_ctrl_stall, clk, rst, clk_out);
|
|
input [7:0] bus_in;
|
|
wire [7:0] bus_in;
|
|
output [7:0] bus_out;
|
|
wire [7:0] bus_out;
|
|
input clk;
|
|
wire clk;
|
|
output clk_out;
|
|
wire clk_out;
|
|
output enabled;
|
|
wire enabled;
|
|
wire [7:0] mux_bus_in;
|
|
wire [7:0] mux_bus_out;
|
|
wire mux_clk_out;
|
|
wire mux_enabled;
|
|
wire mux_parity_out;
|
|
wire mux_wb__ack;
|
|
wire [28:0] mux_wb__adr;
|
|
wire mux_wb__cyc;
|
|
wire [63:0] mux_wb__dat_r;
|
|
wire [63:0] mux_wb__dat_w;
|
|
wire [7:0] mux_wb__sel;
|
|
wire mux_wb__stall;
|
|
wire mux_wb__stb;
|
|
wire mux_wb__we;
|
|
wire mux_wb_ctrl__ack;
|
|
wire [29:0] mux_wb_ctrl__adr;
|
|
wire mux_wb_ctrl__cyc;
|
|
wire [31:0] mux_wb_ctrl__dat_r;
|
|
wire [31:0] mux_wb_ctrl__dat_w;
|
|
wire [3:0] mux_wb_ctrl__sel;
|
|
wire mux_wb_ctrl__stb;
|
|
wire mux_wb_ctrl__we;
|
|
wire mux_wb_ctrl_stall;
|
|
input parity_in;
|
|
wire parity_in;
|
|
wire \parity_in$1 ;
|
|
output parity_out;
|
|
wire parity_out;
|
|
input rst;
|
|
wire rst;
|
|
output wb_ack;
|
|
wire wb_ack;
|
|
input [28:0] wb_adr;
|
|
wire [28:0] wb_adr;
|
|
output wb_ctrl_ack;
|
|
wire wb_ctrl_ack;
|
|
input [29:0] wb_ctrl_adr;
|
|
wire [29:0] wb_ctrl_adr;
|
|
input wb_ctrl_cyc;
|
|
wire wb_ctrl_cyc;
|
|
output [31:0] wb_ctrl_dat_r;
|
|
wire [31:0] wb_ctrl_dat_r;
|
|
input [31:0] wb_ctrl_dat_w;
|
|
wire [31:0] wb_ctrl_dat_w;
|
|
input [3:0] wb_ctrl_sel;
|
|
wire [3:0] wb_ctrl_sel;
|
|
output wb_ctrl_stall;
|
|
wire wb_ctrl_stall;
|
|
input wb_ctrl_stb;
|
|
wire wb_ctrl_stb;
|
|
input wb_ctrl_we;
|
|
wire wb_ctrl_we;
|
|
input wb_cyc;
|
|
wire wb_cyc;
|
|
output [63:0] wb_dat_r;
|
|
wire [63:0] wb_dat_r;
|
|
input [63:0] wb_dat_w;
|
|
wire [63:0] wb_dat_w;
|
|
input [7:0] wb_sel;
|
|
wire [7:0] wb_sel;
|
|
output wb_stall;
|
|
wire wb_stall;
|
|
input wb_stb;
|
|
wire wb_stb;
|
|
input wb_we;
|
|
wire wb_we;
|
|
mux mux (
|
|
.bus_in(mux_bus_in),
|
|
.bus_out(mux_bus_out),
|
|
.clk(clk),
|
|
.clk_out(mux_clk_out),
|
|
.enabled(mux_enabled),
|
|
.parity_out(mux_parity_out),
|
|
.rst(rst),
|
|
.wb__ack(mux_wb__ack),
|
|
.wb__adr(mux_wb__adr),
|
|
.wb__cyc(mux_wb__cyc),
|
|
.wb__dat_r(mux_wb__dat_r),
|
|
.wb__dat_w(mux_wb__dat_w),
|
|
.wb__sel(mux_wb__sel),
|
|
.wb__stall(mux_wb__stall),
|
|
.wb__stb(mux_wb__stb),
|
|
.wb__we(mux_wb__we),
|
|
.wb_ctrl__ack(mux_wb_ctrl__ack),
|
|
.wb_ctrl__adr(mux_wb_ctrl__adr),
|
|
.wb_ctrl__cyc(mux_wb_ctrl__cyc),
|
|
.wb_ctrl__dat_r(mux_wb_ctrl__dat_r),
|
|
.wb_ctrl__dat_w(mux_wb_ctrl__dat_w),
|
|
.wb_ctrl__sel(mux_wb_ctrl__sel),
|
|
.wb_ctrl__stb(mux_wb_ctrl__stb),
|
|
.wb_ctrl__we(mux_wb_ctrl__we),
|
|
.wb_ctrl_stall(mux_wb_ctrl_stall)
|
|
);
|
|
assign wb_ctrl_stall = mux_wb_ctrl_stall;
|
|
assign wb_ctrl_ack = mux_wb_ctrl__ack;
|
|
assign wb_ctrl_dat_r = mux_wb_ctrl__dat_r;
|
|
assign mux_wb_ctrl__we = wb_ctrl_we;
|
|
assign mux_wb_ctrl__stb = wb_ctrl_stb;
|
|
assign mux_wb_ctrl__cyc = wb_ctrl_cyc;
|
|
assign mux_wb_ctrl__sel = wb_ctrl_sel;
|
|
assign mux_wb_ctrl__dat_w = wb_ctrl_dat_w;
|
|
assign mux_wb_ctrl__adr = wb_ctrl_adr;
|
|
assign wb_stall = mux_wb__stall;
|
|
assign wb_ack = mux_wb__ack;
|
|
assign wb_dat_r = mux_wb__dat_r;
|
|
assign mux_wb__we = wb_we;
|
|
assign mux_wb__stb = wb_stb;
|
|
assign mux_wb__cyc = wb_cyc;
|
|
assign mux_wb__sel = wb_sel;
|
|
assign mux_wb__dat_w = wb_dat_w;
|
|
assign mux_wb__adr = wb_adr;
|
|
assign enabled = mux_enabled;
|
|
assign clk_out = mux_clk_out;
|
|
assign parity_out = mux_parity_out;
|
|
assign bus_out = mux_bus_out;
|
|
assign \parity_in$1 = parity_in;
|
|
assign mux_bus_in = bus_in;
|
|
endmodule
|