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25 lines
437 B
Verilog
25 lines
437 B
Verilog
module Microwatt_FP_DFFRFile (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input [6:0] R1, R2, R3, RW,
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input [63:0] DW,
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output [63:0] D1, D2, D3,
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input CLK,
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input WE
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);
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reg [63:0] registers[0:79];
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assign D1 = registers[R1];
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assign D2 = registers[R2];
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assign D3 = registers[R3];
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always @(posedge CLK) begin
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if (WE)
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registers[RW] <= DW;
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end
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endmodule
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