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41 lines
738 B
Verilog
41 lines
738 B
Verilog
module RAM32_1RW1R #(
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parameter BITS=5
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input CLK,
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input EN0,
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input [BITS-1:0] A0,
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input [7:0] WE0,
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input [63:0] Di0,
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output reg [63:0] Do0,
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input EN1,
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input [BITS-1:0] A1,
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output reg [63:0] Do1
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);
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reg [63:0] RAM[2**BITS-1:0];
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always @(posedge CLK) begin
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if (EN1)
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Do1 <= RAM[A1];
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end
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generate
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genvar i;
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for (i=0; i<8; i=i+1) begin: BYTE
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always @(posedge CLK) begin
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if (EN0) begin
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if (WE0[i])
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RAM[A0][i*8+7:i*8] <= Di0[i*8+7:i*8];
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end
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end
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end
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endgenerate
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endmodule
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