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64 lines
1.9 KiB
VHDL
64 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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entity main_bram is
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generic(
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WIDTH : natural := 64;
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HEIGHT_BITS : natural := 11;
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MEMORY_SIZE : natural := (8*1024);
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
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din : in std_logic_vector(WIDTH-1 downto 0);
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dout : out std_logic_vector(WIDTH-1 downto 0);
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sel : in std_logic_vector((WIDTH/8)-1 downto 0);
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re : in std_ulogic;
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we : in std_ulogic
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);
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end entity main_bram;
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architecture behaviour of main_bram is
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component RAM512 port (
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CLK : in std_ulogic;
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WE0 : in std_ulogic_vector(7 downto 0);
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EN0 : in std_ulogic;
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Di0 : in std_ulogic_vector(63 downto 0);
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Do0 : out std_ulogic_vector(63 downto 0);
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A0 : in std_ulogic_vector(8 downto 0)
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);
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end component;
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signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0);
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signal obuf : std_logic_vector(WIDTH-1 downto 0);
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begin
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assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE;
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-- Do we have a log2 round up issue here?
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assert (HEIGHT_BITS = 10) report "HEIGHT_BITS must be 10" severity FAILURE;
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assert (MEMORY_SIZE = 4096) report "MEMORY_SIZE must be 4096" severity FAILURE;
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sel_qual <= sel when we = '1' else (others => '0');
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memory_0 : RAM512
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port map (
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CLK => clk,
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WE0 => sel_qual(7 downto 0),
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EN0 => re or we,
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Di0 => din(63 downto 0),
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Do0 => obuf(63 downto 0),
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A0 => addr(8 downto 0)
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);
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-- The wishbone BRAM wrapper assumes a 1 cycle delay
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memory_read_buffer: process(clk)
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begin
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if rising_edge(clk) then
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dout <= obuf;
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end if;
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end process;
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end architecture behaviour;
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