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28 lines
778 B
VHDL
28 lines
778 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package params is
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type CACHE_PARAMS_T is record
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LINE_SIZE : natural;
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ICACHE_NUM_LINES : natural;
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ICACHE_NUM_WAYS : natural;
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ICACHE_TLB_SIZE : natural;
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DCACHE_NUM_LINES : natural;
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DCACHE_NUM_WAYS : natural;
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DCACHE_TLB_SET_SIZE : natural;
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DCACHE_TLB_NUM_WAYS : natural;
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end record;
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constant CACHE_PARAMS_DEFAULT : CACHE_PARAMS_T := (
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LINE_SIZE => 64,
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ICACHE_NUM_LINES => 64,
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ICACHE_NUM_WAYS => 2,
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ICACHE_TLB_SIZE => 64,
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DCACHE_NUM_LINES => 64,
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DCACHE_NUM_WAYS => 2,
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DCACHE_TLB_SET_SIZE => 64,
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DCACHE_TLB_NUM_WAYS => 2
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);
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end package;
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