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71 lines
2.0 KiB
Python
71 lines
2.0 KiB
Python
#!/usr/bin/python
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import sys
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import re
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module_regex = r'[a-zA-Z0-9_\.\\]+'
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# match:
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# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
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module_re = re.compile(r'module\s+(' + module_regex + r')\((.*)\);')
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# match:
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# dcache_64_2_2_2_2_12_0 dcache_0 (
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hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(')
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header1 = """\
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`ifdef USE_POWER_PINS
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vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2,
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`endif\
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"""
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header2 = """\
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`ifdef USE_POWER_PINS
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inout vdda1; // User area 1 3.3V supply
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inout vdda2; // User area 2 3.3V supply
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inout vssa1; // User area 1 analog ground
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inout vssa2; // User area 2 analog ground
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inout vccd1; // User area 1 1.8V supply
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inout vccd2; // User area 2 1.8v supply
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inout vssd1; // User area 1 digital ground
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inout vssd2; // User area 2 digital ground
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`endif\
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"""
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header3 = """\
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`ifdef USE_POWER_PINS
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.vdda1(vdda1), // User area 1 3.3V power
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.vdda2(vdda2), // User area 2 3.3V power
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.vssa1(vssa1), // User area 1 analog ground
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.vssa2(vssa2), // User area 2 analog ground
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.vccd1(vccd1), // User area 1 1.8V power
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.vccd2(vccd2), // User area 2 1.8V power
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.vssd1(vssd1), // User area 1 digital ground
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.vssd2(vssd2), // User area 2 digital ground
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`endif\
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"""
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if len(sys.argv) < 3:
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print("Usage: insert_power.py verilog.v module1 module2..")
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sys.exit(1);
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verilog_file = sys.argv[1]
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modules = sys.argv[2:]
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with open(sys.argv[1]) as f:
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for line in f:
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m = module_re.match(line)
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m2 = hookup_re.match(line)
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if m and m.group(1) in modules:
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module_name = m.group(1)
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module_args = m.group(2)
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print('module %s(' % module_name)
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print(header1)
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print(' %s);' % module_args)
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print(header2)
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elif m2 and m2.group(1) in modules:
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print(line, end='')
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print(header3)
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else:
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print(line, end='')
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