diff --git a/specification/app_a.xml b/specification/app_a.xml index 52cf4e7..8b2b013 100644 --- a/specification/app_a.xml +++ b/specification/app_a.xml @@ -35,11 +35,11 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> supported range leads to implementation-defined behavior. It is recommended that compilers generate a warning or error for out-of-range literals. - Vectors may be constructed from scalar values with a vector + Vectors may be constructed from scalar values with a vector constructor. For example: (vector type){e1, e2, ..., en}. The values specified for each vector element can be either a compile-time constant or a runtime expression. - Floating-point vector built-in operators are controlled by the + Floating-point vector built-in operators are controlled by the rounding mode set for floating-point operations unless otherwise specified.
@@ -321,7 +321,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_abs (vector float); - + VEC_ABSD (ARG1, ARG2) POWER ISA 3.0 @@ -335,7 +335,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> arithmetic. - + POWER ISA 3.0 @@ -344,7 +344,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char); - + POWER ISA 3.0 @@ -353,7 +353,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int); - + POWER ISA 3.0 @@ -812,14 +812,14 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> - Phased in. + Phased in. This optional function is being phased in, and it might not be available on all implementations. - Phased-in interfaces are optional + Phased-in interfaces are optional for the current generation of compliant systems. - + vector bool long long vec_and (vector bool long long, vector bool long long); @@ -1102,11 +1102,11 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Purpose: - Gathers up to 16 1-bit values from a quadword or from each + Gathers up to 16 1-bit values from a quadword or from each doubleword element in the specified order, zeroing other bits. Result value: - When the type of ARG1 is vector + When the type of ARG1 is vector unsigned char or vector unsigned __int128: @@ -1125,9 +1125,9 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> All other bits are zeroed. - When the type of ARG1 is vector + When the type of ARG1 is vector unsigned long long: - + For each doubleword element i (0 ≤ i < 2) of ARG1, regardless of the input operand type specified for @@ -1168,7 +1168,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned char); - + Phased in. @@ -1178,7 +1178,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> __int128, vector unsigned char); - + POWER ISA 3.0 Phased in. @@ -1278,7 +1278,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Otherwise, the value of each bit is 0. - + @@ -1305,7 +1305,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char); - + @@ -1332,7 +1332,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int); - + @@ -1359,7 +1359,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned long long); - + @@ -1843,7 +1843,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Otherwise, the value of each bit is 0. - + @@ -1870,7 +1870,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char); - + @@ -1897,7 +1897,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int); - + @@ -1924,7 +1924,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned long long); - + @@ -1969,7 +1969,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> float); - + VEC_CMPNEZ (ARG1, ARG2) POWER ISA 3.0 @@ -1986,7 +1986,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> element is 0. Otherwise, the value of each bit is 0. - + POWER ISA 3.0 @@ -1995,7 +1995,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed char); - + POWER ISA 3.0 @@ -2004,7 +2004,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char); - + POWER ISA 3.0 @@ -2013,7 +2013,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed int); - + POWER ISA 3.0 @@ -2022,7 +2022,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int); - + POWER ISA 3.0 @@ -2031,7 +2031,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed short); - + POWER ISA 3.0 @@ -2131,7 +2131,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short); - + VEC_CNTLZ_LSBB (ARG1) POWER ISA 3.0 @@ -2147,7 +2147,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> least-significant bit of 0. - + POWER ISA 3.0 @@ -2155,7 +2155,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed int vec_cntlz_lsbb (vector signed char); - + POWER ISA 3.0 @@ -2163,7 +2163,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed int vec_cntlz_lsbb (vector unsigned char); - + VEC_CNTTZ (ARG1) POWER ISA 3.0 @@ -2179,7 +2179,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> ARG1. - + POWER ISA 3.0 @@ -2187,7 +2187,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed char vec_cnttz (vector signed char); - + POWER ISA 3.0 @@ -2196,7 +2196,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char); - + POWER ISA 3.0 @@ -2204,7 +2204,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed int vec_cnttz (vector signed int); - + POWER ISA 3.0 @@ -2212,7 +2212,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned int vec_cnttz (vector unsigned int); - + POWER ISA 3.0 @@ -2221,7 +2221,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> long); - + POWER ISA 3.0 @@ -2230,7 +2230,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> long); - + POWER ISA 3.0 @@ -2238,7 +2238,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed short vec_cnttz (vector signed short); - + POWER ISA 3.0 @@ -2247,7 +2247,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short); - + VEC_CNTTZ_LSBB (ARG1) POWER ISA 3.0 @@ -2263,7 +2263,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> least-significant bit of 0. - + POWER ISA 3.0 @@ -2271,7 +2271,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed int vec_cnttz_lsbb (vector signed char); - + POWER ISA 3.0 @@ -2324,7 +2324,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Result value: The value of each element of the result is the closest floating-point - approximationestimate + approximation of the value of the corresponding element of ARG1 divided by 2 to the power of ARG2, which should be in the range 0–31. @@ -2356,7 +2356,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Converts a real vector into a vector signed int. Result value: The value of each element of the result is the saturated - signed-integer value, + signed-integer value, truncated towards zero, obtained by multiplying the corresponding element of ARG1 by 2 to the power of ARG2, which should be in the range 0–31. @@ -2379,7 +2379,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Converts a real vector into a vector unsigned int. Result value: The value of each element of the result is the saturated - unsigned-integer value, + unsigned-integer value, truncated towards zero, obtained by multiplying the corresponding element of ARG1 by 2 to the power of ARG2, which should be in the range 0–31. @@ -2410,7 +2410,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> element of ARG2. - + @@ -2419,7 +2419,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed long long); - + @@ -2450,10 +2450,10 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> VEC_DOUBLE (ARG1) - Purpose: + Purpose: Converts a vector of long integers into a vector of double-precision numbers. - Result value: + Result value: Target elements are computed by converting the respective input elements. @@ -2519,9 +2519,9 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Purpose: Converts - an input vectora vector of integers + an input vector to a vector of double-precision - floating-point numbers. + floating-point numbers. Result value: Target elements 0 and 1 are set to the converted values of source elements 0 and 1. @@ -2558,9 +2558,9 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Purpose: Converts - an input vectora vector of integers + an input vector to a vector of double-precision - floating-point numbers. + floating-point numbers. Result value: Target elements 0 and 1 are set to the converted values of source elements 2 and 3. @@ -2680,7 +2680,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed int vec_eqv (vector signed int, vector - signed + signed int); @@ -2735,7 +2735,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed short vec_eqv (vector signed short, vector - signed short); + signed short); @@ -2925,7 +2925,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> float vec_extract (vector float, signed int); - + POWER ISA 3.0 Phased in. @@ -2935,7 +2935,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> _Float16 vec_extract (vector _Float16, signed int); - + VEC_EXTRACT_EXP (ARG1) POWER ISA 3.0 @@ -2953,7 +2953,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> 754, without further processing. - + POWER ISA 3.0 @@ -2962,7 +2962,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> double); - + POWER ISA 3.0 @@ -2970,7 +2970,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned int vec_extract_exp (vector float); - + VEC_EXTRACT_FP32_ FROM_SHORTH (ARG1) POWER ISA 3.0 @@ -2988,7 +2988,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> single-precision IEEE numbers. - + POWER ISA 3.0 @@ -2997,7 +2997,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short); - + VEC_EXTRACT_FP32_ FROM_SHORTL (ARG1) POWER ISA 3.0 @@ -3015,7 +3015,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> single-precision IEEE numbers. - + POWER ISA 3.0 @@ -3024,7 +3024,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short); - + VEC_EXTRACT_SIG (ARG1) POWER ISA 3.0 @@ -3044,7 +3044,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> exponent. - + POWER ISA 3.0 @@ -3053,7 +3053,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> double); - + POWER ISA 3.0 @@ -3061,7 +3061,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned int vec_extract_sig (vector float); - + VEC_EXTRACT4B (ARG1, ARG2) POWER ISA 3.0 @@ -3076,7 +3076,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> (0–12) of the word to be extracted. - + POWER ISA 3.0 @@ -3085,7 +3085,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char, const int); - + VEC_FIRST_MATCH_INDEX (ARG1, ARG2) POWER ISA 3.0 @@ -3101,7 +3101,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> an element count in the vector argument. - + POWER ISA 3.0 @@ -3110,7 +3110,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed char); - + POWER ISA 3.0 @@ -3119,7 +3119,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned char); - + POWER ISA 3.0 @@ -3128,7 +3128,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed int); - + POWER ISA 3.0 @@ -3137,7 +3137,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned int); - + POWER ISA 3.0 @@ -3146,7 +3146,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed short); - + POWER ISA 3.0 @@ -3155,7 +3155,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned short); - + VEC_FIRST_MATCH_OR_EOS_ INDEX (ARG1, ARG2) POWER ISA 3.0 @@ -3172,7 +3172,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> element count in the vector argument. - + POWER ISA 3.0 @@ -3181,7 +3181,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char, vector signed char); - + POWER ISA 3.0 @@ -3190,7 +3190,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char, vector unsigned char); - + POWER ISA 3.0 @@ -3199,7 +3199,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int, vector signed int); - + POWER ISA 3.0 @@ -3208,7 +3208,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int, vector unsigned int); - + POWER ISA 3.0 @@ -3217,7 +3217,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short, vector signed short); - + POWER ISA 3.0 @@ -3226,7 +3226,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short, vector unsigned short); - + VEC_FIRST_MISMATCH_INDEX (ARG1, ARG2) POWER ISA 3.0 @@ -3242,7 +3242,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> characters as an element count in the vector argument. - + POWER ISA 3.0 @@ -3251,7 +3251,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed char); - + POWER ISA 3.0 @@ -3260,7 +3260,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char, vector unsigned char); - + POWER ISA 3.0 @@ -3269,7 +3269,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed int); - + POWER ISA 3.0 @@ -3278,7 +3278,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned int); - + POWER ISA 3.0 @@ -3287,7 +3287,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed short); - + POWER ISA 3.0 @@ -3296,7 +3296,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short, vector unsigned short); - + VEC_FIRST_MISMATCH_OR_ EOS_INDEX (ARG1, ARG2) POWER ISA 3.0 @@ -3313,7 +3313,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> element count in the vector argument. - + POWER ISA 3.0 @@ -3322,7 +3322,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char, vector signed char); - + POWER ISA 3.0 @@ -3331,7 +3331,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char, vector unsigned char); - + POWER ISA 3.0 @@ -3340,7 +3340,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int, vector signed int); - + POWER ISA 3.0 @@ -3349,7 +3349,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int, vector unsigned int); - + POWER ISA 3.0 @@ -3358,7 +3358,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> short, vector signed short); - + POWER ISA 3.0 @@ -3386,7 +3386,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> - vector float + vector float vec_float (vector signed int); @@ -3395,7 +3395,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> - vector float + vector float vec_float (vector unsigned int); @@ -3406,7 +3406,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Purpose: Converts - an input vectora vector of integers + an input vector to a vector of single-precision numbers. Result value: Target elements are obtained by converting the source @@ -3486,7 +3486,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_floate (vector double); - + VEC_FLOATH (ARG2) POWER ISA 3.0 @@ -3502,7 +3502,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> of source elements 0 through 3, respectively. - + POWER ISA 3.0 @@ -3510,7 +3510,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_floath (vector _Float16); - + VEC_FLOATL (ARG2) POWER ISA 3.0 @@ -3526,7 +3526,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> of source elements 4 through 7, respectively. - + POWER ISA 3.0 @@ -3703,7 +3703,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed short vec_insert (signed short, vector signed - short,. + short, signed int); @@ -3734,7 +3734,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int); - + POWER ISA 3.0 Phased in. @@ -3745,7 +3745,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed int); - + VEC_INSERT_EXP (ARG1, ARG2) POWER ISA 3.0 @@ -3765,7 +3765,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> further processing. - + POWER ISA 3.0 @@ -3774,7 +3774,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned long long); - + POWER ISA 3.0 @@ -3783,7 +3783,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned long long); - + POWER ISA 3.0 @@ -3792,7 +3792,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int); - + POWER ISA 3.0 @@ -3801,7 +3801,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int); - + VEC_INSERT4B (ARG1, ARG2, ARG3) POWER ISA 3.0 @@ -3815,7 +3815,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> ARG2 at the byte position (0–12) specified by ARG3. - + POWER ISA 3.0 @@ -3824,7 +3824,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned char, const int); - + POWER ISA 3.0 @@ -4300,7 +4300,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> float); - + POWER ISA 3.0 Phased in. @@ -4464,7 +4464,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> float); - + POWER ISA 3.0 Phased in. @@ -5688,22 +5688,6 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned short); - - - - - - vector double vec_or (vector bool long long, vector double); - - - - - - - - vector double vec_or (vector double, vector bool long long); - - @@ -5712,22 +5696,6 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector double vec_or (vector double, vector double); - - - - - - vector float vec_or (vector bool int, vector float); - - - - - - - - vector float vec_or (vector float, vector bool int); - - @@ -5883,11 +5851,11 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Packs information from each element of two vectors into the result vector. Result value: - For integer types, theThe + For integer types, the value of each element of the result vector is taken from the low-order half of the corresponding element of the result of concatenating ARG1 and ARG2. - For floating-point types, the value of each element of the + For floating-point types, the value of each element of the result vector is the corresponding element of the result of concatenating ARG1 and ARG2, rounded to the result type. @@ -5982,7 +5950,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> double); - + POWER ISA 3.0 Phased in. @@ -5993,7 +5961,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> float); - + VEC_PACK_TO_SHORT_FP32 (ARG1, ARG2) POWER ISA 3.0 @@ -6009,7 +5977,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> half-precision. - + POWER ISA 3.0 @@ -6190,7 +6158,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned int); - + VEC_PARITY_LSBB (ARG1) POWER ISA 3.0 @@ -6204,7 +6172,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> the low-order bit of each of the bytes in that element. - + POWER ISA 3.0 @@ -6213,7 +6181,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int); - + POWER ISA 3.0 @@ -6222,7 +6190,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int); - + POWER ISA 3.0 @@ -6231,7 +6199,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed __int128); - + POWER ISA 3.0 @@ -6240,7 +6208,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned __int128); - + POWER ISA 3.0 @@ -6249,7 +6217,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> long long); - + POWER ISA 3.0 @@ -6409,7 +6377,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char); - + POWER ISA 3.0 Phased in. @@ -6768,7 +6736,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_revb (vector float); - + POWER ISA 3.0 Phased in. @@ -6907,7 +6875,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_reve (vector float); - + POWER ISA 3.0 Phased in. @@ -7037,7 +7005,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned short); - + VEC_RLMI (ARG1, ARG2, ARG3) POWER ISA 3.0 @@ -7053,7 +7021,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> bits 27:31 contain the shift count. - + POWER ISA 3.0 @@ -7062,7 +7030,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int, vector unsigned int); - + POWER ISA 3.0 @@ -7072,7 +7040,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> long); - + VEC_RLNM (ARG1, ARG2, ARG3) POWER ISA 3.0 @@ -7091,7 +7059,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> other bytes zero. - + POWER ISA 3.0 @@ -7100,7 +7068,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int, vector unsigned int); - + POWER ISA 3.0 @@ -7361,7 +7329,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed long long, vector bool long long); - + Phased in. @@ -7381,7 +7349,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> long, vector unsigned long long, vector bool long long); - + Phased in. @@ -7482,7 +7450,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned int); - + POWER ISA 3.0 Phased in. @@ -7493,7 +7461,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector bool short); - + POWER ISA 3.0 Phased in. @@ -7514,7 +7482,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed integers. Result value: Target elements are obtained by - truncatingconverting + truncating the respective source elements to signed integers. @@ -7545,7 +7513,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed integers. Result value: Target elements are obtained by - truncatingconverting + truncating the source elements to the signed integers as follows: @@ -7577,7 +7545,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> integers. Result value: The even target elements are obtained by - truncatingconverting + truncating the source elements to signed integers as follows: Target elements 0 and 2 contain the converted values of the @@ -7602,7 +7570,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> integers. Result value: The odd target elements are obtained by - truncatingconverting + truncating the source elements to signed integers as follows: Target elements 1 and 3 contain the converted values of the @@ -7710,7 +7678,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Purpose: - Left shifts a double vector (that is, two concatenated + Left shifts a double vector (that is, two concatenated vectors) by a given number of bytes. For vec_sld being performed on the vector bool and floating-point types, the result is undefined, when the specified shift count is not a multiple of @@ -7841,7 +7809,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned short, const int); - + Phased in. @@ -7958,7 +7926,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Purpose: Left shifts a vector by a given number of bits. Result value: - The result is the contents of ARG1, shifted left by the + The result is the contents of ARG1, shifted left by the number of bits specified by the three least-significant bits of ARG2. The bits that are shifted out are replaced by zeros. The shift count must have been replicated into all bytes of the shift @@ -8001,7 +7969,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char); - + Phased in. @@ -8011,7 +7979,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned char); - + Phased in. @@ -8246,7 +8214,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char); - + VEC_SLV (ARG1, ARG2) POWER ISA 3.0 @@ -8269,7 +8237,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Xi. - + POWER ISA 3.0 @@ -8427,7 +8395,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_splat (vector float, const int); - + POWER ISA 3.0 Phased in. @@ -8674,7 +8642,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_splats (float); - + POWER ISA 3.0 Phased in. @@ -8901,7 +8869,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> The result is the contents of ARG1, shifted right by the number of bits specified by the 3 least-significant bits of ARG2. The bits that are shifted out are replaced by zeros. - The shift + The shift count must have been replicated into all bytes of the shift count specification. @@ -8942,7 +8910,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned char); - + Phased in. @@ -8952,7 +8920,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned char); - + Phased in. @@ -9187,7 +9155,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> char); - + VEC_SRV (ARG1, ARG2) POWER ISA 3.0 @@ -9214,7 +9182,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Si. - + POWER ISA 3.0 @@ -9671,7 +9639,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed int); - + VEC_TEST_DATA_CLASS (ARG1, ARG2) POWER ISA 3.0 @@ -9688,7 +9656,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> . - + POWER ISA 3.0 @@ -9697,7 +9665,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> int); - + POWER ISA 3.0 @@ -9748,7 +9716,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> If ARG1 is an integer vector, the value of each element of the result is the value of the corresponding element of the most-significant half of ARG1. - If ARG1 is a floating-point vector, the value of each + If ARG1 is a floating-point vector, the value of each element of the result is the value of the corresponding element of the most-significant half of ARG1, widened to the result precision. @@ -9846,7 +9814,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector double vec_unpackh (vector float); - + POWER ISA 3.0 Phased in. @@ -9868,7 +9836,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> If ARG1 is an integer vector, the value of each element of the result is the value of the corresponding element of the least-significant half of ARG1. - If ARG1 is a floating-point vector, the value of each + If ARG1 is a floating-point vector, the value of each element of the result is the value of the corresponding element of the least-significant half of ARG, widened to the result precision. @@ -9923,7 +9891,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector unsigned int vec_unpackl (vector pixel); - + @@ -9966,7 +9934,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector double vec_unpackl (vector float); - + POWER ISA 3.0 Phased in. @@ -9986,7 +9954,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> of unsigned integers. Result value: Target elements are obtained by - truncatingconverting + truncating the respective source elements to unsigned integers. @@ -10018,7 +9986,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> of unsigned integers. Result value: Target elements are obtained by - truncatingconverting + truncating the source elements to the unsigned integers as follows: @@ -10050,7 +10018,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> integers. Result value: The even target elements are obtained by - truncatingconverting + truncating the source elements to unsigned integers as follows: Target elements 0 and 2 contain the converted values of the @@ -10075,7 +10043,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> integers. Result value: The odd target elements are obtained by - truncatingconverting + truncating the source elements to unsigned integers as follows: Target elements 1 and 3 contain the converted values of the @@ -10215,7 +10183,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_xl (signed long long, float *); - + POWER ISA 3.0 Phased in. @@ -10353,7 +10321,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_xl_be (signed long long, float *); - + POWER ISA 3.0 Phased in. @@ -10363,7 +10331,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector _Float16 vec_xl_be (signed long long, _Float16 *); - + VEC_XL_LEN (ARG1, ARG2) POWER ISA 3.0 @@ -10384,7 +10352,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> multiple of the vector element size. - + POWER ISA 3.0 @@ -10393,7 +10361,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10402,7 +10370,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10410,7 +10378,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector signed int vec_xl_len (signed int *, size_t); - + POWER ISA 3.0 @@ -10419,7 +10387,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10428,7 +10396,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10437,7 +10405,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10446,7 +10414,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10455,7 +10423,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10464,7 +10432,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10473,7 +10441,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10481,7 +10449,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector double vec_xl_len (double *, size_t); - + POWER ISA 3.0 @@ -10489,7 +10457,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector float vec_xl_len (float *, size_t); - + POWER ISA 3.0 @@ -10497,7 +10465,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector _Float16 vec_xl_len (_Float16 *, size_t); - + VEC_XL_LEN_R (ARG1, ARG2) POWER ISA 3.0 @@ -10521,7 +10489,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> multiple of the vector element size. - + POWER ISA 3.0 @@ -10794,7 +10762,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> void vec_xst (vector float, signed long long, float *); - + POWER ISA 3.0 Phased in. @@ -10934,7 +10902,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> void vec_xst_be (vector float, signed long long, float *); - + POWER ISA 3.0 Phased in. @@ -10945,7 +10913,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> *); - + VEC_XST_LEN (ARG1, ARG2, ARG3) POWER ISA 3.0 @@ -10967,7 +10935,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> multiple of the vector element size. - + POWER ISA 3.0 @@ -10976,7 +10944,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10985,7 +10953,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -10994,7 +10962,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -11003,7 +10971,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -11012,7 +10980,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> *, size_t); - + POWER ISA 3.0 @@ -11021,7 +10989,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> __int128 *, size_t); - + POWER ISA 3.0 @@ -11030,7 +10998,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> *, size_t); - + POWER ISA 3.0 @@ -11039,7 +11007,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> long *, size_t); - + POWER ISA 3.0 @@ -11048,7 +11016,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -11057,7 +11025,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + POWER ISA 3.0 @@ -11065,7 +11033,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> void vec_xst_len (vector double, double *, size_t); - + POWER ISA 3.0 @@ -11073,7 +11041,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> void vec_xst_len (vector float, float *, size_t); - + POWER ISA 3.0 @@ -11082,7 +11050,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> size_t); - + VEC_XST_LEN_R (ARG1, ARG2, ARG3) POWER ISA 3.0 @@ -11102,7 +11070,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> multiple of the vector element size. - + POWER ISA 3.0 @@ -11691,7 +11659,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Phased in.This optional function is being phased in, and it might not be available on all implementations. - Phased-in interfaces are optional for the current generation of + Phased-in interfaces are optional for the current generation of compliant systems. @@ -13464,7 +13432,7 @@ vec_xst_be(result,0, &le_result);
-
+
PowerSIMD API Named Constants This section defines constants for use by the PowerSIMD vector programming operators. They may be defined either as macros or as named @@ -15279,7 +15247,7 @@ vec_xst_be(result,0, &le_result); vector unsigned int vec_vpopcntw (vector - unsigned + unsigned int); @@ -16186,7 +16154,7 @@ vec_xst_be(result,0, &le_result); vector signed long long vec_vupklsw (vector - signed + signed int); @@ -16196,7 +16164,7 @@ vec_xst_be(result,0, &le_result); vector unsigned long long vec_vupklsw (vector - unsigned + unsigned int); @@ -17033,7 +17001,7 @@ vec_xst_be(result,0, &le_result); vector bool short); - + VEC_INSERT (ARG1, ARG2, ARG3) @@ -17049,7 +17017,7 @@ vec_xst_be(result,0, &le_result); the vector to determine the element position. - + @@ -17058,7 +17026,7 @@ vec_xst_be(result,0, &le_result); char, signed int); - + @@ -17067,7 +17035,7 @@ vec_xst_be(result,0, &le_result); signed int); - + @@ -17076,7 +17044,7 @@ vec_xst_be(result,0, &le_result); vector bool long long, signed int); - + @@ -17503,7 +17471,7 @@ vec_xst_be(result,0, &le_result); vector bool short); - + VEC_MLADD (ARG1, ARG2, ARG3) @@ -17520,7 +17488,7 @@ vec_xst_be(result,0, &le_result); using modular arithmetic. - + @@ -17529,7 +17497,7 @@ vec_xst_be(result,0, &le_result); signed short, vector signed short); - + @@ -17538,7 +17506,7 @@ vec_xst_be(result,0, &le_result); unsigned short, vector unsigned short); - + @@ -17547,7 +17515,7 @@ vec_xst_be(result,0, &le_result); vector signed short, vector signed short); - + @@ -17913,7 +17881,7 @@ vec_xst_be(result,0, &le_result); bool short); - + @@ -17922,7 +17890,7 @@ vec_xst_be(result,0, &le_result); double); - + @@ -17931,7 +17899,7 @@ vec_xst_be(result,0, &le_result); long); - + @@ -17939,7 +17907,7 @@ vec_xst_be(result,0, &le_result); vector float vec_or (vector bool int, vector float); - + @@ -18104,7 +18072,7 @@ vec_xst_be(result,0, &le_result); vector bool short); - + @@ -18113,7 +18081,7 @@ vec_xst_be(result,0, &le_result); double); - + @@ -18122,7 +18090,7 @@ vec_xst_be(result,0, &le_result); long); - + @@ -18131,7 +18099,7 @@ vec_xst_be(result,0, &le_result); float); - + @@ -18140,7 +18108,7 @@ vec_xst_be(result,0, &le_result); int); - + VEC_SEL (ARG1, ARG2, ARG3) @@ -18155,7 +18123,7 @@ vec_xst_be(result,0, &le_result); corresponding bit of ARG2. - + @@ -18164,7 +18132,7 @@ vec_xst_be(result,0, &le_result); unsigned long long); - + VEC_SLL (ARG1, ARG2) @@ -18179,7 +18147,7 @@ vec_xst_be(result,0, &le_result); count specification. - + @@ -18188,7 +18156,7 @@ vec_xst_be(result,0, &le_result); char); - + @@ -18197,7 +18165,7 @@ vec_xst_be(result,0, &le_result); int); - + @@ -18206,7 +18174,7 @@ vec_xst_be(result,0, &le_result); short); - + @@ -18215,7 +18183,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18224,7 +18192,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18233,7 +18201,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18242,7 +18210,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18251,7 +18219,7 @@ vec_xst_be(result,0, &le_result); char); - + @@ -18260,7 +18228,7 @@ vec_xst_be(result,0, &le_result); int); - + @@ -18269,7 +18237,7 @@ vec_xst_be(result,0, &le_result); short); - + @@ -18278,7 +18246,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18287,7 +18255,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18296,7 +18264,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18305,7 +18273,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18314,7 +18282,7 @@ vec_xst_be(result,0, &le_result); vector unsigned char); - + @@ -18323,7 +18291,7 @@ vec_xst_be(result,0, &le_result); vector unsigned long long); - + @@ -18332,7 +18300,7 @@ vec_xst_be(result,0, &le_result); vector unsigned short); - + @@ -18341,7 +18309,7 @@ vec_xst_be(result,0, &le_result); vector unsigned long long); - + @@ -18350,7 +18318,7 @@ vec_xst_be(result,0, &le_result); vector unsigned short); - + @@ -18359,7 +18327,7 @@ vec_xst_be(result,0, &le_result); long, vector unsigned long long); - + @@ -18368,7 +18336,7 @@ vec_xst_be(result,0, &le_result); long, vector unsigned short); - + @@ -18377,7 +18345,7 @@ vec_xst_be(result,0, &le_result); int); - + @@ -18386,7 +18354,7 @@ vec_xst_be(result,0, &le_result); short); - + @@ -18395,7 +18363,7 @@ vec_xst_be(result,0, &le_result); unsigned char); - + @@ -18404,7 +18372,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18413,7 +18381,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18422,7 +18390,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18431,7 +18399,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18440,7 +18408,7 @@ vec_xst_be(result,0, &le_result); vector unsigned int); - + @@ -18460,7 +18428,7 @@ vec_xst_be(result,0, &le_result); The result is the contents of ARG1, shifted right by the number of bits specified by the 3 least-significant bits of ARG2. The bits that are shifted out are replaced by zeros. - The shift + The shift count must have been replicated into all bytes of the shift count specification. @@ -18492,7 +18460,7 @@ vec_xst_be(result,0, &le_result); short); - + @@ -18501,7 +18469,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18510,7 +18478,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18519,7 +18487,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18555,7 +18523,7 @@ vec_xst_be(result,0, &le_result); short); - + @@ -18564,7 +18532,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18573,7 +18541,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18582,7 +18550,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18591,7 +18559,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18600,7 +18568,7 @@ vec_xst_be(result,0, &le_result); vector unsigned long long); - + @@ -18609,7 +18577,7 @@ vec_xst_be(result,0, &le_result); vector unsigned short); - + @@ -18618,7 +18586,7 @@ vec_xst_be(result,0, &le_result); long, vector unsigned long long); - + @@ -18627,7 +18595,7 @@ vec_xst_be(result,0, &le_result); long, vector unsigned short); - + @@ -18636,7 +18604,7 @@ vec_xst_be(result,0, &le_result); int); - + @@ -18672,7 +18640,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18681,7 +18649,7 @@ vec_xst_be(result,0, &le_result); unsigned int); - + @@ -18690,7 +18658,7 @@ vec_xst_be(result,0, &le_result); unsigned short); - + @@ -18699,7 +18667,7 @@ vec_xst_be(result,0, &le_result); vector unsigned int); - + @@ -19231,7 +19199,7 @@ vec_xst_be(result,0, &le_result); vector bool short); - + @@ -19240,7 +19208,7 @@ vec_xst_be(result,0, &le_result); double); - + @@ -19249,7 +19217,7 @@ vec_xst_be(result,0, &le_result); long); - + @@ -19258,7 +19226,7 @@ vec_xst_be(result,0, &le_result); float); - + diff --git a/specification/app_b.xml b/specification/app_b.xml index 0d3770c..7cff499 100644 --- a/specification/app_b.xml +++ b/specification/app_b.xml @@ -12,7 +12,7 @@ --> +xml:id="dbdoclet.50655245_pgfId-1450875"> Binary-Coded Decimal Built-In Functions Binary-coded decimal (BCD) values are compressed; each decimal digit and sign bit occupies 4 bits. Digits are ordered with the most significant diff --git a/specification/app_glossary.xml b/specification/app_glossary.xml index c4d9274..2c4ac47 100644 --- a/specification/app_glossary.xml +++ b/specification/app_glossary.xml @@ -28,7 +28,7 @@ xml:id="dbdoclet.50655246_33489"> Application binary interface - + AES @@ -36,7 +36,7 @@ xml:id="dbdoclet.50655246_33489"> Advanced Encryption Standard - + API @@ -44,7 +44,7 @@ xml:id="dbdoclet.50655246_33489"> Application programming interface - + ASCII @@ -52,7 +52,7 @@ xml:id="dbdoclet.50655246_33489"> American Standard Code for Information Interchange - + BCD @@ -68,7 +68,7 @@ xml:id="dbdoclet.50655246_33489"> Big-endian - + COBOL @@ -84,7 +84,7 @@ xml:id="dbdoclet.50655246_33489"> Condition Register - + CTR @@ -92,7 +92,7 @@ xml:id="dbdoclet.50655246_33489"> Count Register - + DFP @@ -108,7 +108,7 @@ xml:id="dbdoclet.50655246_33489"> Double precision - + DRN @@ -117,7 +117,7 @@ xml:id="dbdoclet.50655246_33489"> register. - + DSCR @@ -149,7 +149,7 @@ xml:id="dbdoclet.50655246_33489"> Debug with arbitrary record format - + EA @@ -165,7 +165,7 @@ xml:id="dbdoclet.50655246_33489"> Executable and Linking Format - + EOS @@ -189,7 +189,7 @@ xml:id="dbdoclet.50655246_33489"> Floating-Point Status and Control Register - + GCC @@ -197,7 +197,7 @@ xml:id="dbdoclet.50655246_33489"> GNU Compiler Collection - + GEP @@ -221,7 +221,7 @@ xml:id="dbdoclet.50655246_33489"> General Purpose Register - + HTM @@ -293,7 +293,7 @@ xml:id="dbdoclet.50655246_33489"> Little-endian - + LEP @@ -317,7 +317,7 @@ xml:id="dbdoclet.50655246_33489"> Least-significant byte, least-significant bit - + MB @@ -325,7 +325,7 @@ xml:id="dbdoclet.50655246_33489"> Megabyte - + MSB @@ -333,7 +333,7 @@ xml:id="dbdoclet.50655246_33489"> Most-significant byte, most-significant bit - + MSR @@ -341,7 +341,7 @@ xml:id="dbdoclet.50655246_33489"> Machine State Register - + N/A @@ -357,7 +357,7 @@ xml:id="dbdoclet.50655246_33489"> Not-a-Number - + NOP @@ -366,7 +366,7 @@ xml:id="dbdoclet.50655246_33489"> affect registers or generate bus activity. - + NOR @@ -374,7 +374,7 @@ xml:id="dbdoclet.50655246_33489"> In Boolean logic, the negation of a logical OR. - + OE @@ -399,7 +399,7 @@ xml:id="dbdoclet.50655246_33489"> Position-independent executable - + PIM @@ -423,7 +423,7 @@ xml:id="dbdoclet.50655246_33489"> Performance Monitor Registers - + POSIX @@ -431,7 +431,7 @@ xml:id="dbdoclet.50655246_33489"> Portable Operating System Interface - + PS @@ -439,7 +439,7 @@ xml:id="dbdoclet.50655246_33489"> Positive sign - + RN @@ -448,7 +448,7 @@ xml:id="dbdoclet.50655246_33489"> FPSCR register. - + RPG @@ -456,7 +456,7 @@ xml:id="dbdoclet.50655246_33489"> Report Program Generator - + SHA @@ -488,7 +488,7 @@ xml:id="dbdoclet.50655246_33489"> Special Purpose Register - + SVID @@ -528,7 +528,7 @@ xml:id="dbdoclet.50655246_33489"> Thread pointer - + UE @@ -545,7 +545,7 @@ xml:id="dbdoclet.50655246_33489"> Unit of least precision - + VDSO @@ -553,7 +553,7 @@ xml:id="dbdoclet.50655246_33489"> Virtual dynamic shared object - + VE @@ -586,7 +586,7 @@ xml:id="dbdoclet.50655246_33489"> Vector scalar extension - + XE @@ -595,7 +595,7 @@ xml:id="dbdoclet.50655246_33489"> FPSCR register. - + XER @@ -603,7 +603,7 @@ xml:id="dbdoclet.50655246_33489"> Fixed-Point Exception Register - + XNOR @@ -611,7 +611,7 @@ xml:id="dbdoclet.50655246_33489"> Exclusive NOR - + XOR @@ -619,7 +619,7 @@ xml:id="dbdoclet.50655246_33489"> Exclusive OR - + ZE diff --git a/specification/bk_main.xml b/specification/bk_main.xml index 2efdd6f..80700a4 100644 --- a/specification/bk_main.xml +++ b/specification/bk_main.xml @@ -105,9 +105,9 @@ - 2016-06-13 + 2016-06-13 - + Version 1.3: POWER9 support. @@ -116,9 +116,9 @@ - 2016-06-13 + 2016-06-13 - + Version 1.2: POWER8 errata. diff --git a/specification/ch_2.xml b/specification/ch_2.xml index ea29df9..c7c3e40 100644 --- a/specification/ch_2.xml +++ b/specification/ch_2.xml @@ -2715,7 +2715,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> 264 – 1. - + @@ -2732,7 +2732,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 1 unsigned quadword. - + @@ -2749,7 +2749,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 1 signed quadword. - + @@ -4488,7 +4488,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - Erratum: + When executing an mfocr instruction, the POWER8 processor does not implement the behavior described in the "Fixed-Point Invalid Forms @@ -5387,7 +5387,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Pad an aggregate or union smaller than one doubleword in - size, but having a non-zero size, + size, but having a non-zero size, so that it is in the least-significant bits of the doubleword. Pad all others, if @@ -5556,8 +5556,8 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> a number of GPRs are skipped, in allocation order, commensurate to the size of the corresponding in-memory representation of the passed argument's type. - The parameter size is always rounded up to the next multiple of a - doubleword. + The parameter size is always rounded up to the next multiple of a + doubleword. Consequently, each parameter of a non-zero size is allocated to at least one doubleword. diff --git a/specification/ch_3.xml b/specification/ch_3.xml index 496d8b9..aa084d2 100644 --- a/specification/ch_3.xml +++ b/specification/ch_3.xml @@ -444,7 +444,7 @@ e_ident[EI_DATA] ELFDATA2LSB For all little-endian implementations.The local-entry-point handling field of st_other is generated with the .localentry pseudo op. The following is an example using the medium code model: - .globl my_func + .globl my_func .type my_func, @function my_func: addis r2, r12, (.TOC.-my_func)@ha @@ -459,11 +459,11 @@ my_func: points, even if the global entry point will not be used. (In such a case, the instructions of the global entry setup sequence may optionally be initialized with TRAP instructions.) - For very large programs, a 32-bit offset from + For very large programs, a 32-bit offset from the TOC base may not suffice to reach all function addresses. In this case, the large program model must be used, and the above sequence is replaced by: - .globl my_func + .globl my_func .type my_func, @function .quad .TOC.-my_func my_func: @@ -473,10 +473,10 @@ my_func: .localentry my_func, .-my_func ... ; function definition blr - The linker will resolve .TOC.-my_func to a + The linker will resolve .TOC.-my_func to a 64-bit offset stored 8 bytes prior to the global entry point. The prologue code then forms the absolute address of the TOC base. - Optionally, the linker may optimize the + Optionally, the linker may optimize the prologue sequence for functions that are within 2GB of the TOC base. To faciliate this, the compiler may associate an R_PPC64_ENTRY relocation with the global entry point. Note that this relocation @@ -4030,7 +4030,7 @@ my_func: .) - + R_PPC64_ENTRY @@ -4234,8 +4234,8 @@ my_func: inserting a call to a PLT stub code, the PLT stub code must not rely on the presence of a valid TOC base address in TOC register r2 to reference the PLT function table. - R_PPC64_ENTRY - This relocation type may optionally be + R_PPC64_ENTRY + This relocation type may optionally be associated with a global entry point. See for discussion of its use. diff --git a/specification/ch_4.xml b/specification/ch_4.xml index 6b5be70..81b1854 100644 --- a/specification/ch_4.xml +++ b/specification/ch_4.xml @@ -353,7 +353,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en"> argument passing. For example, a C program might typically issue the following declaration to begin executing at the local entry point of a function named main: - extern int main (int argc, char *argv[ ], char *envp[ ], void *auxv[ ]); + extern int main (int argc, char *argv[ ], char *envp[ ], void *auxv[ ]); int main(int argc, char *argv[ ], char *envp[ ], ElfW(auxv_t) *auxvec) where: diff --git a/specification/ch_5.xml b/specification/ch_5.xml index 71f7e4a..753b265 100644 --- a/specification/ch_5.xml +++ b/specification/ch_5.xml @@ -65,13 +65,13 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> such headers. They shall have the following definitions: - typedef long long ptrdiff_t; + typedef long ptrdiff_t; - typedef unsigned longint size_t; + typedef unsigned long size_t; - typedef intlong wchar_t; + typedef int wchar_t; typedef int sig_atomic_t; @@ -89,7 +89,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> typedef int int32_t; - typedef long long int64_t; + typedef long int64_t; typedef unsigned char uint8_t; @@ -101,7 +101,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> typedef unsigned int uint32_t; - typedef unsigned long long uint64_t; + typedef unsigned long uint64_t; typedef signed char int_least8_t; @@ -113,7 +113,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> typedef int int_least32_t; - typedef long long int_least64_t; + typedef long int_least64_t; typedef unsigned char uint_least8_t; @@ -125,7 +125,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> typedef unsigned int uint_least32_t; - typedef unsigned long long uint_least64_t; + typedef unsigned long uint_least64_t; typedef signed char int_fast8_t; @@ -137,7 +137,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> typedef int int_fast32_t; - typedef long long int_fast64_t; + typedef long int_fast64_t; typedef unsigned char uint_fast8_t; @@ -149,19 +149,19 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> typedef unsigned int uint_fast32_t; - typedef unsigned long long uint_fast64_t; + typedef unsigned long uint_fast64_t; - typedef long long intptr_t; + typedef long intptr_t; - typedef unsigned long long uintptr_t; + typedef unsigned long uintptr_t; - typedef long long intmax_t; + typedef long intmax_t; - typedef unsigned long long uintmax_t; + typedef unsigned long uintmax_t;
diff --git a/specification/ch_6.xml b/specification/ch_6.xml index a1c2f53..ac7c35f 100644 --- a/specification/ch_6.xml +++ b/specification/ch_6.xml @@ -239,7 +239,7 @@ register vector double vd = vec_splats(*double_ptr); - + vec_bperm @@ -251,7 +251,7 @@ register vector double vd = vec_splats(*double_ptr); the result. - + vec_cntlz_lsbb @@ -262,7 +262,7 @@ register vector double vd = vec_splats(*double_ptr); For LE, use vctzlsbb. - + vec_cnttz_lsbb @@ -284,7 +284,7 @@ register vector double vd = vec_splats(*double_ptr); vec_extract (v, 3) is equivalent to v[3]. - + vec_extract_fp32_from_shorth @@ -295,7 +295,7 @@ register vector double vd = vec_splats(*double_ptr); For LE, extract the left four elements. - + vec_extract_fp32_from_shortl @@ -306,7 +306,7 @@ register vector double vd = vec_splats(*double_ptr); For LE, extract the right four elements. - + vec_extract4b @@ -318,7 +318,7 @@ register vector double vd = vec_splats(*double_ptr); halves of the result. - + vec_first_match_index @@ -329,7 +329,7 @@ register vector double vd = vec_splats(*double_ptr); For LE, use vctz. - + vec_first_match_index_or_eos @@ -352,7 +352,7 @@ register vector double vd = vec_splats(*double_ptr); third element modified to contain x. - + vec_insert4b @@ -548,7 +548,7 @@ register vector double vd = vec_splats(*double_ptr); Use vupkhsb, and so on, for LE. - + vec_xl_len_r @@ -561,7 +561,7 @@ register vector double vd = vec_splats(*double_ptr); number of bytes specified to be loaded by vec_xl_len_r. - + vec_xst_len_r @@ -1183,7 +1183,7 @@ register vector double vd = vec_splats(*double_ptr); - vec_xlw4 + vec_xlw4 Deprecated. The use of vector data type assignment and overloaded vec_xl and vec_xst vector built-in functions are preferred forms for assigning @@ -1301,7 +1301,7 @@ register vector double vd = vec_splats(*double_ptr); - + VEC_CONCAT (ARG1, ARG2)(Fortran) @@ -1322,7 +1322,7 @@ register vector double vd = vec_splats(*double_ptr); - + @@ -1331,7 +1331,7 @@ register vector double vd = vec_splats(*double_ptr); signed long long); - + @@ -1340,7 +1340,7 @@ register vector double vd = vec_splats(*double_ptr); unsigned long long); - +