diff --git a/specification/bk_main.xml b/specification/bk_main.xml
index e1f6468..4262e2a 100644
--- a/specification/bk_main.xml
+++ b/specification/bk_main.xml
@@ -37,7 +37,7 @@
- 2014-2018
+ 2014-2019
OpenPOWER Foundation
@@ -57,7 +57,7 @@
Freescale Semiconductor, Inc
- Revision 1.5h draft
+ Revision 1.5i draft
OpenPOWER
@@ -94,7 +94,17 @@
- 2018-12-20
+ 2019-04-16
+
+
+
+ Revision 1.5i: Changes from compiler workshop.
+
+
+
+
+
+ 2019-02-01
diff --git a/specification/ch_2.xml b/specification/ch_2.xml
index 3e00de3..46c161f 100644
--- a/specification/ch_2.xml
+++ b/specification/ch_2.xml
@@ -6645,8 +6645,8 @@ s6 - 72 (stored)
instructions:
- lis r16, symbol@ha
-ld r12, symbol@l(r16)
+ lis r16, symbol@hba
+ld r10, symbol@l(r16)
lis r16, symbol2@ha
addi r16, r16, symbol2@l
@@ -6658,8 +6658,8 @@ lvx v1, r0, r16
.)
- <load TOC base to r2>
-ld r12, symbol@toc(r2)
+ <load TOC base to r2>
+ld r10, symbol@toc(r2)
li r16, symbol2@toc
lvx v1, r2, r16
@@ -6669,13 +6669,13 @@ lvx v1, r2, r16
addressing:
- <load TOC base to r2>
+ <load TOC base to r2>
-ld r12, symbol@got(r2)
-ld r12, 0(r12)
+ld r10, symbol@got(r2)
+ld r10, 0(r10)
-ld r12, symbol2@got(r2)
-lvx v1, 0, r12
+ld r10, symbol2@got(r2)
+lvx v1, 0, r10
@@ -6683,7 +6683,7 @@ lvx v1, 0, r12
- pld r12, symbol@pcrel
+ pld r10, symbol@pcrel
plxv v1, symbol@pcrel
In the OpenPOWER ELF V2 ABI, position-dependent code built with
@@ -6769,9 +6769,9 @@ plxv v1, symbol@pcrel
relative addressing (for private data).
- <load TOC base to r2>
+ <load TOC base to r2>
-ld r12, symbol@toc(r2)
+ld r10, symbol@toc(r2)
li r16, symbol2@toc
lvx v1, r2, r16
@@ -6782,21 +6782,21 @@ lvx v1, r2, r16
sections):
- <load TOC base to r2>
+ <load TOC base to r2>
-ld r12, symbol@got(r2)
+ld r10, symbol@got(r2)
-ld r12, 0(r12)
+ld r10, 0(r10)
-ld r12 symbol2@got(r2)
-lvx v1, 0, r12
+ld r10, symbol2@got(r2)
+lvx v1, 0, r10
By using PC-relative addressing (for
private data).
- pld r12, symbol@pcrel
+ pld r10, symbol@pcrel
plxv v1, symbol@pcrel
@@ -6806,11 +6806,11 @@ plxv v1, symbol@pcrel
- pld r12, symbol@got@pcrel
-ld r12, 0(r12)
+ pld r10, symbol@got@pcrel
+ld r10, 0(r10)
-pld r12, symbol@got@pcrel
-lvx v1, 0, r12
+pld r10, symbol@got@pcrel
+lvx v1, 0, r10
A compiler may generate a PC-relative addressing sequence to access
static or restricted-visibility data, but must generate a PC-relative
diff --git a/specification/ch_3.xml b/specification/ch_3.xml
index 08780fa..a39a81e 100644
--- a/specification/ch_3.xml
+++ b/specification/ch_3.xml
@@ -5350,15 +5350,15 @@ target:
and replace the reference with direct PC-relative addressing.
For example:
- pld r12, symbol@got@pcrel
-lvx v1, 0, r12
+ pld r10, symbol@got@pcrel
+lvx v1, 0, r10
The previous sequence may be replaced by:
plxv v1, symbol@pcrel
nop
However, this optimization is not universally safe, since it
- changes the value of r12 following the data reference. The
- compiler or programmer must ensure that the value of r12 is not
+ changes the value of r10 following the data reference. The
+ compiler or programmer must ensure that the value of r10 is not
subsequently used, and communicate a request for this optimization
by placing an R_PPC64_PCREL_OPT relocation on the first instruction
in the sequence. The compiler or programmer must further ensure that
@@ -5375,19 +5375,19 @@ nop
of these instructions, but may instead generate a short sequence
that can be optimized by a linker. For example:
- paddi r12,symbol@pcrel
-pmlxvx v1,r10,r12,VRM,MC,P,0
+ paddi r10,symbol@pcrel
+pmlxvx v1,r9,r10,VRM,MC,P,0
The previous sequence may be replaced by:
dnop
-pmlxv v1,symbol@pcrel(r10),VRM,MC,P,1
+pmlxv v1,symbol@pcrel(r9),VRM,MC,P,1
when the linker determines that the offset from the current
instruction address to symbol's address will fit in 28 bits.
Again, this optimization is not universally safe, since it changes
- the value of r12 following the data reference. The compiler or
- programmer must ensure that the value of r12 is not subsequently
+ the value of r10 following the data reference. The compiler or
+ programmer must ensure that the value of r10 is not subsequently
used, and communicate a request for this optimization by placing
an R_PPC64_PCREL_OPT relocation on the first instruction in the
sequence. The compiler or programmer must further ensure that the
diff --git a/specification/ch_4.xml b/specification/ch_4.xml
index cceb7d2..10f8603 100644
--- a/specification/ch_4.xml
+++ b/specification/ch_4.xml
@@ -716,7 +716,9 @@ PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.0 */
PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float 128-bit */
PPC_FEATURE2_DARN 0x00200000 /* darn instruction */
PPC_FEATURE2_SCV 0x00100000 /* scv syscall */
-PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 /* TM without suspended state */
+PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 /* TM without suspended state */
+PPC_FEATURE2_ARCH_3_1 0x00040000 /* ISA 3.1 */
+PPC_FEATURE2_MMA 0x00020000 /* Matrix Multiply Accumulate */
When a process starts to execute, its stack holds the arguments,
environment, and auxiliary vector received from the exec call. The system
makes no guarantees about the relative arrangement of argument strings,