diff --git a/specification/app_a.xml b/specification/app_a.xml index f8bba6d..9792b14 100644 --- a/specification/app_a.xml +++ b/specification/app_a.xml @@ -821,7 +821,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> vector bool long long vec_and (vector bool long long, - vector bool long long) + vector bool long long); diff --git a/specification/app_b.xml b/specification/app_b.xml index 98dcc69..0d3770c 100644 --- a/specification/app_b.xml +++ b/specification/app_b.xml @@ -15,10 +15,10 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en" xml:id="dbdoclet.50655245_pgfId-1450875" revisionflag="added"> Binary-Coded Decimal Built-In Functions Binary-coded decimal (BCD) values are compressed; each decimal digit - and sign bit occupies 4 bits. Digits are ordered right-to-left in the order - of significance. The final 4 bits encode the sign. A valid encoding must - have a value in the range 0–9 in each of its 31 digits, and a value in - the range 10–15 for the sign field. + and sign bit occupies 4 bits. Digits are ordered with the most significant + on the left and the least on the right. The final 4 bits encode the sign. + A valid encoding must have a value in the range 0–9 in each of its 31 + digits, and a value in the range 10–15 for the sign field. Source operands with sign codes of 0b1010, 0b1100, 0b1110, or 0b1111 are interpreted as positive values. Source operands with sign codes of 0b1011 or 0b1101 are interpreted as negative values. diff --git a/specification/app_glossary.xml b/specification/app_glossary.xml index 98b9d58..c4d9274 100644 --- a/specification/app_glossary.xml +++ b/specification/app_glossary.xml @@ -314,7 +314,7 @@ xml:id="dbdoclet.50655246_33489"> LSB - Least-significant byte + Least-significant byte, least-significant bit @@ -330,7 +330,7 @@ xml:id="dbdoclet.50655246_33489"> MSB - Most-significant byte + Most-significant byte, most-significant bit diff --git a/specification/ch_1.xml b/specification/ch_1.xml index 15c143f..4ac5519 100644 --- a/specification/ch_1.xml +++ b/specification/ch_1.xml @@ -40,7 +40,7 @@ OpenPOWER-compliant processors in the 64-bit Power Architecture can execute in either big-endian or little-endian mode. Executables and executable-generated data (in general) that subscribe to either byte - ordering is not portable to a system running in the other mode. + ordering are not portable to a system running in the other mode. Note: diff --git a/specification/ch_2.xml b/specification/ch_2.xml index c01c63d..ea18225 100644 --- a/specification/ch_2.xml +++ b/specification/ch_2.xml @@ -2234,13 +2234,13 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> long int - + 8 - + Doubleword - + Signed doubleword @@ -2248,15 +2248,6 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> signed long int - - 8 - - - Doubleword - - - Signed doubleword - @@ -2806,7 +2797,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Quadword - Vector of 2 double-precision doubles. + Vector of 2 double-precision floats. @@ -2981,10 +2972,10 @@ xml:id="dbdoclet.50655240_pgfId-1156194">   - IEEE BINARY 128 EXTENDED + IEEE BINARY 128 QUADRUPLE PRECISION - IEEE BINARY 128 EXTENDED PRECISION Type + IEEE BINARY 128 QUADRUPLE PRECISION Type @@ -3029,7 +3020,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - IEEE BINARY 128 EXTENDED PRECISION + IEEE BINARY 128 QUADRUPLE PRECISION long double @@ -3052,7 +3043,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - IEEE BINARY 128 EXTENDED PRECISION + IEEE BINARY 128 QUADRUPLE PRECISION _Float128 @@ -3095,14 +3086,14 @@ xml:id="dbdoclet.50655240_pgfId-1156194">
  - IBM EXTENDED PRECISION && IEEE BINARY 128 EXTENDED + IBM EXTENDED PRECISION && IEEE BINARY 128 QUADRUPLE PRECISION Availability of the long double data type is subject to conformance to a long double standard where the IBM EXTENDED PRECISION - format and the IEEE BINARY 128 EXTENDED PRECISION format are mutually + format and the IEEE BINARY 128 QUADRUPLE PRECISION format are mutually exclusive.   - IEEE BINARY 128 EXTENDED + IEEE BINARY 128 QUADRUPLE PRECISION || IBM EXTENDED PRECISION This ABI provides the following choices for implementation of long double in compilers and systems. The preferred implementation for @@ -3110,7 +3101,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> type. - IEEE BINARY 128 EXTENDED PRECISION + IEEE BINARY 128 QUADRUPLE PRECISION Long double is implemented as an IEEE 128-bit quad-precision @@ -3121,8 +3112,8 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Support is provided for all IEEE standard features. - IEEE128 quad-precision values are passed in VMX parameter - registers. + IEEE128 quad-precision values are passed and returned in + VMX parameter registers. With some compilers, _Float128 can be used to access IEEE128 @@ -3211,9 +3202,9 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> previous member, internal padding can be required. - The entire aggregate or union must have a size that is a - multiple of its alignment. Depending on the last member, tail - padding may be required. + Unless it is packed, the entire aggregate or union must have + a size that is a multiple of its alignment. Depending on the last + member, tail padding may be required. For @@ -3459,9 +3450,9 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> least-significant (right) end. - A bit field cannot cross its unit boundary; it must occupy - part or all or the storage unit allocated for its declared - type. + Unless it appears in a packed struct, a bit field cannot + cross its unit boundary; it must occupy part or all of the storage + unit allocated for its declared type. If there is enough space within a storage unit, bit fields @@ -4644,27 +4635,14 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> DFP Support The OpenPOWER ABI supports the decimal floating-point (DFP) format and DFP language extensions. The default implementation of DFP - types shall be a software implementation of the IEEE DFP standard (IEEE - Standard 754-2008). + types shall be an implementation of the IEEE DFP standard (IEEE + Standard 754-2008). The default may be either a hardware or a + software implementation. The Power ISA decimal floating-point category extends the Power Architecture by adding a decimal floating-point unit. It uses the existing 64-bit floating-point registers and extends the FPSCR register to 64 bits, where it defines a decimal rounding-control field in the - extended space. For OpenPOWER, DFP support is defined as an optional - category. When DFP is supported as a vendor-specific implementation - capability, compilers can be used to implement DFP support. The - compilers should provide an option to generate DFP instructions or to - issue calls to DFP emulation software. The DFP parameters are passed in - floating-point registers. - As with other implementation-specific features, all - OpenPOWER-compliant programs must be able to execute, functionally - indistinguishably, on hardware with and without vendor-specific - extensions. It is the application's responsibility to transparently - adapt to the absence of vendor-specific features by using a library - responsive to the presence of DFP hardware, or in conjunction with - operating-system dynamic library services, to select from among - multiple DFP libraries that contain either a first software - implementation or a second hardware implementation. + extended space. Single-precision, double-precision, and quad-precision decimal floating-point parameters shall be passed in the floating-point registers. Single-precision decimal floating-point shall occupy the @@ -4721,6 +4699,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> + Vector Registers The OpenPOWER vector-category instruction repertoire provides the ability to reference 32 vector registers, each 128 bits wide, of the vector-scalar register file, and a special-purpose register VSCR. @@ -4815,17 +4794,17 @@ xml:id="dbdoclet.50655240_pgfId-1156194">   - IEEE BINARY 128 EXTENDED + IEEE BINARY 128 QUADRUPLE PRECISION - Parameters in IEEE BINARY 128 EXTENDED PRECISION format shall be - passed in a single 128-bit vector register as if they were vector - values. + Parameters and function results in IEEE BINARY 128 QUADRUPLE + PRECISION format shall be passed in a single 128-bit vector register + as if they were vector values.   IBM EXTENDED PRECISION - Parameters in the IBM EXTENDED PRECISION format with a pair of - two double-precision floating-point values shall be passed in two - successive floating-point registers. + Parameters and function results in the IBM EXTENDED PRECISION + format with a pair of two double-precision floating-point values shall + be passed in two successive floating-point registers. If only one value can be passed in a floating-point register, the second parameter will be passed in a GPR or in memory in accordance with the parameter passing rules for structure aggregates. @@ -5081,7 +5060,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - . + See . Before a function calls any other functions, it shall save @@ -5250,8 +5229,8 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Parameter Save Area to be created for functions where the number and type of parameters exceeds the registers available for parameter passing in registers, for those functions where the prototype contains - an ellipsis to indicate a variadic function, and functions are declared - without prototype.) + an ellipsis to indicate a variadic function, and functions declared + without a prototype.) When the caller allocates the Parameter Save Area, it will always be automatically quadword aligned because it must always start at SP + 32. It shall be at least 8 doublewords in length. If a function needs @@ -5346,7 +5325,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> If extended precision floating-point values in IEEE BINARY - 128 EXTENDED PRECISION format are supported (see + 128 QUADRUPLE PRECISION format are supported (see ), map them to a single quadword, quadword aligned. This might result in skipped doublewords in the Parameter Save Area. @@ -5506,7 +5485,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> floating-point type. (A complex floating-point data type is treated as if two separate scalar values of the base type were passed.) Homogeneous floating-point aggregates can have up to four IBM - EXTENDED PRECISION members, four IEEE BINARY 128 EXTENDED precision + EXTENDED PRECISION members, four IEEE BINARY 128 QUADRUPLE PRECISION members, four _Decimal128 members, or eight members of other floating-point types. (Unions are treated as their largest member. For homogeneous unions, different union alternatives may have different @@ -5554,7 +5533,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> A homogeneous aggregate is either a homogeneous floating-point aggregate or a homogeneous vector aggregate. This ABI does not specify homogeneous aggregates for integer types. - Binary extended precision numbers in IEEE BINARY 128 EXTENDED + Binary extended precision numbers in IEEE BINARY 128 QUADRUPLE PRECISION format (see ) are passed using a VMX register. Binary extended precision numbers in IBM EXTENDED PRECISION @@ -5591,7 +5570,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> valid and invalid, except in the last doubleword where invalid padding may be present.)   - IEEE BINARY 128 EXTENDED PRECISION + IEEE BINARY 128 QUADRUPLE PRECISION Up to 12 quad-precision parameters can be passed in v2–v13. @@ -5766,13 +5745,13 @@ float: // float is passed in one FPR. // double is passed in one FPR. // IBM EXTENDED PRECISION is passed in the next two FPRs. -// IEEE BINARY 128 EXTENDED PRECISION is passed in one VR. +// IEEE BINARY 128 QUADRUPLE PRECISION is passed in one VR. // _Decimal32 is passed in the lower half of one FPR. // _Decimal64 is passed in one FPR. // _Decimal128 is passed in an even-odd FPR pair, skipping an FPR if necessary. if (register_type_used (type (argument)) == vr) - // Assumes == vr is true for IEEE BINARY 128 EXTENDED PRECISION. + // Assumes == vr is true for IEEE BINARY 128 QUADRUPLE PRECISION. goto use_vr; fr += align_pad(fr,type(argument)) diff --git a/specification/ch_6.xml b/specification/ch_6.xml index 434d471..a1c2f53 100644 --- a/specification/ch_6.xml +++ b/specification/ch_6.xml @@ -103,8 +103,8 @@ register vector double vd = vec_splats(*double_ptr); types. The traditional C/C++ operators are defined on vector types with “do all” semantics for unary and binary +, unary and binary –, binary *, binary - %, and binary / as well as the unary and binary logical and comparison - operators. + %, and binary / as well as the unary and binary shift, logical and + comparison operators, and the ternary ?: operator. For unary operators, the specified operation is performed on the corresponding base element of the single operand to derive the result value for each vector element of the vector result. The result type of unary @@ -871,8 +871,12 @@ register vector double vd = vec_splats(*double_ptr); lxvd2x - Use lxvd2x for vector long long; vector long, vector - double. + Use lxvd2x for vector long long; vector long, + The vector long types are deprecated due to their + ambiguity between 32-bit and 64-bit environments. The use + of the vector long long types is preferred. + vector double. Use lxvd2x followed by reversal of elements within each doubleword for all other data types. @@ -885,8 +889,8 @@ register vector double vd = vec_splats(*double_ptr); stxvd2x - Use stxvd2x for vector long long; vector long, vector - double. + Use stxvd2x for vector long long; vector long, vector double. Use stxvd2x following a reversal of elements within each doubleword for all other data types. @@ -1169,8 +1173,12 @@ register vector double vd = vec_splats(*double_ptr); lxvd2x - Use lxvd2x for vector long long; vector long, vector - double. + Use lxvd2x for vector long long; vector long, + The vector long types are deprecated due to their + ambiguity between 32-bit and 64-bit environments. The use + of the vector long long types is preferred. + vector double. @@ -1213,8 +1221,8 @@ register vector double vd = vec_splats(*double_ptr); stxvd2x - Use stxvd2x for vector long long; vector long, vector - double. + Use stxvd2x for vector long long; vector long, vector double. @@ -1274,7 +1282,7 @@ register vector double vd = vec_splats(*double_ptr); bit-exact type conversions between vector types. - Built-In Vector Conversion Function + Built-In Vector Conversion Functions @@ -1422,7 +1430,12 @@ register vector double vd = vec_splats(*double_ptr); VECTOR(INTEGER(8)) - vector signed long long, vector signed long + vector signed long long, vector signed long + The vector long types are deprecated due to their + ambiguity between 32-bit and 64-bit environments. The use + of the vector long long types is preferred. + @@ -1462,7 +1475,8 @@ register vector double vd = vec_splats(*double_ptr); VECTOR(UNSIGNED(8)) - vector unsigned long long, vector unsigned long + vector unsigned long long, vector unsigned long