This ABI does not specify any additional interfaces for general-purpose libraries. However, certain processor-specific support routines are defined to ensure portability between ABI-conforming implementations. Such processor-specific support definitions concern vector and floating-point alignment, register save and restore routines, variable argument list layout, and a limited set of data definitions.

The malloc( ) routine must always return a pointer with the alignment of the largest alignment needed for loads and stores of the built-in data types. This is currently 16 bytes.

Requirements for the handling of limited-access bits in certain registers by standard library functions are defined in .

All of the save and restore routines described in are required. These routines use unusual calling conventions due to their special purpose. Parameters for these functions are described in , , and . The symbols for these functions shall be hidden and locally resolved within each module. The symbols so created shall not be exported. These functions can either be provided in a utility library that is linked by the linker to each module, or the functions can be synthesized by the linker as necessary to resolve symbols.

The type va_list shall be defined as follows: typedef void * va_list; The following integer types are defined in headers, which must be provided by freestanding implementations, or have their limits defined in such headers. They shall have the following definitions: typedef long long ptrdiff_t; typedef unsigned longint size_t; typedef intlong wchar_t; typedef int sig_atomic_t; typedef unsigned int wint_t; typedef signed char int8_t; typedef short int16_t; typedef int int32_t; typedef long long int64_t; typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned int uint32_t; typedef unsigned long long uint64_t; typedef signed char int_least8_t; typedef short int_least16_t; typedef int int_least32_t; typedef long long int_least64_t; typedef unsigned char uint_least8_t; typedef unsigned short uint_least16_t; typedef unsigned int uint_least32_t; typedef unsigned long long uint_least64_t; typedef signed char int_fast8_t; typedef int int_fast16_t; typedef int int_fast32_t; typedef long long int_fast64_t; typedef unsigned char uint_fast8_t; typedef unsigned int uint_fast16_t; typedef unsigned int uint_fast32_t; typedef unsigned long long uint_fast64_t; typedef long long intptr_t; typedef unsigned long long uintptr_t; typedef long long intmax_t; typedef unsigned long long uintmax_t;

A C preprocessor that conforms to this ABI shall predefine the macro _CALL_ELF to have a value of 2. The macros listed in are based on environment characteristics. They shall be predefined to a value of 1 by conforming C preprocessors when the corresponding condition applies. Macro Condition __PPC__ __powerpc__ The target is a Power Architecture processor. __PPC64__ __powerpc64__ __64BIT__ Phased in. The target is a Power Architecture processor running in 64-bit mode. __BIG_ENDIAN__ The target processor is big endian. __LITTLE_ENDIAN__ The target processor is little endian. ARCH_PWRn Indicates that the target processor supports the Power ISA level for POWERn or higher. For example, ARCH_PWR8 supports the Power ISA for a POWER8 processor. The macros in listed are based on the order of the data elements. They shall be predefined to one of the allowable values by conforming C preprocessors when the corresponding condition applies. Macro Value Condition __BYTE_ORDER__ __ORDER_BIG_ENDIAN__ The target processor is big endian. __ORDER_LITTLE_ENDIAN__ The target processor is little endian. __FLOAT_WORD_ORDER__ __ORDER_BIG_ENDIAN__ The target processor is big endian. __ORDER_LITTLE_ENDIAN__ The target processor is little endian. __VEC_ELEMENT_REG_ORDER__ For more information, see . __ORDER_BIG_ENDIAN__ The target processor is big endian, or big-endian vector element order has been requested. __ORDER_LITTLE_ENDIAN__ The target processor is little endian, and big-endian vector element order has not been requested.

The Data Stream Control Register (DSCR) affects how the processor handles data streams that are detected by the hardware and defined by the software. For more information, see “Data Stream Control Overview, ABI, and API” at the following link: https://github.com/paflib/paflib/wiki/Data-Stream-Control-Overview,-ABI,-and-API The event-based branching facility generates exceptions when certain criteria are met. For more information, see the “Event Based Branching Overview, ABI, and API” section at the following link: https://github.com/paflib/paflib/wiki/Event-Based-Branching----Overview,-ABI,-and-API