From 4231cede142393e3c108f3f8c8a630c84c8303e1 Mon Sep 17 00:00:00 2001 From: Jeff Scheel Date: Wed, 22 Apr 2020 09:41:45 -0500 Subject: [PATCH] Tree cleanup: remove old directories for sub-docs. Signed-off-by: Jeff Scheel --- DeviceTree/app_bibliography.xml | 284 ------ DeviceTree/app_glossary.xml | 1290 ------------------------ DeviceTree/bk_main.xml | 345 ------- DeviceTree/ch_introduction.xml | 97 -- DeviceTree/pom.xml | 148 --- Error Handling/app_bibliography.xml | 284 ------ Error Handling/app_glossary.xml | 1290 ------------------------ Error Handling/bk_main.xml | 348 ------- Error Handling/pom.xml | 148 --- Error Handling/sec_error_reporting.xml | 87 -- Platform/bk_main.xml | 357 ------- Platform/pom.xml | 148 --- RTAS/app_bibliography.xml | 284 ------ RTAS/app_glossary.xml | 1290 ------------------------ RTAS/bk_main.xml | 347 ------- RTAS/ch_error_codes.xml | 1272 ----------------------- RTAS/pom.xml | 148 --- Virtualization/app_bibliography.xml | 284 ------ Virtualization/app_glossary.xml | 1282 ----------------------- Virtualization/bk_main.xml | 349 ------- Virtualization/pom.xml | 148 --- 21 files changed, 10230 deletions(-) delete mode 100644 DeviceTree/app_bibliography.xml delete mode 100644 DeviceTree/app_glossary.xml delete mode 100644 DeviceTree/bk_main.xml delete mode 100644 DeviceTree/ch_introduction.xml delete mode 100644 DeviceTree/pom.xml delete mode 100644 Error Handling/app_bibliography.xml delete mode 100644 Error Handling/app_glossary.xml delete mode 100644 Error Handling/bk_main.xml delete mode 100644 Error Handling/pom.xml delete mode 100644 Error Handling/sec_error_reporting.xml delete mode 100644 Platform/bk_main.xml delete mode 100644 Platform/pom.xml delete mode 100644 RTAS/app_bibliography.xml delete mode 100644 RTAS/app_glossary.xml delete mode 100644 RTAS/bk_main.xml delete mode 100644 RTAS/ch_error_codes.xml delete mode 100644 RTAS/pom.xml delete mode 100644 Virtualization/app_bibliography.xml delete mode 100644 Virtualization/app_glossary.xml delete mode 100644 Virtualization/bk_main.xml delete mode 100644 Virtualization/pom.xml diff --git a/DeviceTree/app_bibliography.xml b/DeviceTree/app_bibliography.xml deleted file mode 100644 index bd1412b..0000000 --- a/DeviceTree/app_bibliography.xml +++ /dev/null @@ -1,284 +0,0 @@ - - - - - Bibliography - This section lists documents which were referenced in this specification or which provide - additional information, and some useful information for obtaining these documents. Referenced - documents are listed below. When any of the following standards are superseded by an approved - revision, the revision shall apply. - - - - - - Linux on Power Architecture Reference: Platform and Device Tree - - - - - - - Linux on Power Architecture Reference: Error Recovery and Logging - - - - - Linux on Power Architecture Reference: Virtualization - - - - - Linux on Power Architecture Reference: Runtime Abstraction Services (RTAS) - - - - - Power ISA - - - - - IEEE 1275, IEEE Standard for Boot (Initialization Configuration) Firmware: - Core Requirements and Practices - IEEE part number DS02683, ISBN 1-55937-426-8 - - - - - Core Errata, IEEE P1275.7/D4 - - - - - Open Firmware Recommended Practice:OBP-TFTP - Extension - - - - - Open Firmware Recommended Practice: Device - Support Extensions - - - - - PCI Bus binding to: IEEE Std 1275-1994, Standard - for Boot (Initialization, Configuration) Firmware - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping - - - - - Open Firmware: Recommended Practice - Forth Source - and FCode Image Support, Version 1.0 - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping, Version 1.0 - - - - - Open Firmware: Recommended Practice - TFTP Booting - Extensions, Version 0.8 - - - - - Open Firmware: Recommended Practice - - Interposition, Version 0.2 - - - - - MS-DOS Programmer's Reference - Published by Microsoft - - - - - Peering Inside the PE: A Tour of the Win32 Portable - Executable File Format - Found in the March, 1994 issue of Microsoft Systems Journal - - - - - ISO-9660, Information processing -- Volume and - file structure of CD-ROM for information interchange - Published by International Organization for Standardization - - - - - System V Application Binary Interface, PowerPC - Processor Supplement - By Sunsoft - - - - - ISO Standard 8879:1986, Information Processing - -- Text and Office Systems -- Standard Generalized Markup Language (SGML) - - - - - IEEE 996, A Standard for an Extended Personal Computer - Back Plane Bus - - - - - PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - PCI-to-PCI Bridge Architecture Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the - PCI SIG website for the most current version of this document. - - - - - PCI Standard Hot-Plug Controller and Subsystem - Specification - - - - - PCI-X Protocol Addendum to the PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI-X related components or platforms. See the PCI SIG website for the most - current version of this document. - - - - - PCI Express Base Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design PCI Express related components or platforms. See the PCI SIG website for - the most current version of this document. - - - - - PCI Express to PCI/PCI-X Bridge Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express related components or platforms. See the PCI SIG website for the most current - version of this document. - - - - - System Management BIOS (SMBIOS) Reference - Specification - - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - - IBM RS/6000® Division, Product Topology Data System, - Product Development Guide - Version 2.1 - - - - - Single Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI Express SR-IOV related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - Multi-Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express MR-IOV related components or platforms. See the PCI SIG website for the - most current version of this document. - - - - - - diff --git a/DeviceTree/app_glossary.xml b/DeviceTree/app_glossary.xml deleted file mode 100644 index acd25d0..0000000 --- a/DeviceTree/app_glossary.xml +++ /dev/null @@ -1,1290 +0,0 @@ - - - - - Glossary - This glossary contains an alphabetical list of terms, phrases, and abbreviations used in this document. - - - - Term - Definition - - - - AC - Alternating current - - - - ACR - Architecture Change Request - - - - AD - Address Data line - - - - Adapter - A device which attaches a device to a bus or which converts one - bus to another; for example, an I/O Adapter (IOA), a PCI Host Bridge (PHB), - or a NUMA fabric attachment device. - - - - - addr - Address - - - - Architecture - The hardware/software interface definition or software module to - software module interface definition. - - - - ASCII - American National Standards Code for Information - Interchange - - - - ASR - Address Space Register - - - - BAT - Block Address Translation - - - - BE - Big-Endian or Branch Trace Enable bit in the - MSR (MSRBE) - - - - BIO - Bottom of Peripheral Input/Output Space - - - - BIOS - Basic Input/Output system - - - - BIST - Built in Self Test - - - - Boundedly undefined - Describes some addresses and registers which when referenced provide - one of a small set of predefined results. - - - - BPA - Bulk Power Assembly. Refers to components used for power distribution - from a central point in the rack. - - - - BPM - Bottom of Peripheral Memory - - - - BSCA - Bottom of System Control Area - - - - BSM - Bottom of System Memory - - - - BUID - Bus Unit Identifier. The high-order part of an interrupt source number - which is used for hardware routing purposes by the platform. - - - - CCIN - Custom Card Identification Number - - - - CD-ROM - Compact Disk Read-Only Memory - - - - CIS - Client Interface Service - - - - CMO - Cooperative Memory Over-commitment option. See - for more information. - - - - - - CMOS - Complimentary Metal Oxide Semiconductor - - - - Conventional PCI - Behavior or features that conform to . - - - - CPU - Central Processing Unit - - - - CR - Condition Register - - - - CTR - Count Register - - - - DABR - Data Address Breakpoint Register - - - - DAR - Data Address Register - - - - DASD - Direct Access Storage Device (a synonym for “hard disk”) - - - - DBAT - Data Block Address Translation - - - - DC - Direct current - - - - DEC - Decrementer - - - - DIMM - Dual In-line Memory Module - - - - DMA - Direct Memory Access - - - - DMA Read - A data transfer from System Memory to I/O. A DMA Read Request - is the inbound operation and the DMA Read Reply (or Read Completion) is the - outbound data coming back from a DMA Read Request. - - - - DMA Write - A data transfer to System Memory from I/O or a Message Signalled Interrupt (MSI) DMA Write. This is an inbound operation. - - - - DOS - Disk OS - - - - DR - Data Relocate bit in MSR (MSRDR) - - - - DRA - Deviation Risk Assessment - - - - DRAM - Dynamic Random Access Memory - - - - DRC - Delayed Read Completion. A transaction that has completed - on the destination bus and is now moving toward the originating bus to complete. - DR Connector. - - - - DR entity - An entity that can participate in DR operations. That is, an entity - that can be added or removed from the platform while the platform power is on and the - system remains operational. - - - - DRR - Delayed Read Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - DSISR - Data Storage Interrupt Status Register - - - - DWR - Delayed Write Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - EA - Effective Address - - - - EAR - External Access Register - - - - ECC - Error Checking and Correction - - - - EE - External interrupt Enable bit in the MSR (MSREE) - - - - EEH - Enhance I/O Error Handling - - - - EEPROM - Electrically Erasable Programmable Read Only Memory - - - - EPOW - Environment and Power Warning - - - - - Error Log indicator An amber indicator that indicates that the user needs to - look at the error log or problem determination procedures, in order to determine the cause. - Previously called System Information (Attention). - - - - FCode - A computer programming language defined by the OF standard which is semantically - similar to the Forth programming language, but is encoded as a sequence of binary byte codes - representing a defined set of Forth words. - - - - FE0 - Floating-point Exception mode 0 bit in the MSR (MSRFE0) - - - - FE1 - Floating-point Exception mode 1bit in the MSR (MSRFE1) - - - - FIR - Fault Isolation Registers - - - - FLR - Function Level Reset (see PCI Express documentation). An optional reset for PCI Express - functions that allows resetting a single function of a multi-function IOA. - - - - FP - Floating-Point available bit in the MSR (MSRFP) - - - - FPSCR - Floating-Point Status And Control Register - - - - FRU - Field Replaceable Unit - - - - FSM - Finite State Machine - - - - GB - Gigabytes - as used in this document it is 2 raised to the power of 30 - - - - HB - Host Bridge - - - - HMC - Hardware Management Console - used generically to refer to the system - component that performs platform administration function where ever physically located. - The HMC is outside of this architecture and may be implemented in multiple ways. - Examples include: a special HMC applications in another system, an external appliance, - or in an LPAR partition using the Virtual Management Channel (VMC) interface to the - hypervisor. - - - - Hz - Hertz - - - - IBAT - Instruction block address translation - - - - ID - Identification - - - - IDE - Integrated Device Electronics - - - - IDU - Interrupt Delivery Unit - - - - IEEE - Institute of Electrical and Electronics Engineers - - - - I2C - Inter Integrated-circuit Communications - - - - I/O - nput/Output - - - - I/O bus master - Any entity other than a processor, cache, - memory controller, or host bridge which supplies both address and data in - write transactions or supplies the address and is the sink for the data in - read transactions. - - - - I/O device - Generally refers to any entity that is connected - to an IOA (usually through a cable), but in some cases may refer to the IOA - itself (that is, a device in the device tree that happens to be used for I/O - operations). - - - - I/O Drawer - An enclosure in a rack that holds at least one PHB and at - least one IOA. - - - - ILE - Interrupt Little-Endian bit in MSR (MSRILE) - - - - Instr - Instruction - - - - Interrupt Number - See Interrupt Vector below. - - - - Interrupt Vector - The identifier associated with a specific interrupt source. - The identifier’s value is loaded into the source’s Interrupt Vector Register and - is read from the Interrupt Delivery Unit’s Interrupt Acknowledge Register. - - - - IOA - I/O Adapter. A device which attaches to a physical bus which is capable - of supporting I/O (a physical IOA) or logical bus (a virtual IOA). The term “IOA” - without the usage of the qualifier “physical” or “virtual” will be - used to designate a physical IOA. Virtual IOAs are defined further in - - . - In PCI terms, an IOA may be defined by a unique combination of its assigned - bus number and device number, but not necessarily including its function number. - That is, an IOA may be a single or multi-function device, unless otherwise specified by - the context of the text. In the context of a PCIe I/O Virtualized (IOV) device (not to be - confused with a virtual IOA), an IOA is a single or multiple function device (for example, a - PCIe Virtual Function (VF) or multiple VFs). An IOA function may or may not have its own set of - resources, that is may or may not be in its own Partitionable Endpoint (PE) domain - (see also - - ). - - - - - IOA function - That part of an IOA that deals with a specific part of the - IOA as defined by the configuration space “Function” part of Bus/Device/Function. - For single-function IOAs, the IOA Function and the IOA are synonymous. - - - - IP - Interrupt Prefix bit in MSR (MSRIP) - - - - IPI - Interprocessor Interrupt - - - - IR - Instruction Relocate bit in MSR register (MSRIR) or infrared - - - - ISF - Interrupt 64-bit processor mode bit in the MSR (MSRISF) - - - - ISO - International Standards Organization - - - - ISR - Interrupt Source Register - - - - ISU - Interrupt Source Unit - - - - KB - Kilobytes - as used in this document it is 2 raised to the power of 10 - - - - KHz - Kilo Hertz - - - - LAN - Local Area Network - - - - LCD - Liquid Crystal Display - - - - LE - Little-Endian bit in MSR (MSRLE) or Little-Endian - - - - LED - Light Emitting Diode - - - - LMB - Logical Memory Block. The Block of logical memory addresses associated with a dynamically - reconfigurable memory node. - - - - Load - A Load Request is the outbound (from the processor) operation - and the Load Reply is the inbound data coming back from a - Load Request. When it relates to I/O operations, this is an - MMIO Load . - - - - LR - Link Register - - - - LSb - Least Significant bit - - - - LSB - Least Significant Byte - - - - LSI - Level Sensitive Interrupt - - - - LUN - Logical Unit Number - - - - L1 - Primary cache - - - - L2 - Secondary cache - - - - MB - Megabytes - as used in this document it is 2 raised to the power of 20 - - - - ME - Machine check Enable - - - - MMIO - Memory Mapped I/O. This refers to the mapping of the address space required - by an I/O device for Load or Store operations into - the system’s address space. - - - - MES - Miscellaneous Equipment Specification - - - - MFM - Modified frequency modulation - - - - MHz - Mega Hertz - - - - MOD - Address modification bit in the MSR - (MSRMOD) - - - - MP - Multiprocessor - - - - MSb - Most Significant bit - - - - MSB - Most Significant Byte - - - - MSI - Message Signalled Interrupt - - - - MSR - Machine State Register - - - - MTT - Multi-TCE-Table option. See - - - . - - - - - N/A - Not Applicable - - - - Nibble - Refers to the first or last four bits in an 8 bit byte - - - - NUMA - Non-Uniform Memory Access - - - - NUMA fabric - Mechanism and method for connecting the multiple nodes of a NUMA system - - - - NVRAM - Nonvolatile Random Access Memory - - - - OF - Open Firmware - - - - OP - Operator - - - - OS - Operating System - - - - OUI - Organizationally Unique Identifier - - - - PA - Processor Architecture - - - - PAP - Privileged Access Password - - - - LoPAR - Used within the Linux on Power Architecture - Reference documents to denote: (1) the architectural requirements specified - by the Linux on Power Architecture Reference document, (2) the Linux on Power Architecture - Reference documents themself, and (3) as an adjective to qualify an entity as being - related to this architecture. - - - - Partitionable Endpoint - This refers to the I/O granule that may be treated as one for - purposes of assignment to an OS (for example, to an LPAR partition). May be an - I/O adapter (IOA), or groups of IOAs and bridges, or portions of IOAs. PE granularity - supported by the hardware may be finer than is supported by the firmware. Grouping - of multiple PEs into one DR entity may limit assignment of a the separate PEs to different - LPAR partitions. See also DR entity. - - - - PC - Personal Computer - - - - PCI - Peripheral Component Interconnect. An all-encompassing term referring to - conventional PCI, PCI-X, and PCI Express. - - - - PCI bus - A general term referring to either the PCI Local Bus, as - specified in and - for conventional PCI and PCI-X, or a PCI Express link, as specified in - for PCI Express. - - - - PCI Express - Behavior or features that conform to - . - - - - PCI link - A PCI Express link, as specified in . - - - - PCI-X - Behavior or features that conform to . - - - - PD - Presence Detect - - - - PE - When referring to the body of the LoPAR, this refers to a Partitionable - Endpoint. - - - - - - - PEM - Partition Energy Management option. See - - - . - - - - - Peripheral I/O Space - The range of real addresses which are assigned - to the I/O Space of a Host Bridge (HB) and which are sufficient to contain all of - the Load and Store address space requirements of all the devices in the I/O Space - of the I/O bus that is generated by the HB. A keyboard controller is an example of - a device which may require Peripheral I/O Space addresses. - - - - Peripheral Memory Space - The range of real addresses which are assigned to the Memory - Space of a Host Bridge (HB) and which are sufficient to contain all of the Load and - Store address space requirements of the devices in the Memory Space of the I/O bus - that is generated by the HB. The frame buffer of a graphics adapter is an example - of a device which may require Peripheral Memory Space addresses. - - - - Peripheral Space - Refers to the physical address space which may - be accessed by a processor, but which is controlled by a host bridge. At least one - peripheral space must be present and it is referred to by the suffix 0. A host bridge - will typically provide access to at least a memory space and possibly to an I/O - space. - - - - PHB - PCI Host Bridge - - - - PIC - Programmable Interrupt Controller - - - - PIR - Processor Identification Register - - - - Platform - Refers to the hardware plus firmware portion of a system composed of hardware, - firmware, and OS. - - - - Platform firmware - Refers to all firmware on a system including the software or firmware in a - support processor. - - - - Plug-in I/O card - A card which can be plugged into an I/O - connector in a platform and which contains one or more IOAs and potentially - one or more I/O bridges or switches. - - - - Plug-in Card - An entity that plugs into a physical slot. - - - - PMW - Posted memory write. A transaction that has complete on the - originating bus before completing on the destination bus - - - - PnP - Plug and Play - - - - POP - Power On Password - - - - POST - Power-On Self Test - - - - PR - Privileged bit in the MSR (MSRPR) - - - - Processor Architecture - Used throughout this document to - mean compliance with the requirements specified in - . - - - - Processor revision number - A 16-bit number that distinguishes between various releases - of a particular processor version, for example different engineering change - levels. - - - - PVN - Processor Version Number. Uniquely determines the particular - processor and PA version. - - - - PVR - Processor Version Register. A register in each processor - that identifies its type. The contents of the PVR include the processor - version number and processor revision number. - - - - RAID - Redundant Array of Independent Disks - - - - RAM - Random Access Memory - - - - RAS - Reliability, Availability, and Serviceability - - - - Real address - A real address results from doing address - translation on an effective address when address translation is enabled. - If address translation is not enabled, the real address is the same as the - effective address. An attempt to fetch from, load from, or store to a real - address that is not physically present in the machine may result in a - machine check interrupt. - - - - Reserved - The term “reserved” is used within this - document to refer to bits in registers or areas in the address space - which should not be referenced by software except as described in this - document. - - - - Reserved for firmware use - Refers to a given location or bit which may not be used by - software, but are used by firmware. - - - - Reserved for future use - Refers to areas of address space or bits in registers which may be - used by future versions of this architecture. - - - - RI - Recoverable interrupt bit in the MSR (MSRRI) - - - - RISC - Reduced Instruction Set Computing - - - - RMA - Real Mode Area. The first block of logical memory addresses - owned by a logical partition, containing the storage that may be accessed with - translate off. - - - - ROM - Read Only Memory - - - - Root Complex - A PCI Express root complex as specified in - . - - - - RPN - Real Page Number - - - - RTAS - Run-Time Abstraction Services - - - - RTC - Real Time Clock - - - - SAE - Log Service Action Event log - - - - SCC - Serial Communications Controller - - - - SCSI - Small Computer System Interface - - - - SE - Single-step trace enabled bit in the MSR - (MSRSE) - - - - Service Focal Point - The common point of control in the system for handling all - service actions - - - - Serviceable Event - Serviceable Events are platform, - global, regional and local error events that require a service action - and possibly a call home when the serviceable event must be handled by a - service representative or at least reported to the service provider. - Activation of the Error Log indicator notifies the customer of the event - and the event indicates to the customer that there must be some intervention - to rectify the problem. The intervention may be a service action that the - customer can perform or it may require a service provider. - - - - SES - Storage Enclosure Services (can also mean SCSI Enclosure - Services in relation to SCSI storage) - - - - SF - Processor 32-bit or 64-bit processor mode bit in the MSR - (MSRSF) - - - - SFP - Service Focal Point - - - - Shrink-wrap OS - A single version of an OS that runs on all - compliant platforms. - - - - Shrink-wrap Application - A single version of an application program - that runs on all compliant platforms with the applicable OS. - - - - SMP - Symmetric multiprocessor - - - - SMS - System Management Services - - - - Snarf - An industry colloquialism for cache-to-cache - transfer. A typical scenario is as follows: (1) cache miss from cache A, - (2) line found modified in cache B, (3) cache B performs castout of modified - line, and (4) cache A allocates the modified line as it is being written back - to memory. - - - - Snoop - The act of interrogating a cache for the presence of a - line, usually in response to another party on a shared bus attempting to - allocate that line. - - - - SPRG - Special Purpose Registers for General use - - - - SR - System Registers - - - - SRC - Service Reference Code - - - - SRN - Service Request Number - - - - Store - A Store Request is an - outbound (from the processor) operation. When it relates to I/O - operations, this is an MMIO Store. - - - - System - Refers to the collection of hardware, system firmware, - and OS software which comprise a computer model. - - - - System address space - The total range of addressability as established by the - processor implementation. - - - - System Control Area - Refers to a range of addresses which - contains the system ROM(s) and an unarchitected, reserved, platform-dependent - area used by firmware and Run-Time Abstraction services for control of the - platform. The ROM areas are defined by the OF properties in the - openprom and os-rom nodes - of the OF device tree. - - - - System Information (Attention) indicator - See Error Log indicator. - - - - System firmware - Refers to the collection of all firmware on a system - including OF, RTAS and any legacy firmware. - - - - System Memory - Refers to those areas of memory which form - a coherency domain with respect to the PA processor or processors that - execute application software on a system. - - - - System software - Refers to the combination of OS software, - device driver software, and any hardware abstraction software, but - excludes the application software. - - - - TB - Time Base - - - - TCE - Translation Control Entry - - - - TLB - Translation Look-aside Buffer - - - - TOD - Time Of Day - - - - TOSM - Top of system memory - - - - TPM - Top of Peripheral Memory - Trusted Platform Module - - - - tty - Teletypewriter or ASCII character driven - terminal device - - - - UI - User Interface - - - - USB - Universal Serial Bus - - - - v - Volt - - - - VGA - Video Graphics Array - - - - VMC - Virtual Management Channel - - - - VPD - Vital Product Data - - - - VPNH - Virtual Processor Home Node option. See - - - . - - - - - - - - - - - - - - diff --git a/DeviceTree/bk_main.xml b/DeviceTree/bk_main.xml deleted file mode 100644 index 443f0a5..0000000 --- a/DeviceTree/bk_main.xml +++ /dev/null @@ -1,345 +0,0 @@ - - - - - - - Device Tree Bindings - Linux on Power Architecture Reference - - - - - System Software Work Group - - syssw-chair@openpowerfoundation.org - - OpenPOWER Foundation - - - - 2016, 2018, 2020 - OpenPOWER Foundation - - - Revision 0.5_pre5 - OpenPOWER - - - - - - Copyright details are filled in by the template. - - - - - - The purpose of this document is to provide firmware and software - architectural details associated with Device Tree Bindings on OpenPOWER Systems. - The base content for this document were contributed to the OpenPOWER Foundation in the - IBM Linux on Power Architecture Platform Reference (LoPAPR) Draft - document which detailed Linux running on PowerVM. While this information is not always - immediately applicable to new OpenPOWER modes of bare metal or KVM, many of the - concepts and interfaces remain in some form. Until such time as the document addresses - these new OpenPOWER modes and components, it will remain versioned less than 1.0. It should - also be noted that the original document had numerous contributors inside IBM. - - This document is a Standard Track, Work Group Specification work product owned by the - System Software Workgroup and handled in compliance with the requirements outlined in the - OpenPOWER Foundation Work Group (WG) Process document. It was - created using the Master Template Guide version 0.9.5. Comments, - questions, etc. can be submitted to the public mailing list for this document at - TBD. - - - - - - 2020-04-06 - - - - Revision 0.5_pre5 - Updates to include latest PAPR ACRs (2.9) as follows: - - - Add H_VIOCTL subfunctions for VNIC failover support - - - Add H_VIOCTL subfunction for virtual ethernet MAC scan functionality - - - Add H_VIOCTL subfunctions for virtual scsi and FC mobility preparation functionality - - - ibm,current-associativity-domain property - - - HPT resizing option - KVM only - - - Add Coherent Platform Facilities (CAPI) - - - XIVE Exploitation - - - Add 'OCC online/offline' events to 'IE' error log subsection - - - LPM Redundancy Phase II: Redundancy - - - Add optional sub-queue support to VFC on P9 and newer - - - Increase max num-entries for H_SEND_SUB_CRQ_INDIRECT to 128 - - - Add Virtual Serial Multiplex adapter interfaces - - - Maximum size of Dispatch Trace Log Buffer - - - Eliminate requirement for clearing TCP checksum field for ILLAN checksum calculation - - - Continued Extension of H_Send_Logical_LAN for large send packets - - - Add LPM Capablity keyword to RTAS AIX Support system parameter - - - XIVE Exploitation addition: Add ESB Reset Status to RTAS ibm,read-slot-reset-state2 - - - Add NVDIMM Protection and Encryption State system parameters - - - Change or Remove 0x9 and 0xA event subtypes for 'IE' error log subsection - - - - - Additional, post PAPR 2.9 ACRs as follows: - - - Reserve a range of hcalls to to support Ultravisor - - - Add New CAS Bit For SRIOV Virtual Function (VF) Dynamic DMA Window (DDW) Support - - - Updates to support vTPM 2.0 - - - Update XIVE Legacy hcalls to add H_Function - - - Add NVDIMM Secure Erase Command system parameter - - - Update H_REGISTER_VPA to add H_STATE return code for VPA and SLB shadow buffer. - - - Extend Firmware Assisted Dump for ISA Version 3.0 - - - Add a new return code, H_NOT_AVAILABLE, to start-cpu rtas call - - - Document already-implemented NVRAM variables - - - Update ibm,dynamic-memory-vN flags to include a "Hotplugged Memory" flag - - - - - - - - 2019-01-08 - - - - Revision 0.5_pre4 - Update document type to Work Group Note. Final review ready. - - - - - - 2018-07-30 - - - - Revision 0.5_pre3 - Updates to documentation in preparation for System SW WG review: - - - Reset document version to 0.5 - - - Improved Abstract - - - - - - - - 2017-10-11 - - - - Revision 2.0_pre2 - Updates to include latest PAPR ACRs (2.8) as follows: - - - ISA 2.07 privileged doorbell extensions (9/16/2012) - - - POWER ISA Name Change Category Vector.XOR to Vector.CRYPTO (11/4/2012) - - - Enable Multiple Redirected RDMA mappings per page (3/5/2013) - - - Add Block Invalidate Option (3/5/2013) - - - Implementation Dependent Optimizations (3/13/2013) - - - System Firmware Service Entitlement Date (Warranty Date) Check (4/3/2013) - - - New Function for ibm,change-msi to specify 32 bit MSI (5/14/2013) - - - Remove Client-Architecture-Support bit for UUID option (4/16/2013) - - - AddClient Architecture Support bit for RTAS ibm,change-msi (5/28/2013) - - - Add VNIC Server (5/24/2014) - - - VPA changes for P8 (EBB) (5/24/2013) - - - Add an hcall to clean up the entire MMU hashtable (11/20/2013) - - - Add LPCR[ILE] support to H_SET_MODE (5/31/2013) - - - New Root Node Properties (1/12/2016) - - - Extended Firmware Assisted Dump for P8 Registers (1/24/2014) - - - Sufficient H_COP_OP output buffer (6/21/2014) - - - Extend H_SEND_LOGICAL_LAN for large send packets (6/29/2014) - - - Extend H_GET_MPP_X reporting coalesced pages (8/24/2014) - - - Update ibm,pcie-link-speed-stats property to support PCIe 3.0 link speeds (6/12/2015) - - - Extend ibm,get-system-parameters RTAS to report Energy Management Tuning Parameters (3/18/2015) - - - Additional System Parameters related to mgmt of FW Service Entitlement Warranty period (6/22/2015) - - - Additional System Parameter to read LPAR Name string (10/7/2015) - - - Redesign of properties for DRC information and dynamic memory (7/23/2015) - - - Add additional logical loction code sections (3/4/2016) - - - Add ibm,vnic-client-mac to support vNIC failover (2/29/2016) - - - hcall for registering the process table (3/21/2016) - - - New device tree property for UUID (3/21/2016) - - - Changes for Hotplug RTAS Events (10/24/2016) - - - Support 64-bit PE TCEs in ibm,query-pe-dma-window (7/14/2016) - - - - - - - - 2016-05-04 - - - - Revision 2.0_pre1 - initial conversion from IBM document. Extracted from - Linux on Power Architecture Platform Reference (LoPAPR) version 1.1 dated March 24, - 2016 -- Appendix B (LoPAPR Binding) and Appendix C (PA Processor Binding). - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DeviceTree/ch_introduction.xml b/DeviceTree/ch_introduction.xml deleted file mode 100644 index a3e2417..0000000 --- a/DeviceTree/ch_introduction.xml +++ /dev/null @@ -1,97 +0,0 @@ - - - - - Introduction - - This document specifies the application of OF to an LoPAR System, - including requirements and practices to support unique hardware and - firmware specific to the platform implementation. The core requirements and - practices specified by OF must be augmented by system-specific requirements - to form a complete specification for the firmware implementation of an - LoPAR System. This appendix establishes such additional requirements - pertaining to the platform and the support required by OF. - - This document also specifies the application of OF to a PA Processor - (which covers all PowerPC processors and their successors), including - requirements and practices to support unique firmware specific to a PA - Processor. The core requirements and practices specified by OF must be - augmented by processor-specific requirements to form a complete - specification for the firmware implementation for a PA processor. - - establishes such additional requirements pertaining to the - processor and the support required by OF. - - This document further specifies the application of - IEEE Std 1275-1994 Standard for Boot (Initialization, - Configuration) Firmware, Core Practices and Requirements, - Core Errata, IEEE P1275.7 and appropriate OF Standards - for LoPAR computer systems, including practices for client program - interface and data formats. - -
- General Requirements - An OF implementation for an LoPAR platform shall implement the - core requirements as defined in - , core errata - , the PA Processor-specific - extensions described in - , other appropriate bindings - and/or recommended practices contained in the references (see - ), and the LoPAR Binding - specific extensions described in this appendix. - In addition, an OF implementation for an LoPAR platform shall - implement the - Device Interface, - Client Interface and - User Interface as defined in - . - Some LoPAR Binding property names exceed the OF Base specification - limit of 31 characters. LoPAR OF implementations shall support property - names of at least 47 characters. - -
- -
- Processor Architecture Requirements - - specifies the application of - - - to computer systems that use the PA instruction set, including - instruction-set-specific requirements and practices for debugging, client - program interface and data formats. An implementation of OF for PA shall - implement the core requirements as defined in - and the PA-specific extensions - described in this binding. - This appendix addresses - . The descriptions that follow, - and the relevant sections describing translation features for this binding, - assume that the system’s PA processor(s) implement the entire PA - (that is, all books of - ). Some processors may implement - different Book II-III features; such processors may need a variant of this - binding describing the differences to the mapping functions, etc. - -
- - diff --git a/DeviceTree/pom.xml b/DeviceTree/pom.xml deleted file mode 100644 index b8bed71..0000000 --- a/DeviceTree/pom.xml +++ /dev/null @@ -1,148 +0,0 @@ - - - - - org.openpowerfoundation.docs - workgroup-pom - 1.0.0-SNAPSHOT - ../pom.xml - - 4.0.0 - - - LoPAR-DeviceTree - - jar - - - LoPAR-DeviceTree - - - - - 0 - - - - - - - - - org.openpowerfoundation.docs - - openpowerdocs-maven-plugin - - - - generate-webhelp - - generate-webhelp - - generate-sources - - - ${comments.enabled} - LoPAR-DeviceTree - 1 - UA-17511903-1 - - appendix toc,title - article/appendix nop - article toc,title - book toc,title,figure,table,example,equation - book/appendix nop - book/chapter nop - chapter toc,title - chapter/section nop - section toc - part toc,title - qandadiv toc - qandaset toc - reference toc,title - set toc,title - - - 1 - 3 - 1 - - - LoPAR_DeviceTree - - - LoPAR_DeviceTree - - - workgroupNotes - - - - - - workgroupConfidential - - - - - - review - - - - - - - - true - . - - - bk_main.xml - - - - - ${basedir}/../glossary/glossary-terms.xml - 1 - www.openpowerfoundation.org - - - - - - diff --git a/Error Handling/app_bibliography.xml b/Error Handling/app_bibliography.xml deleted file mode 100644 index 4b48169..0000000 --- a/Error Handling/app_bibliography.xml +++ /dev/null @@ -1,284 +0,0 @@ - - - - - Bibliography - This section lists documents which were referenced in this specification or which provide - additional information, and some useful information for obtaining these documents. Referenced - documents are listed below. When any of the following standards are superseded by an approved - revision, the revision shall apply. - - - - - - Linux on Power Architecture Reference: Platform and Device Tree - - - - - Linux on Power Architecture Reference: Device Tree - - - - - - - Linux on Power Architecture Reference: Virtualization - - - - - Linux on Power Architecture Reference: Runtime Abstraction Services (RTAS) - - - - - Power ISA - - - - - IEEE 1275, IEEE Standard for Boot (Initialization Configuration) Firmware: - Core Requirements and Practices - IEEE part number DS02683, ISBN 1-55937-426-8 - - - - - Core Errata, IEEE P1275.7/D4 - - - - - Open Firmware Recommended Practice:OBP-TFTP - Extension - - - - - Open Firmware Recommended Practice: Device - Support Extensions - - - - - PCI Bus binding to: IEEE Std 1275-1994, Standard - for Boot (Initialization, Configuration) Firmware - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping - - - - - Open Firmware: Recommended Practice - Forth Source - and FCode Image Support, Version 1.0 - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping, Version 1.0 - - - - - Open Firmware: Recommended Practice - TFTP Booting - Extensions, Version 0.8 - - - - - Open Firmware: Recommended Practice - - Interposition, Version 0.2 - - - - - MS-DOS Programmer's Reference - Published by Microsoft - - - - - Peering Inside the PE: A Tour of the Win32 Portable - Executable File Format - Found in the March, 1994 issue of Microsoft Systems Journal - - - - - ISO-9660, Information processing -- Volume and - file structure of CD-ROM for information interchange - Published by International Organization for Standardization - - - - - System V Application Binary Interface, PowerPC - Processor Supplement - By Sunsoft - - - - - ISO Standard 8879:1986, Information Processing - -- Text and Office Systems -- Standard Generalized Markup Language (SGML) - - - - - IEEE 996, A Standard for an Extended Personal Computer - Back Plane Bus - - - - - PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - PCI-to-PCI Bridge Architecture Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the - PCI SIG website for the most current version of this document. - - - - - PCI Standard Hot-Plug Controller and Subsystem - Specification - - - - - PCI-X Protocol Addendum to the PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI-X related components or platforms. See the PCI SIG website for the most - current version of this document. - - - - - PCI Express Base Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design PCI Express related components or platforms. See the PCI SIG website for - the most current version of this document. - - - - - PCI Express to PCI/PCI-X Bridge Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express related components or platforms. See the PCI SIG website for the most current - version of this document. - - - - - System Management BIOS (SMBIOS) Reference - Specification - - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - - IBM RS/6000® Division, Product Topology Data System, - Product Development Guide - Version 2.1 - - - - - Single Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI Express SR-IOV related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - Multi-Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express MR-IOV related components or platforms. See the PCI SIG website for the - most current version of this document. - - - - - - diff --git a/Error Handling/app_glossary.xml b/Error Handling/app_glossary.xml deleted file mode 100644 index 3aae9ef..0000000 --- a/Error Handling/app_glossary.xml +++ /dev/null @@ -1,1290 +0,0 @@ - - - - - Glossary - This glossary contains an alphabetical list of terms, phrases, and abbreviations used in this document. - - - - Term - Definition - - - - AC - Alternating current - - - - ACR - Architecture Change Request - - - - AD - Address Data line - - - - Adapter - A device which attaches a device to a bus or which converts one - bus to another; for example, an I/O Adapter (IOA), a PCI Host Bridge (PHB), - or a NUMA fabric attachment device. - - - - - addr - Address - - - - Architecture - The hardware/software interface definition or software module to - software module interface definition. - - - - ASCII - American National Standards Code for Information - Interchange - - - - ASR - Address Space Register - - - - BAT - Block Address Translation - - - - BE - Big-Endian or Branch Trace Enable bit in the - MSR (MSRBE) - - - - BIO - Bottom of Peripheral Input/Output Space - - - - BIOS - Basic Input/Output system - - - - BIST - Built in Self Test - - - - Boundedly undefined - Describes some addresses and registers which when referenced provide - one of a small set of predefined results. - - - - BPA - Bulk Power Assembly. Refers to components used for power distribution - from a central point in the rack. - - - - BPM - Bottom of Peripheral Memory - - - - BSCA - Bottom of System Control Area - - - - BSM - Bottom of System Memory - - - - BUID - Bus Unit Identifier. The high-order part of an interrupt source number - which is used for hardware routing purposes by the platform. - - - - CCIN - Custom Card Identification Number - - - - CD-ROM - Compact Disk Read-Only Memory - - - - CIS - Client Interface Service - - - - CMO - Cooperative Memory Over-commitment option. See - for more information. - - - - - - CMOS - Complimentary Metal Oxide Semiconductor - - - - Conventional PCI - Behavior or features that conform to . - - - - CPU - Central Processing Unit - - - - CR - Condition Register - - - - CTR - Count Register - - - - DABR - Data Address Breakpoint Register - - - - DAR - Data Address Register - - - - DASD - Direct Access Storage Device (a synonym for “hard disk”) - - - - DBAT - Data Block Address Translation - - - - DC - Direct current - - - - DEC - Decrementer - - - - DIMM - Dual In-line Memory Module - - - - DMA - Direct Memory Access - - - - DMA Read - A data transfer from System Memory to I/O. A DMA Read Request - is the inbound operation and the DMA Read Reply (or Read Completion) is the - outbound data coming back from a DMA Read Request. - - - - DMA Write - A data transfer to System Memory from I/O or a Message Signalled Interrupt (MSI) DMA Write. This is an inbound operation. - - - - DOS - Disk OS - - - - DR - Data Relocate bit in MSR (MSRDR) - - - - DRA - Deviation Risk Assessment - - - - DRAM - Dynamic Random Access Memory - - - - DRC - Delayed Read Completion. A transaction that has completed - on the destination bus and is now moving toward the originating bus to complete. - DR Connector. - - - - DR entity - An entity that can participate in DR operations. That is, an entity - that can be added or removed from the platform while the platform power is on and the - system remains operational. - - - - DRR - Delayed Read Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - DSISR - Data Storage Interrupt Status Register - - - - DWR - Delayed Write Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - EA - Effective Address - - - - EAR - External Access Register - - - - ECC - Error Checking and Correction - - - - EE - External interrupt Enable bit in the MSR (MSREE) - - - - EEH - Enhance I/O Error Handling - - - - EEPROM - Electrically Erasable Programmable Read Only Memory - - - - EPOW - Environment and Power Warning - - - - - Error Log indicator An amber indicator that indicates that the user needs to - look at the error log or problem determination procedures, in order to determine the cause. - Previously called System Information (Attention). - - - - FCode - A computer programming language defined by the OF standard which is semantically - similar to the Forth programming language, but is encoded as a sequence of binary byte codes - representing a defined set of Forth words. - - - - FE0 - Floating-point Exception mode 0 bit in the MSR (MSRFE0) - - - - FE1 - Floating-point Exception mode 1bit in the MSR (MSRFE1) - - - - FIR - Fault Isolation Registers - - - - FLR - Function Level Reset (see PCI Express documentation). An optional reset for PCI Express - functions that allows resetting a single function of a multi-function IOA. - - - - FP - Floating-Point available bit in the MSR (MSRFP) - - - - FPSCR - Floating-Point Status And Control Register - - - - FRU - Field Replaceable Unit - - - - FSM - Finite State Machine - - - - GB - Gigabytes - as used in this document it is 2 raised to the power of 30 - - - - HB - Host Bridge - - - - HMC - Hardware Management Console - used generically to refer to the system - component that performs platform administration function where ever physically located. - The HMC is outside of this architecture and may be implemented in multiple ways. - Examples include: a special HMC applications in another system, an external appliance, - or in an LPAR partition using the Virtual Management Channel (VMC) interface to the - hypervisor. - - - - Hz - Hertz - - - - IBAT - Instruction block address translation - - - - ID - Identification - - - - IDE - Integrated Device Electronics - - - - IDU - Interrupt Delivery Unit - - - - IEEE - Institute of Electrical and Electronics Engineers - - - - I2C - Inter Integrated-circuit Communications - - - - I/O - nput/Output - - - - I/O bus master - Any entity other than a processor, cache, - memory controller, or host bridge which supplies both address and data in - write transactions or supplies the address and is the sink for the data in - read transactions. - - - - I/O device - Generally refers to any entity that is connected - to an IOA (usually through a cable), but in some cases may refer to the IOA - itself (that is, a device in the device tree that happens to be used for I/O - operations). - - - - I/O Drawer - An enclosure in a rack that holds at least one PHB and at - least one IOA. - - - - ILE - Interrupt Little-Endian bit in MSR (MSRILE) - - - - Instr - Instruction - - - - Interrupt Number - See Interrupt Vector below. - - - - Interrupt Vector - The identifier associated with a specific interrupt source. - The identifier’s value is loaded into the source’s Interrupt Vector Register and - is read from the Interrupt Delivery Unit’s Interrupt Acknowledge Register. - - - - IOA - I/O Adapter. A device which attaches to a physical bus which is capable - of supporting I/O (a physical IOA) or logical bus (a virtual IOA). The term “IOA” - without the usage of the qualifier “physical” or “virtual” will be - used to designate a physical IOA. Virtual IOAs are defined further in - - . - In PCI terms, an IOA may be defined by a unique combination of its assigned - bus number and device number, but not necessarily including its function number. - That is, an IOA may be a single or multi-function device, unless otherwise specified by - the context of the text. In the context of a PCIe I/O Virtualized (IOV) device (not to be - confused with a virtual IOA), an IOA is a single or multiple function device (for example, a - PCIe Virtual Function (VF) or multiple VFs). An IOA function may or may not have its own set of - resources, that is may or may not be in its own Partitionable Endpoint (PE) domain - (see also - - ). - - - - - IOA function - That part of an IOA that deals with a specific part of the - IOA as defined by the configuration space “Function” part of Bus/Device/Function. - For single-function IOAs, the IOA Function and the IOA are synonymous. - - - - IP - Interrupt Prefix bit in MSR (MSRIP) - - - - IPI - Interprocessor Interrupt - - - - IR - Instruction Relocate bit in MSR register (MSRIR) or infrared - - - - ISF - Interrupt 64-bit processor mode bit in the MSR (MSRISF) - - - - ISO - International Standards Organization - - - - ISR - Interrupt Source Register - - - - ISU - Interrupt Source Unit - - - - KB - Kilobytes - as used in this document it is 2 raised to the power of 10 - - - - KHz - Kilo Hertz - - - - LAN - Local Area Network - - - - LCD - Liquid Crystal Display - - - - LE - Little-Endian bit in MSR (MSRLE) or Little-Endian - - - - LED - Light Emitting Diode - - - - LMB - Logical Memory Block. The Block of logical memory addresses associated with a dynamically - reconfigurable memory node. - - - - Load - A Load Request is the outbound (from the processor) operation - and the Load Reply is the inbound data coming back from a - Load Request. When it relates to I/O operations, this is an - MMIO Load . - - - - LR - Link Register - - - - LSb - Least Significant bit - - - - LSB - Least Significant Byte - - - - LSI - Level Sensitive Interrupt - - - - LUN - Logical Unit Number - - - - L1 - Primary cache - - - - L2 - Secondary cache - - - - MB - Megabytes - as used in this document it is 2 raised to the power of 20 - - - - ME - Machine check Enable - - - - MMIO - Memory Mapped I/O. This refers to the mapping of the address space required - by an I/O device for Load or Store operations into - the system’s address space. - - - - MES - Miscellaneous Equipment Specification - - - - MFM - Modified frequency modulation - - - - MHz - Mega Hertz - - - - MOD - Address modification bit in the MSR - (MSRMOD) - - - - MP - Multiprocessor - - - - MSb - Most Significant bit - - - - MSB - Most Significant Byte - - - - MSI - Message Signalled Interrupt - - - - MSR - Machine State Register - - - - MTT - Multi-TCE-Table option. See - - - . - - - - - N/A - Not Applicable - - - - Nibble - Refers to the first or last four bits in an 8 bit byte - - - - NUMA - Non-Uniform Memory Access - - - - NUMA fabric - Mechanism and method for connecting the multiple nodes of a NUMA system - - - - NVRAM - Nonvolatile Random Access Memory - - - - OF - Open Firmware - - - - OP - Operator - - - - OS - Operating System - - - - OUI - Organizationally Unique Identifier - - - - PA - Processor Architecture - - - - PAP - Privileged Access Password - - - - LoPAR - Used within the Linux on Power Architecture - Reference documents to denote: (1) the architectural requirements specified - by the Linux on Power Architecture Reference document, (2) the Linux on Power Architecture - Reference documents themself, and (3) as an adjective to qualify an entity as being - related to this architecture. - - - - Partitionable Endpoint - This refers to the I/O granule that may be treated as one for - purposes of assignment to an OS (for example, to an LPAR partition). May be an - I/O adapter (IOA), or groups of IOAs and bridges, or portions of IOAs. PE granularity - supported by the hardware may be finer than is supported by the firmware. Grouping - of multiple PEs into one DR entity may limit assignment of a the separate PEs to different - LPAR partitions. See also DR entity. - - - - PC - Personal Computer - - - - PCI - Peripheral Component Interconnect. An all-encompassing term referring to - conventional PCI, PCI-X, and PCI Express. - - - - PCI bus - A general term referring to either the PCI Local Bus, as - specified in and - for conventional PCI and PCI-X, or a PCI Express link, as specified in - for PCI Express. - - - - PCI Express - Behavior or features that conform to - . - - - - PCI link - A PCI Express link, as specified in . - - - - PCI-X - Behavior or features that conform to . - - - - PD - Presence Detect - - - - PE - When referring to the body of the LoPAR, this refers to a Partitionable - Endpoint. - - - - - - - PEM - Partition Energy Management option. See - - - . - - - - - Peripheral I/O Space - The range of real addresses which are assigned - to the I/O Space of a Host Bridge (HB) and which are sufficient to contain all of - the Load and Store address space requirements of all the devices in the I/O Space - of the I/O bus that is generated by the HB. A keyboard controller is an example of - a device which may require Peripheral I/O Space addresses. - - - - Peripheral Memory Space - The range of real addresses which are assigned to the Memory - Space of a Host Bridge (HB) and which are sufficient to contain all of the Load and - Store address space requirements of the devices in the Memory Space of the I/O bus - that is generated by the HB. The frame buffer of a graphics adapter is an example - of a device which may require Peripheral Memory Space addresses. - - - - Peripheral Space - Refers to the physical address space which may - be accessed by a processor, but which is controlled by a host bridge. At least one - peripheral space must be present and it is referred to by the suffix 0. A host bridge - will typically provide access to at least a memory space and possibly to an I/O - space. - - - - PHB - PCI Host Bridge - - - - PIC - Programmable Interrupt Controller - - - - PIR - Processor Identification Register - - - - Platform - Refers to the hardware plus firmware portion of a system composed of hardware, - firmware, and OS. - - - - Platform firmware - Refers to all firmware on a system including the software or firmware in a - support processor. - - - - Plug-in I/O card - A card which can be plugged into an I/O - connector in a platform and which contains one or more IOAs and potentially - one or more I/O bridges or switches. - - - - Plug-in Card - An entity that plugs into a physical slot. - - - - PMW - Posted memory write. A transaction that has complete on the - originating bus before completing on the destination bus - - - - PnP - Plug and Play - - - - POP - Power On Password - - - - POST - Power-On Self Test - - - - PR - Privileged bit in the MSR (MSRPR) - - - - Processor Architecture - Used throughout this document to - mean compliance with the requirements specified in - . - - - - Processor revision number - A 16-bit number that distinguishes between various releases - of a particular processor version, for example different engineering change - levels. - - - - PVN - Processor Version Number. Uniquely determines the particular - processor and PA version. - - - - PVR - Processor Version Register. A register in each processor - that identifies its type. The contents of the PVR include the processor - version number and processor revision number. - - - - RAID - Redundant Array of Independent Disks - - - - RAM - Random Access Memory - - - - RAS - Reliability, Availability, and Serviceability - - - - Real address - A real address results from doing address - translation on an effective address when address translation is enabled. - If address translation is not enabled, the real address is the same as the - effective address. An attempt to fetch from, load from, or store to a real - address that is not physically present in the machine may result in a - machine check interrupt. - - - - Reserved - The term “reserved” is used within this - document to refer to bits in registers or areas in the address space - which should not be referenced by software except as described in this - document. - - - - Reserved for firmware use - Refers to a given location or bit which may not be used by - software, but are used by firmware. - - - - Reserved for future use - Refers to areas of address space or bits in registers which may be - used by future versions of this architecture. - - - - RI - Recoverable interrupt bit in the MSR (MSRRI) - - - - RISC - Reduced Instruction Set Computing - - - - RMA - Real Mode Area. The first block of logical memory addresses - owned by a logical partition, containing the storage that may be accessed with - translate off. - - - - ROM - Read Only Memory - - - - Root Complex - A PCI Express root complex as specified in - . - - - - RPN - Real Page Number - - - - RTAS - Run-Time Abstraction Services - - - - RTC - Real Time Clock - - - - SAE - Log Service Action Event log - - - - SCC - Serial Communications Controller - - - - SCSI - Small Computer System Interface - - - - SE - Single-step trace enabled bit in the MSR - (MSRSE) - - - - Service Focal Point - The common point of control in the system for handling all - service actions - - - - Serviceable Event - Serviceable Events are platform, - global, regional and local error events that require a service action - and possibly a call home when the serviceable event must be handled by a - service representative or at least reported to the service provider. - Activation of the Error Log indicator notifies the customer of the event - and the event indicates to the customer that there must be some intervention - to rectify the problem. The intervention may be a service action that the - customer can perform or it may require a service provider. - - - - SES - Storage Enclosure Services (can also mean SCSI Enclosure - Services in relation to SCSI storage) - - - - SF - Processor 32-bit or 64-bit processor mode bit in the MSR - (MSRSF) - - - - SFP - Service Focal Point - - - - Shrink-wrap OS - A single version of an OS that runs on all - compliant platforms. - - - - Shrink-wrap Application - A single version of an application program - that runs on all compliant platforms with the applicable OS. - - - - SMP - Symmetric multiprocessor - - - - SMS - System Management Services - - - - Snarf - An industry colloquialism for cache-to-cache - transfer. A typical scenario is as follows: (1) cache miss from cache A, - (2) line found modified in cache B, (3) cache B performs castout of modified - line, and (4) cache A allocates the modified line as it is being written back - to memory. - - - - Snoop - The act of interrogating a cache for the presence of a - line, usually in response to another party on a shared bus attempting to - allocate that line. - - - - SPRG - Special Purpose Registers for General use - - - - SR - System Registers - - - - SRC - Service Reference Code - - - - SRN - Service Request Number - - - - Store - A Store Request is an - outbound (from the processor) operation. When it relates to I/O - operations, this is an MMIO Store. - - - - System - Refers to the collection of hardware, system firmware, - and OS software which comprise a computer model. - - - - System address space - The total range of addressability as established by the - processor implementation. - - - - System Control Area - Refers to a range of addresses which - contains the system ROM(s) and an unarchitected, reserved, platform-dependent - area used by firmware and Run-Time Abstraction services for control of the - platform. The ROM areas are defined by the OF properties in the - openprom and os-rom nodes - of the OF device tree. - - - - System Information (Attention) indicator - See Error Log indicator. - - - - System firmware - Refers to the collection of all firmware on a system - including OF, RTAS and any legacy firmware. - - - - System Memory - Refers to those areas of memory which form - a coherency domain with respect to the PA processor or processors that - execute application software on a system. - - - - System software - Refers to the combination of OS software, - device driver software, and any hardware abstraction software, but - excludes the application software. - - - - TB - Time Base - - - - TCE - Translation Control Entry - - - - TLB - Translation Look-aside Buffer - - - - TOD - Time Of Day - - - - TOSM - Top of system memory - - - - TPM - Top of Peripheral Memory - Trusted Platform Module - - - - tty - Teletypewriter or ASCII character driven - terminal device - - - - UI - User Interface - - - - USB - Universal Serial Bus - - - - v - Volt - - - - VGA - Video Graphics Array - - - - VMC - Virtual Management Channel - - - - VPD - Vital Product Data - - - - VPNH - Virtual Processor Home Node option. See - - - . - - - - - - - - - - - - - - diff --git a/Error Handling/bk_main.xml b/Error Handling/bk_main.xml deleted file mode 100644 index b192c62..0000000 --- a/Error Handling/bk_main.xml +++ /dev/null @@ -1,348 +0,0 @@ - - - - - - - Error Handling - Linux on Power Architecture Reference - - - - - System Software Work Group - - syssw-chair@openpowerfoundation.org - - OpenPOWER Foundation - - - - 2016, 2018, 2020 - OpenPOWER Foundation - - - Revision 0.5_pre5 - OpenPOWER - - - - - - Copyright details are filled in by the template. - - - - - - The purpose of this document is to provide firmware and software - architectural details associated with Error Recovery and Logging on OpenPOWER Systems. - The base content for this document were contributed to the OpenPOWER Foundation in the - IBM Linux on Power Architecture Platform Reference (LoPAPR) Draft - document which detailed Linux running on PowerVM. While this information is not always - immediately applicable to new OpenPOWER modes of bare metal or KVM, many of the - concepts and interfaces remain in some form. Until such time as the document addresses - these new OpenPOWER modes and components, it will remain versioned less than 1.0. It should - also be noted that the original document had numerous contributors inside IBM. - - This document is a Standard Track, Work Group Specification work product owned by the - System Software Workgroup and handled in compliance with the requirements outlined in the - OpenPOWER Foundation Work Group (WG) Process document. It was - created using the Master Template Guide version 0.9.5. Comments, - questions, etc. can be submitted to the public mailing list for this document at - TBD. - - - - - - 2020-04-06 - - - - Revision 0.5_pre5 - Updates to include latest PAPR ACRs (2.9) as follows: - - - Add H_VIOCTL subfunctions for VNIC failover support - - - Add H_VIOCTL subfunction for virtual ethernet MAC scan functionality - - - Add H_VIOCTL subfunctions for virtual scsi and FC mobility preparation functionality - - - ibm,current-associativity-domain property - - - HPT resizing option - KVM only - - - Add Coherent Platform Facilities (CAPI) - - - XIVE Exploitation - - - Add 'OCC online/offline' events to 'IE' error log subsection - - - LPM Redundancy Phase II: Redundancy - - - Add optional sub-queue support to VFC on P9 and newer - - - Increase max num-entries for H_SEND_SUB_CRQ_INDIRECT to 128 - - - Add Virtual Serial Multiplex adapter interfaces - - - Maximum size of Dispatch Trace Log Buffer - - - Eliminate requirement for clearing TCP checksum field for ILLAN checksum calculation - - - Continued Extension of H_Send_Logical_LAN for large send packets - - - Add LPM Capablity keyword to RTAS AIX Support system parameter - - - XIVE Exploitation addition: Add ESB Reset Status to RTAS ibm,read-slot-reset-state2 - - - Add NVDIMM Protection and Encryption State system parameters - - - Change or Remove 0x9 and 0xA event subtypes for 'IE' error log subsection - - - - - Additional, post PAPR 2.9 ACRs as follows: - - - Reserve a range of hcalls to to support Ultravisor - - - Add New CAS Bit For SRIOV Virtual Function (VF) Dynamic DMA Window (DDW) Support - - - Updates to support vTPM 2.0 - - - Update XIVE Legacy hcalls to add H_Function - - - Add NVDIMM Secure Erase Command system parameter - - - Update H_REGISTER_VPA to add H_STATE return code for VPA and SLB shadow buffer. - - - Extend Firmware Assisted Dump for ISA Version 3.0 - - - Add a new return code, H_NOT_AVAILABLE, to start-cpu rtas call - - - Document already-implemented NVRAM variables - - - Update ibm,dynamic-memory-vN flags to include a "Hotplugged Memory" flag - - - - - - - - 2019-01-08 - - - - Revision 0.5_pre4 - Update document type to Work Group Note. Final review ready. - - - - - - 2018-07-30 - - - - Revision 0.5_pre3 - Updates to documentation in preparation for System SW WG review: - - - Reset document version to 0.5 - - - Improved Abstract - - - - - - - - 2017-10-11 - - - - Revision 2.0_pre2 - Updates to include latest PAPR ACRs (2.8) as follows: - - - ISA 2.07 privileged doorbell extensions (9/16/2012) - - - POWER ISA Name Change Category Vector.XOR to Vector.CRYPTO (11/4/2012) - - - Enable Multiple Redirected RDMA mappings per page (3/5/2013) - - - Add Block Invalidate Option (3/5/2013) - - - Implementation Dependent Optimizations (3/13/2013) - - - System Firmware Service Entitlement Date (Warranty Date) Check (4/3/2013) - - - New Function for ibm,change-msi to specify 32 bit MSI (5/14/2013) - - - Remove Client-Architecture-Support bit for UUID option (4/16/2013) - - - AddClient Architecture Support bit for RTAS ibm,change-msi (5/28/2013) - - - Add VNIC Server (5/24/2014) - - - VPA changes for P8 (EBB) (5/24/2013) - - - Add an hcall to clean up the entire MMU hashtable (11/20/2013) - - - Add LPCR[ILE] support to H_SET_MODE (5/31/2013) - - - New Root Node Properties (1/12/2016) - - - Extended Firmware Assisted Dump for P8 Registers (1/24/2014) - - - Sufficient H_COP_OP output buffer (6/21/2014) - - - Extend H_SEND_LOGICAL_LAN for large send packets (6/29/2014) - - - Extend H_GET_MPP_X reporting coalesced pages (8/24/2014) - - - Update ibm,pcie-link-speed-stats property to support PCIe 3.0 link speeds (6/12/2015) - - - Extend ibm,get-system-parameters RTAS to report Energy Management Tuning Parameters (3/18/2015) - - - Additional System Parameters related to mgmt of FW Service Entitlement Warranty period (6/22/2015) - - - Additional System Parameter to read LPAR Name string (10/7/2015) - - - Redesign of properties for DRC information and dynamic memory (7/23/2015) - - - Add additional logical loction code sections (3/4/2016) - - - Add ibm,vnic-client-mac to support vNIC failover (2/29/2016) - - - hcall for registering the process table (3/21/2016) - - - New device tree property for UUID (3/21/2016) - - - Changes for Hotplug RTAS Events (10/24/2016) - - - Support 64-bit PE TCEs in ibm,query-pe-dma-window (7/14/2016) - - - - - - - - 2016-05-04 - - - - Revision 2.0_pre1 - initial conversion from IBM document. Extracted from - Linux on Power Architecture Platform Reference (LoPAPR) version 1.1 dated March 24, - 2016 -- Section 7.3.3 ([RTAS] Error and Event Reporting), Chapter 10 (Error and - Event Notification), Sections 1-3 of Chapter 16 (Service Indicators), and - Appendix L (When to use: Fault vs. Error Log Indicators). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Error Handling/pom.xml b/Error Handling/pom.xml deleted file mode 100644 index f3edcf3..0000000 --- a/Error Handling/pom.xml +++ /dev/null @@ -1,148 +0,0 @@ - - - - - org.openpowerfoundation.docs - workgroup-pom - 1.0.0-SNAPSHOT - ../pom.xml - - 4.0.0 - - - LoPAR-Error - - jar - - - LoPAR-Error - - - - - 0 - - - - - - - - - org.openpowerfoundation.docs - - openpowerdocs-maven-plugin - - - - generate-webhelp - - generate-webhelp - - generate-sources - - - ${comments.enabled} - LoPAR-Error - 1 - UA-17511903-1 - - appendix toc,title - article/appendix nop - article toc,title - book toc,title,figure,table,example,equation - book/appendix nop - book/chapter nop - chapter toc,title - chapter/section nop - section toc - part toc,title - qandadiv toc - qandaset toc - reference toc,title - set toc,title - - - 1 - 3 - 1 - - - LoPAR_Error_Handling - - - LoPAR_Error_Handling - - - workgroupNotes - - - - - - workgroupConfidential - - - - - - review - - - - - - - - true - . - - - bk_main.xml - - - - - ${basedir}/../glossary/glossary-terms.xml - 1 - www.openpowerfoundation.org - - - - - - diff --git a/Error Handling/sec_error_reporting.xml b/Error Handling/sec_error_reporting.xml deleted file mode 100644 index 837388c..0000000 --- a/Error Handling/sec_error_reporting.xml +++ /dev/null @@ -1,87 +0,0 @@ - - -
- - Error and Event Reporting - - The error and event reporting RTAS calls are designed to provide an - abstract interface into hardware registers in the system that may contain - correctable or non-correctable errors and to provide an abstract interface - to certain platform events that may be of interest to the OS. Such errors - and events may be detected either by a periodic scan or by an exception trap. - - - These functions are not intended to replace the normal error handling - in the OS. Rather, they enhance the OS’s abilities by providing an - abstract interface to check for, report, and recover from errors or events - on the platform that are not necessarily known to the OS. - - The OS uses the error and event RTAS calls in two distinct ways: - - - - - Periodically, the OS calls event-scan - to have - the system firmware check for any errors or events that have occurred. - - - - - Whenever the OS receives an interrupt or exception that it cannot - fully process, it calls check-exception. - - - - - The first case covers all errors and events that do not signal their - occurrence with an interrupt or exception. The second case covers those - errors and events that do signal with an interrupt or exception. It is - platform dependent whether any specific error or event causes an interrupt - on that platform. - - - - - R1--1. - - RTAS must return the event generated by a - particular interrupt or event source by either - check-exception or event-scan, - but not both. - - - - - R1--2. - - check-exception - and event-scan , on a 64-bit capable platform, must - be able to handle platform resources that are accessed using 64-bit - addresses when instantiated in 32-bit mode. - - - - -
diff --git a/Platform/bk_main.xml b/Platform/bk_main.xml deleted file mode 100644 index 7a1aa88..0000000 --- a/Platform/bk_main.xml +++ /dev/null @@ -1,357 +0,0 @@ - - - - - - - Platform - Linux on Power Architecture Reference - - - - - System Software Work Group - - syssw-chair@openpowerfoundation.org - - OpenPOWER Foundation - - - - 2016, 2018, 2020 - OpenPOWER Foundation - - - Revision 0.5_pre5 - OpenPOWER - - - - - - Copyright details are filled in by the template. - - - - - - The purpose of this document is to provide firmware and software - architectural details for the base Platform hardware associated with an OpenPOWER Systems. - The base content for this document were contributed to the OpenPOWER Foundation in the - IBM Linux on Power Architecture Platform Reference (LoPAPR) Draft - document which detailed Linux running on PowerVM. While this information is not always - immediately applicable to new OpenPOWER modes of bare metal or KVM, many of the - concepts and interfaces remain in some form. Until such time as the document addresses - these new OpenPOWER modes and components, it will remain versioned less than 1.0. It should - also be noted that the original document had numerous contributors inside IBM. - - This document is a Standard Track, Work Group Specification work product owned by the - System Software Workgroup and handled in compliance with the requirements outlined in the - OpenPOWER Foundation Work Group (WG) Process document. It was - created using the Master Template Guide version 0.9.5. Comments, - questions, etc. can be submitted to the public mailing list for this document at - TBD. - - - - - - 2020-04-06 - - - - Revision 0.5_pre5 - Updates to include latest PAPR ACRs (2.9) as follows: - - - Add H_VIOCTL subfunctions for VNIC failover support - - - Add H_VIOCTL subfunction for virtual ethernet MAC scan functionality - - - Add H_VIOCTL subfunctions for virtual scsi and FC mobility preparation functionality - - - ibm,current-associativity-domain property - - - HPT resizing option - KVM only - - - Add Coherent Platform Facilities (CAPI) - - - XIVE Exploitation - - - Add 'OCC online/offline' events to 'IE' error log subsection - - - LPM Redundancy Phase II: Redundancy - - - Add optional sub-queue support to VFC on P9 and newer - - - Increase max num-entries for H_SEND_SUB_CRQ_INDIRECT to 128 - - - Add Virtual Serial Multiplex adapter interfaces - - - Maximum size of Dispatch Trace Log Buffer - - - Eliminate requirement for clearing TCP checksum field for ILLAN checksum calculation - - - Continued Extension of H_Send_Logical_LAN for large send packets - - - Add LPM Capablity keyword to RTAS AIX Support system parameter - - - XIVE Exploitation addition: Add ESB Reset Status to RTAS ibm,read-slot-reset-state2 - - - Add NVDIMM Protection and Encryption State system parameters - - - Change or Remove 0x9 and 0xA event subtypes for 'IE' error log subsection - - - - - Additional, post PAPR 2.9 ACRs as follows: - - - Reserve a range of hcalls to to support Ultravisor - - - Add New CAS Bit For SRIOV Virtual Function (VF) Dynamic DMA Window (DDW) Support - - - Updates to support vTPM 2.0 - - - Update XIVE Legacy hcalls to add H_Function - - - Add NVDIMM Secure Erase Command system parameter - - - Update H_REGISTER_VPA to add H_STATE return code for VPA and SLB shadow buffer. - - - Extend Firmware Assisted Dump for ISA Version 3.0 - - - Add a new return code, H_NOT_AVAILABLE, to start-cpu rtas call - - - Document already-implemented NVRAM variables - - - Update ibm,dynamic-memory-vN flags to include a "Hotplugged Memory" flag - - - - - - - - 2019-01-08 - - - - Revision 0.5_pre4 - Update document type to Work Group Note. Final review ready. - - - - - - 2018-07-30 - - - - Revision 0.5_pre3 - Updates to documentation in preparation for System SW WG review: - - - Reset document version to 0.5 - - - Improved Abstract - - - - - - - - 2017-10-11 - - - - Revision 2.0_pre2 - Updates to include latest PAPR ACRs (2.8) as follows: - - - ISA 2.07 privileged doorbell extensions (9/16/2012) - - - POWER ISA Name Change Category Vector.XOR to Vector.CRYPTO (11/4/2012) - - - Enable Multiple Redirected RDMA mappings per page (3/5/2013) - - - Add Block Invalidate Option (3/5/2013) - - - Implementation Dependent Optimizations (3/13/2013) - - - System Firmware Service Entitlement Date (Warranty Date) Check (4/3/2013) - - - New Function for ibm,change-msi to specify 32 bit MSI (5/14/2013) - - - Remove Client-Architecture-Support bit for UUID option (4/16/2013) - - - AddClient Architecture Support bit for RTAS ibm,change-msi (5/28/2013) - - - Add VNIC Server (5/24/2014) - - - VPA changes for P8 (EBB) (5/24/2013) - - - Add an hcall to clean up the entire MMU hashtable (11/20/2013) - - - Add LPCR[ILE] support to H_SET_MODE (5/31/2013) - - - New Root Node Properties (1/12/2016) - - - Extended Firmware Assisted Dump for P8 Registers (1/24/2014) - - - Sufficient H_COP_OP output buffer (6/21/2014) - - - Extend H_SEND_LOGICAL_LAN for large send packets (6/29/2014) - - - Extend H_GET_MPP_X reporting coalesced pages (8/24/2014) - - - Update ibm,pcie-link-speed-stats property to support PCIe 3.0 link speeds (6/12/2015) - - - Extend ibm,get-system-parameters RTAS to report Energy Management Tuning Parameters (3/18/2015) - - - Additional System Parameters related to mgmt of FW Service Entitlement Warranty period (6/22/2015) - - - Additional System Parameter to read LPAR Name string (10/7/2015) - - - Redesign of properties for DRC information and dynamic memory (7/23/2015) - - - Add additional logical loction code sections (3/4/2016) - - - Add ibm,vnic-client-mac to support vNIC failover (2/29/2016) - - - hcall for registering the process table (3/21/2016) - - - New device tree property for UUID (3/21/2016) - - - Changes for Hotplug RTAS Events (10/24/2016) - - - Support 64-bit PE TCEs in ibm,query-pe-dma-window (7/14/2016) - - - - - - - - 2016-05-04 - - - - Revision 2.0_pre1 - initial conversion from IBM document. Extracted from - Linux on Power Architecture Platform Reference (LoPAPR) version 1.1 dated March 24, - 2016 -- Chapter 1 (Introduction), Chapter 2 (System Requirements), - Chapter 3 (Address Map), Chapter 4 (I/O Bridges and Topology), - Chapter 5 (Processors and Memory), Chapter 6 (Interrupt Controller), - Chapter 8 (Non-volatile memory), Chapter 9 (I/O Devices), - Chapter 11 (The Symmetric Multiprocessor Option), Chapter 12 (Product Topology), - and Appendix H (Non-Uniform Memory Access [NUMA] Option). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Platform/pom.xml b/Platform/pom.xml deleted file mode 100644 index 85b86a8..0000000 --- a/Platform/pom.xml +++ /dev/null @@ -1,148 +0,0 @@ - - - - - org.openpowerfoundation.docs - workgroup-pom - 1.0.0-SNAPSHOT - ../pom.xml - - 4.0.0 - - - LoPAR-Platform - - jar - - - LoPAR-Platform - - - - - 0 - - - - - - - - - org.openpowerfoundation.docs - - openpowerdocs-maven-plugin - - - - generate-webhelp - - generate-webhelp - - generate-sources - - - ${comments.enabled} - LoPAR-Platform - 1 - UA-17511903-1 - - appendix toc,title - article/appendix nop - article toc,title - book toc,title,figure,table,example,equation - book/appendix nop - book/chapter nop - chapter toc,title - chapter/section nop - section toc - part toc,title - qandadiv toc - qandaset toc - reference toc,title - set toc,title - - - 1 - 3 - 1 - - - LoPAR_Platform - - - LoPAR_Platform - - - workgroupNotes - - - - - - workgroupConfidential - - - - - - review - - - - - - - - true - . - - - bk_main.xml - - - - - ${basedir}/../glossary/glossary-terms.xml - 1 - www.openpowerfoundation.org - - - - - - diff --git a/RTAS/app_bibliography.xml b/RTAS/app_bibliography.xml deleted file mode 100644 index 0c73bb3..0000000 --- a/RTAS/app_bibliography.xml +++ /dev/null @@ -1,284 +0,0 @@ - - - - - Bibliography - This section lists documents which were referenced in this specification or which provide - additional information, and some useful information for obtaining these documents. Referenced - documents are listed below. When any of the following standards are superseded by an approved - revision, the revision shall apply. - - - - - - Linux on Power Architecture Reference: Platform and Device Tree - - - - - Linux on Power Architecture Reference: Device Tree - - - - - Linux on Power Architecture Reference: Error Recovery and Logging - - - - - Linux on Power Architecture Reference: Virtualization - - - - - - - Power ISA - - - - - IEEE 1275, IEEE Standard for Boot (Initialization Configuration) Firmware: - Core Requirements and Practices - IEEE part number DS02683, ISBN 1-55937-426-8 - - - - - Core Errata, IEEE P1275.7/D4 - - - - - Open Firmware Recommended Practice:OBP-TFTP - Extension - - - - - Open Firmware Recommended Practice: Device - Support Extensions - - - - - PCI Bus binding to: IEEE Std 1275-1994, Standard - for Boot (Initialization, Configuration) Firmware - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping - - - - - Open Firmware: Recommended Practice - Forth Source - and FCode Image Support, Version 1.0 - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping, Version 1.0 - - - - - Open Firmware: Recommended Practice - TFTP Booting - Extensions, Version 0.8 - - - - - Open Firmware: Recommended Practice - - Interposition, Version 0.2 - - - - - MS-DOS Programmer's Reference - Published by Microsoft - - - - - Peering Inside the PE: A Tour of the Win32 Portable - Executable File Format - Found in the March, 1994 issue of Microsoft Systems Journal - - - - - ISO-9660, Information processing -- Volume and - file structure of CD-ROM for information interchange - Published by International Organization for Standardization - - - - - System V Application Binary Interface, PowerPC - Processor Supplement - By Sunsoft - - - - - ISO Standard 8879:1986, Information Processing - -- Text and Office Systems -- Standard Generalized Markup Language (SGML) - - - - - IEEE 996, A Standard for an Extended Personal Computer - Back Plane Bus - - - - - PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - PCI-to-PCI Bridge Architecture Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the - PCI SIG website for the most current version of this document. - - - - - PCI Standard Hot-Plug Controller and Subsystem - Specification - - - - - PCI-X Protocol Addendum to the PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI-X related components or platforms. See the PCI SIG website for the most - current version of this document. - - - - - PCI Express Base Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design PCI Express related components or platforms. See the PCI SIG website for - the most current version of this document. - - - - - PCI Express to PCI/PCI-X Bridge Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express related components or platforms. See the PCI SIG website for the most current - version of this document. - - - - - System Management BIOS (SMBIOS) Reference - Specification - - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - - IBM RS/6000® Division, Product Topology Data System, - Product Development Guide - Version 2.1 - - - - - Single Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI Express SR-IOV related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - Multi-Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express MR-IOV related components or platforms. See the PCI SIG website for the - most current version of this document. - - - - - - diff --git a/RTAS/app_glossary.xml b/RTAS/app_glossary.xml deleted file mode 100644 index a8b2d24..0000000 --- a/RTAS/app_glossary.xml +++ /dev/null @@ -1,1290 +0,0 @@ - - - - - Glossary - This glossary contains an alphabetical list of terms, phrases, and abbreviations used in this document. - - - - Term - Definition - - - - AC - Alternating current - - - - ACR - Architecture Change Request - - - - AD - Address Data line - - - - Adapter - A device which attaches a device to a bus or which converts one - bus to another; for example, an I/O Adapter (IOA), a PCI Host Bridge (PHB), - or a NUMA fabric attachment device. - - - - - addr - Address - - - - Architecture - The hardware/software interface definition or software module to - software module interface definition. - - - - ASCII - American National Standards Code for Information - Interchange - - - - ASR - Address Space Register - - - - BAT - Block Address Translation - - - - BE - Big-Endian or Branch Trace Enable bit in the - MSR (MSRBE) - - - - BIO - Bottom of Peripheral Input/Output Space - - - - BIOS - Basic Input/Output system - - - - BIST - Built in Self Test - - - - Boundedly undefined - Describes some addresses and registers which when referenced provide - one of a small set of predefined results. - - - - BPA - Bulk Power Assembly. Refers to components used for power distribution - from a central point in the rack. - - - - BPM - Bottom of Peripheral Memory - - - - BSCA - Bottom of System Control Area - - - - BSM - Bottom of System Memory - - - - BUID - Bus Unit Identifier. The high-order part of an interrupt source number - which is used for hardware routing purposes by the platform. - - - - CCIN - Custom Card Identification Number - - - - CD-ROM - Compact Disk Read-Only Memory - - - - CIS - Client Interface Service - - - - CMO - Cooperative Memory Over-commitment option. See - for more information. - - - - - - CMOS - Complimentary Metal Oxide Semiconductor - - - - Conventional PCI - Behavior or features that conform to . - - - - CPU - Central Processing Unit - - - - CR - Condition Register - - - - CTR - Count Register - - - - DABR - Data Address Breakpoint Register - - - - DAR - Data Address Register - - - - DASD - Direct Access Storage Device (a synonym for “hard disk”) - - - - DBAT - Data Block Address Translation - - - - DC - Direct current - - - - DEC - Decrementer - - - - DIMM - Dual In-line Memory Module - - - - DMA - Direct Memory Access - - - - DMA Read - A data transfer from System Memory to I/O. A DMA Read Request - is the inbound operation and the DMA Read Reply (or Read Completion) is the - outbound data coming back from a DMA Read Request. - - - - DMA Write - A data transfer to System Memory from I/O or a Message Signalled Interrupt (MSI) DMA Write. This is an inbound operation. - - - - DOS - Disk OS - - - - DR - Data Relocate bit in MSR (MSRDR) - - - - DRA - Deviation Risk Assessment - - - - DRAM - Dynamic Random Access Memory - - - - DRC - Delayed Read Completion. A transaction that has completed - on the destination bus and is now moving toward the originating bus to complete. - DR Connector. - - - - DR entity - An entity that can participate in DR operations. That is, an entity - that can be added or removed from the platform while the platform power is on and the - system remains operational. - - - - DRR - Delayed Read Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - DSISR - Data Storage Interrupt Status Register - - - - DWR - Delayed Write Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - EA - Effective Address - - - - EAR - External Access Register - - - - ECC - Error Checking and Correction - - - - EE - External interrupt Enable bit in the MSR (MSREE) - - - - EEH - Enhance I/O Error Handling - - - - EEPROM - Electrically Erasable Programmable Read Only Memory - - - - EPOW - Environment and Power Warning - - - - - Error Log indicator An amber indicator that indicates that the user needs to - look at the error log or problem determination procedures, in order to determine the cause. - Previously called System Information (Attention). - - - - FCode - A computer programming language defined by the OF standard which is semantically - similar to the Forth programming language, but is encoded as a sequence of binary byte codes - representing a defined set of Forth words. - - - - FE0 - Floating-point Exception mode 0 bit in the MSR (MSRFE0) - - - - FE1 - Floating-point Exception mode 1bit in the MSR (MSRFE1) - - - - FIR - Fault Isolation Registers - - - - FLR - Function Level Reset (see PCI Express documentation). An optional reset for PCI Express - functions that allows resetting a single function of a multi-function IOA. - - - - FP - Floating-Point available bit in the MSR (MSRFP) - - - - FPSCR - Floating-Point Status And Control Register - - - - FRU - Field Replaceable Unit - - - - FSM - Finite State Machine - - - - GB - Gigabytes - as used in this document it is 2 raised to the power of 30 - - - - HB - Host Bridge - - - - HMC - Hardware Management Console - used generically to refer to the system - component that performs platform administration function where ever physically located. - The HMC is outside of this architecture and may be implemented in multiple ways. - Examples include: a special HMC applications in another system, an external appliance, - or in an LPAR partition using the Virtual Management Channel (VMC) interface to the - hypervisor. - - - - Hz - Hertz - - - - IBAT - Instruction block address translation - - - - ID - Identification - - - - IDE - Integrated Device Electronics - - - - IDU - Interrupt Delivery Unit - - - - IEEE - Institute of Electrical and Electronics Engineers - - - - I2C - Inter Integrated-circuit Communications - - - - I/O - nput/Output - - - - I/O bus master - Any entity other than a processor, cache, - memory controller, or host bridge which supplies both address and data in - write transactions or supplies the address and is the sink for the data in - read transactions. - - - - I/O device - Generally refers to any entity that is connected - to an IOA (usually through a cable), but in some cases may refer to the IOA - itself (that is, a device in the device tree that happens to be used for I/O - operations). - - - - I/O Drawer - An enclosure in a rack that holds at least one PHB and at - least one IOA. - - - - ILE - Interrupt Little-Endian bit in MSR (MSRILE) - - - - Instr - Instruction - - - - Interrupt Number - See Interrupt Vector below. - - - - Interrupt Vector - The identifier associated with a specific interrupt source. - The identifier’s value is loaded into the source’s Interrupt Vector Register and - is read from the Interrupt Delivery Unit’s Interrupt Acknowledge Register. - - - - IOA - I/O Adapter. A device which attaches to a physical bus which is capable - of supporting I/O (a physical IOA) or logical bus (a virtual IOA). The term “IOA” - without the usage of the qualifier “physical” or “virtual” will be - used to designate a physical IOA. Virtual IOAs are defined further in - - . - In PCI terms, an IOA may be defined by a unique combination of its assigned - bus number and device number, but not necessarily including its function number. - That is, an IOA may be a single or multi-function device, unless otherwise specified by - the context of the text. In the context of a PCIe I/O Virtualized (IOV) device (not to be - confused with a virtual IOA), an IOA is a single or multiple function device (for example, a - PCIe Virtual Function (VF) or multiple VFs). An IOA function may or may not have its own set of - resources, that is may or may not be in its own Partitionable Endpoint (PE) domain - (see also - - ). - - - - - IOA function - That part of an IOA that deals with a specific part of the - IOA as defined by the configuration space “Function” part of Bus/Device/Function. - For single-function IOAs, the IOA Function and the IOA are synonymous. - - - - IP - Interrupt Prefix bit in MSR (MSRIP) - - - - IPI - Interprocessor Interrupt - - - - IR - Instruction Relocate bit in MSR register (MSR IR) or infrared - - - - ISF - Interrupt 64-bit processor mode bit in the MSR (MSRISF) - - - - ISO - International Standards Organization - - - - ISR - Interrupt Source Register - - - - ISU - Interrupt Source Unit - - - - KB - Kilobytes - as used in this document it is 2 raised to the power of 10 - - - - KHz - Kilo Hertz - - - - LAN - Local Area Network - - - - LCD - Liquid Crystal Display - - - - LE - Little-Endian bit in MSR (MSRLE) or Little-Endian - - - - LED - Light Emitting Diode - - - - LMB - Logical Memory Block. The Block of logical memory addresses associated with a dynamically - reconfigurable memory node. - - - - Load - A Load Request is the outbound (from the processor) operation - and the Load Reply is the inbound data coming back from a - Load Request. When it relates to I/O operations, this is an - MMIO Load . - - - - LR - Link Register - - - - LSb - Least Significant bit - - - - LSB - Least Significant Byte - - - - LSI - Level Sensitive Interrupt - - - - LUN - Logical Unit Number - - - - L1 - Primary cache - - - - L2 - Secondary cache - - - - MB - Megabytes - as used in this document it is 2 raised to the power of 20 - - - - ME - Machine check Enable - - - - MMIO - Memory Mapped I/O. This refers to the mapping of the address space required - by an I/O device for Load or Store operations into - the system’s address space. - - - - MES - Miscellaneous Equipment Specification - - - - MFM - Modified frequency modulation - - - - MHz - Mega Hertz - - - - MOD - Address modification bit in the MSR - (MSRMOD) - - - - MP - Multiprocessor - - - - MSb - Most Significant bit - - - - MSB - Most Significant Byte - - - - MSI - Message Signalled Interrupt - - - - MSR - Machine State Register - - - - MTT - Multi-TCE-Table option. See - - - . - - - - - N/A - Not Applicable - - - - Nibble - Refers to the first or last four bits in an 8 bit byte - - - - NUMA - Non-Uniform Memory Access - - - - NUMA fabric - Mechanism and method for connecting the multiple nodes of a NUMA system - - - - NVRAM - Nonvolatile Random Access Memory - - - - OF - Open Firmware - - - - OP - Operator - - - - OS - Operating System - - - - OUI - Organizationally Unique Identifier - - - - PA - Processor Architecture - - - - PAP - Privileged Access Password - - - - LoPAR - Used within the Linux on Power Architecture - Reference documents to denote: (1) the architectural requirements specified - by the Linux on Power Architecture Reference document, (2) the Linux on Power Architecture - Reference documents themself, and (3) as an adjective to qualify an entity as being - related to this architecture. - - - - Partitionable Endpoint - This refers to the I/O granule that may be treated as one for - purposes of assignment to an OS (for example, to an LPAR partition). May be an - I/O adapter (IOA), or groups of IOAs and bridges, or portions of IOAs. PE granularity - supported by the hardware may be finer than is supported by the firmware. Grouping - of multiple PEs into one DR entity may limit assignment of a the separate PEs to different - LPAR partitions. See also DR entity. - - - - PC - Personal Computer - - - - PCI - Peripheral Component Interconnect. An all-encompassing term referring to - conventional PCI, PCI-X, and PCI Express. - - - - PCI bus - A general term referring to either the PCI Local Bus, as - specified in and - for conventional PCI and PCI-X, or a PCI Express link, as specified in - for PCI Express. - - - - PCI Express - Behavior or features that conform to - . - - - - PCI link - A PCI Express link, as specified in . - - - - PCI-X - Behavior or features that conform to . - - - - PD - Presence Detect - - - - PE - When referring to the body of the LoPAR, this refers to a Partitionable - Endpoint. - - - - - - - PEM - Partition Energy Management option. See - - - . - - - - - Peripheral I/O Space - The range of real addresses which are assigned - to the I/O Space of a Host Bridge (HB) and which are sufficient to contain all of - the Load and Store address space requirements of all the devices in the I/O Space - of the I/O bus that is generated by the HB. A keyboard controller is an example of - a device which may require Peripheral I/O Space addresses. - - - - Peripheral Memory Space - The range of real addresses which are assigned to the Memory - Space of a Host Bridge (HB) and which are sufficient to contain all of the Load and - Store address space requirements of the devices in the Memory Space of the I/O bus - that is generated by the HB. The frame buffer of a graphics adapter is an example - of a device which may require Peripheral Memory Space addresses. - - - - Peripheral Space - Refers to the physical address space which may - be accessed by a processor, but which is controlled by a host bridge. At least one - peripheral space must be present and it is referred to by the suffix 0. A host bridge - will typically provide access to at least a memory space and possibly to an I/O - space. - - - - PHB - PCI Host Bridge - - - - PIC - Programmable Interrupt Controller - - - - PIR - Processor Identification Register - - - - Platform - Refers to the hardware plus firmware portion of a system composed of hardware, - firmware, and OS. - - - - Platform firmware - Refers to all firmware on a system including the software or firmware in a - support processor. - - - - Plug-in I/O card - A card which can be plugged into an I/O - connector in a platform and which contains one or more IOAs and potentially - one or more I/O bridges or switches. - - - - Plug-in Card - An entity that plugs into a physical slot. - - - - PMW - Posted memory write. A transaction that has complete on the - originating bus before completing on the destination bus - - - - PnP - Plug and Play - - - - POP - Power On Password - - - - POST - Power-On Self Test - - - - PR - Privileged bit in the MSR (MSRPR) - - - - Processor Architecture - Used throughout this document to - mean compliance with the requirements specified in - . - - - - Processor revision number - A 16-bit number that distinguishes between various releases - of a particular processor version, for example different engineering change - levels. - - - - PVN - Processor Version Number. Uniquely determines the particular - processor and PA version. - - - - PVR - Processor Version Register. A register in each processor - that identifies its type. The contents of the PVR include the processor - version number and processor revision number. - - - - RAID - Redundant Array of Independent Disks - - - - RAM - Random Access Memory - - - - RAS - Reliability, Availability, and Serviceability - - - - Real address - A real address results from doing address - translation on an effective address when address translation is enabled. - If address translation is not enabled, the real address is the same as the - effective address. An attempt to fetch from, load from, or store to a real - address that is not physically present in the machine may result in a - machine check interrupt. - - - - Reserved - The term “reserved” is used within this - document to refer to bits in registers or areas in the address space - which should not be referenced by software except as described in this - document. - - - - Reserved for firmware use - Refers to a given location or bit which may not be used by - software, but are used by firmware. - - - - Reserved for future use - Refers to areas of address space or bits in registers which may be - used by future versions of this architecture. - - - - RI - Recoverable interrupt bit in the MSR (MSRRI) - - - - RISC - Reduced Instruction Set Computing - - - - RMA - Real Mode Area. The first block of logical memory addresses - owned by a logical partition, containing the storage that may be accessed with - translate off. - - - - ROM - Read Only Memory - - - - Root Complex - A PCI Express root complex as specified in - . - - - - RPN - Real Page Number - - - - RTAS - Run-Time Abstraction Services - - - - RTC - Real Time Clock - - - - SAE - Log Service Action Event log - - - - SCC - Serial Communications Controller - - - - SCSI - Small Computer System Interface - - - - SE - Single-step trace enabled bit in the MSR - (MSRSE) - - - - Service Focal Point - The common point of control in the system for handling all - service actions - - - - Serviceable Event - Serviceable Events are platform, - global, regional and local error events that require a service action - and possibly a call home when the serviceable event must be handled by a - service representative or at least reported to the service provider. - Activation of the Error Log indicator notifies the customer of the event - and the event indicates to the customer that there must be some intervention - to rectify the problem. The intervention may be a service action that the - customer can perform or it may require a service provider. - - - - SES - Storage Enclosure Services (can also mean SCSI Enclosure - Services in relation to SCSI storage) - - - - SF - Processor 32-bit or 64-bit processor mode bit in the MSR - (MSRSF) - - - - SFP - Service Focal Point - - - - Shrink-wrap OS - A single version of an OS that runs on all - compliant platforms. - - - - Shrink-wrap Application - A single version of an application program - that runs on all compliant platforms with the applicable OS. - - - - SMP - Symmetric multiprocessor - - - - SMS - System Management Services - - - - Snarf - An industry colloquialism for cache-to-cache - transfer. A typical scenario is as follows: (1) cache miss from cache A, - (2) line found modified in cache B, (3) cache B performs castout of modified - line, and (4) cache A allocates the modified line as it is being written back - to memory. - - - - Snoop - The act of interrogating a cache for the presence of a - line, usually in response to another party on a shared bus attempting to - allocate that line. - - - - SPRG - Special Purpose Registers for General use - - - - SR - System Registers - - - - SRC - Service Reference Code - - - - SRN - Service Request Number - - - - Store - A Store Request is an - outbound (from the processor) operation. When it relates to I/O - operations, this is an MMIO Store. - - - - System - Refers to the collection of hardware, system firmware, - and OS software which comprise a computer model. - - - - System address space - The total range of addressability as established by the - processor implementation. - - - - System Control Area - Refers to a range of addresses which - contains the system ROM(s) and an unarchitected, reserved, platform-dependent - area used by firmware and Run-Time Abstraction services for control of the - platform. The ROM areas are defined by the OF properties in the - openprom and os-rom nodes - of the OF device tree. - - - - System Information (Attention) indicator - See Error Log indicator. - - - - System firmware - Refers to the collection of all firmware on a system - including OF, RTAS and any legacy firmware. - - - - System Memory - Refers to those areas of memory which form - a coherency domain with respect to the PA processor or processors that - execute application software on a system. - - - - System software - Refers to the combination of OS software, - device driver software, and any hardware abstraction software, but - excludes the application software. - - - - TB - Time Base - - - - TCE - Translation Control Entry - - - - TLB - Translation Look-aside Buffer - - - - TOD - Time Of Day - - - - TOSM - Top of system memory - - - - TPM - Top of Peripheral Memory - Trusted Platform Module - - - - tty - Teletypewriter or ASCII character driven - terminal device - - - - UI - User Interface - - - - USB - Universal Serial Bus - - - - v - Volt - - - - VGA - Video Graphics Array - - - - VMC - Virtual Management Channel - - - - VPD - Vital Product Data - - - - VPNH - Virtual Processor Home Node option. See - - - . - - - - - - - - - - - - - - diff --git a/RTAS/bk_main.xml b/RTAS/bk_main.xml deleted file mode 100644 index 6ea6b0a..0000000 --- a/RTAS/bk_main.xml +++ /dev/null @@ -1,347 +0,0 @@ - - - - - - - Runtime Abstraction Services - Linux on Power Architecture Reference - - - - - System Software Work Group - - syssw-chair@openpowerfoundation.org - - OpenPOWER Foundation - - - - 2016, 2018, 2020 - OpenPOWER Foundation - - - Revision 0.5_pre5 - OpenPOWER - - - - - - Copyright details are filled in by the template. - - - - - - The purpose of this document is to provide firmware and software - architectural details associated with Runtime Abstraction Services (firmware) on OpenPOWER Systems. - The base content for this document were contributed to the OpenPOWER Foundation in the - IBM Linux on Power Architecture Platform Reference (LoPAPR) Draft - document which detailed Linux running on PowerVM. While this information is not always - immediately applicable to new OpenPOWER modes of bare metal or KVM, many of the - concepts and interfaces remain in some form. Until such time as the document addresses - these new OpenPOWER modes and components, it will remain versioned less than 1.0. It should - also be noted that the original document had numerous contributors inside IBM. - - This document is a Standard Track, Work Group Specification work product owned by the - System Software Workgroup and handled in compliance with the requirements outlined in the - OpenPOWER Foundation Work Group (WG) Process document. It was - created using the Master Template Guide version 0.9.5. Comments, - questions, etc. can be submitted to the public mailing list for this document at - TBD. - - - - - - 2020-04-06 - - - - Revision 0.5_pre5 - Updates to include latest PAPR ACRs (2.9) as follows: - - - Add H_VIOCTL subfunctions for VNIC failover support - - - Add H_VIOCTL subfunction for virtual ethernet MAC scan functionality - - - Add H_VIOCTL subfunctions for virtual scsi and FC mobility preparation functionality - - - ibm,current-associativity-domain property - - - HPT resizing option - KVM only - - - Add Coherent Platform Facilities (CAPI) - - - XIVE Exploitation - - - Add 'OCC online/offline' events to 'IE' error log subsection - - - LPM Redundancy Phase II: Redundancy - - - Add optional sub-queue support to VFC on P9 and newer - - - Increase max num-entries for H_SEND_SUB_CRQ_INDIRECT to 128 - - - Add Virtual Serial Multiplex adapter interfaces - - - Maximum size of Dispatch Trace Log Buffer - - - Eliminate requirement for clearing TCP checksum field for ILLAN checksum calculation - - - Continued Extension of H_Send_Logical_LAN for large send packets - - - Add LPM Capablity keyword to RTAS AIX Support system parameter - - - XIVE Exploitation addition: Add ESB Reset Status to RTAS ibm,read-slot-reset-state2 - - - Add NVDIMM Protection and Encryption State system parameters - - - Change or Remove 0x9 and 0xA event subtypes for 'IE' error log subsection - - - - - Additional, post PAPR 2.9 ACRs as follows: - - - Reserve a range of hcalls to to support Ultravisor - - - Add New CAS Bit For SRIOV Virtual Function (VF) Dynamic DMA Window (DDW) Support - - - Updates to support vTPM 2.0 - - - Update XIVE Legacy hcalls to add H_Function - - - Add NVDIMM Secure Erase Command system parameter - - - Update H_REGISTER_VPA to add H_STATE return code for VPA and SLB shadow buffer. - - - Extend Firmware Assisted Dump for ISA Version 3.0 - - - Add a new return code, H_NOT_AVAILABLE, to start-cpu rtas call - - - Document already-implemented NVRAM variables - - - Update ibm,dynamic-memory-vN flags to include a "Hotplugged Memory" flag - - - - - - - - 2019-01-08 - - - - Revision 0.5_pre4 - Update document type to Work Group Note. Final review ready. - - - - - - 2018-07-30 - - - - Revision 0.5_pre3 - Updates to documentation in preparation for System SW WG review: - - - Reset document version to 0.5 - - - Improved Abstract - - - - - - - - 2017-10-11 - - - - Revision 2.0_pre2 - Updates to include latest PAPR ACRs (2.8) as follows: - - - ISA 2.07 privileged doorbell extensions (9/16/2012) - - - POWER ISA Name Change Category Vector.XOR to Vector.CRYPTO (11/4/2012) - - - Enable Multiple Redirected RDMA mappings per page (3/5/2013) - - - Add Block Invalidate Option (3/5/2013) - - - Implementation Dependent Optimizations (3/13/2013) - - - System Firmware Service Entitlement Date (Warranty Date) Check (4/3/2013) - - - New Function for ibm,change-msi to specify 32 bit MSI (5/14/2013) - - - Remove Client-Architecture-Support bit for UUID option (4/16/2013) - - - AddClient Architecture Support bit for RTAS ibm,change-msi (5/28/2013) - - - Add VNIC Server (5/24/2014) - - - VPA changes for P8 (EBB) (5/24/2013) - - - Add an hcall to clean up the entire MMU hashtable (11/20/2013) - - - Add LPCR[ILE] support to H_SET_MODE (5/31/2013) - - - New Root Node Properties (1/12/2016) - - - Extended Firmware Assisted Dump for P8 Registers (1/24/2014) - - - Sufficient H_COP_OP output buffer (6/21/2014) - - - Extend H_SEND_LOGICAL_LAN for large send packets (6/29/2014) - - - Extend H_GET_MPP_X reporting coalesced pages (8/24/2014) - - - Update ibm,pcie-link-speed-stats property to support PCIe 3.0 link speeds (6/12/2015) - - - Extend ibm,get-system-parameters RTAS to report Energy Management Tuning Parameters (3/18/2015) - - - Additional System Parameters related to mgmt of FW Service Entitlement Warranty period (6/22/2015) - - - Additional System Parameter to read LPAR Name string (10/7/2015) - - - Redesign of properties for DRC information and dynamic memory (7/23/2015) - - - Add additional logical loction code sections (3/4/2016) - - - Add ibm,vnic-client-mac to support vNIC failover (2/29/2016) - - - hcall for registering the process table (3/21/2016) - - - New device tree property for UUID (3/21/2016) - - - Changes for Hotplug RTAS Events (10/24/2016) - - - Support 64-bit PE TCEs in ibm,query-pe-dma-window (7/14/2016) - - - - - - - - 2016-05-04 - - - - Revision 2.0_pre1 - initial conversion from IBM document. Extracted from - Linux on Power Architecture Platform Reference (LoPAPR) version 1.1 dated March 24, - 2016 -- Chapter 7 (Run-time Abstration Services), Appendix G (Firmware Assisted - Dump Data Format), and Appendix I (CMO Characteristics Definition). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/RTAS/ch_error_codes.xml b/RTAS/ch_error_codes.xml deleted file mode 100644 index 5f74a7d..0000000 --- a/RTAS/ch_error_codes.xml +++ /dev/null @@ -1,1272 +0,0 @@ - - - - - Error Codes - -
- Displaying Codes on the Standard Operator Panels - - - - - R1--1. - - Platform Implementation: Platforms must display - firmware progress codes (4 hex digits) on the operator panel display. On - 2x16 LCD displays, the progress codes are displayed left-justified on the - first line. - - - - - R1--2. - - Platform Implementation: Platforms must display - firmware error codes (8 hex digits) on the system console (graphic or - tty), and left-justified on the first line of a 2x16 LCD operator panel - display (if available). - - - - - R1--3. - - Platform Implementation: When a platform displays - firmware error codes, associated location codes must be displayed on the - following line on the system console (graphic or tty), and left-justified - on the second line of a 2x16 LCD operator panel display (if - available). - - - - - - The following describes in more detail the standard platform usage - of operator panel LEDs or LCDs for the display of firmware progress and - error codes. - - - - - Progress codes: Progress codes - from the system firmware and - service processor firmware are 4 hex digits in the range from 0x8000 - through 0xFFFF. Codes are displayed in the 4 character positions of a 1x4 - LED, or left justified in the first line of a 2x16 LCD. Subsequent - progress codes are displayed on top of (overlaying) the previous one. If - the system “hangs”, the last displayed progress code is left - on the display. - - - - - Error codes: Error codes are 8 - hex digits, as defined in - . These codes are displayed by - either boot ROM Power On Self Test (POST) or the service processor. If a - critical error is detected which prevents a successful boot or results in - system halt condition, the error code will be displayed left justified on - the first line of a 2x16 LCD. The error code is left on the LCD until the - system is reset or powered down. Error codes are not displayed on the - operator panel of platforms with only a 4-digit LED. On all platforms, - however, POST error codes are displayed on any system console (graphic or - tty). For non-critical errors where the system can boot and operate - normally or in a degraded mode, the associated error codes are not - displayed, but are reported to the OS via the POST error log and the RTAS - event-scan service. - - - - - Location Codes: Location codes - describe the physical location of - the most probable failing part associated with an error code. When an - error code is displayed on the first line of a 2x16 LCD, the location - code, if known, is displayed left justified on the second line. The - location code will remain on the LCD along with the error code until the - system is reset or powered down. Location codes for POST errors are also - displayed on any system console (graphic or tty), on the next line below - the error code. - - - - -
- -
- Firmware Error Codes - - The error code is an 8-character (4-byte) hexadecimal code produced - by firmware to identify the potential failing function or FRU in a - system. It consists of 5 source code characters and 3 reason code - characters. Individual characters within the error code have specific - field definitions, as defined in the following tables. - - - - - R1--1. - - Platform Implementation: To indicate the occurrence - of a critical platform error, platforms must display (either on an - operator panel or console) an 8-digit hex error code as defined in - and - . - - - - - - - - Table 155. Service Reference Code (SRC) Field Layout - - - - - - - - - - - - - - Source Code - - - - - Reason Code - - - - - - - - - Byte 0 - - - - - Byte 1 - - - - - Byte 2 - - - - - Byte 3 - - - - - - S1 - - - S2 - - - S3 - - - S4 - - - S5 - - - R1 - - - R2 - - - R3 - - - - -
- - - Table 156. Service Reference Code (SRC) Field - Descriptions - - - - - - - - Field - - - - - Description - - - - - - - - S1 - - - Maintenance Package Source that produced the SRN - 0: Reserved - 1: Reserved - 2: POST, Firmware - 3: BIST - 4: Service processor, base system controller, etc. - 5: Reserved (potentially for use by AIX - Diagnostics) - 8: Product-Specific Service Guide, MAPs - 9: Reserved (potentially for use by the Problem Solving - Guide) - A-F: Reserved for future extension - - - - - S2 - - - Where applicable, use the lower nibble of the - - - base class code for the IOA definition (see - ). Only 00 to 0C are - currently defined in Revision 2.1, therefore the high nibble is - always zero. (There is a potential exposure that the high - nibble will be defined in the future, but currently there are - 13 base classes defined which include every device class, with - 3 remaining characters for future extension by the PCI SIG. - Therefore the exposure is in the far future.) For non-PCI - devices, use base class 0 to extend the definition (see - ). - - - - - S3-S4 - - - Where applicable, use the - - - subclass code for IOA definition (see - ). Also, extend the - definition to include non-PCI devices where it is not fully - utilized by PCI specification (see - ). - - - - - S5 - - - Unique version of the device/FRU type for a particular - product - - - - - R1 - - - Device/FRU unique failure reason codes. - For POST: assigned by Firmware Developer. - For AIX Diagnostics (S1 = 5, not currently - supported): - 1-7: Use in combination with R2,R3 for diagnostic test - failure when maximum isolation was obtained. - 8-9: Use in combination with R2,R3 for diagnostic test - failure when maximum isolation was NOT obtained. - A: Log analysis of POST error log - B: Log analysis of machine check or checkstop error - log - C: Log analysis of AIX device driver error log - D: diagnostic detected missing resource - E-F: Reserved - For others: assigned by respective developers. - - - - - R2-R3 - - - Device/FRU unique failure reason codes. - For POST: assigned by Firmware Developer - For others: assigned by respective developers. - - - - -
- - - Table 157. Current PCI Class Code Definition - - - - - - - - - PCI Base Class (lower - nibble)S2 - - - - - PCI Sub-ClassS3-S4 - - - - - Description - - - - - - - - 0 - - - Devices that were built before the class code field was - defined - - - - - 00 - - - All currently implemented IOAs except VGA-compatible - IOAs. - - - - - 01 - - - VGA-compatible IOAs. - - - - - 1 - - - Mass storage controller. - - - - - 00 - - - SCSI bus controller. - - - - - 01 - - - IDE controller. - - - - - 02 - - - Floppy disk controller. - - - - - 03 - - - Intelligent Peripheral Interface (IPI) bus - controller. - - - - - 04 - - - Redundant Array of Independent Disks (RAID) - controller. - - - - - 80 - - - Other mass storage controller. - - - - - 2 - - - Network controller. - - - - - 00 - - - Ethernet controller. - - - - - 01 - - - Token Ring controller. - - - - - 02 - - - FDDI controller. - - - - - 03 - - - ATM controller. - - - - - 80 - - - Other Network controller. - - - - - 3 - - - Display controller. - - - - - 00 - - - VGA-Compatible controller. - - - - - 01 - - - Extended Graphics Array (XGA) controller. - - - - - 80 - - - Other display controller. - - - - - 4 - - - Multimedia device - - - - - 00 - - - Video device - - - - - 01 - - - Audio device - - - - - 80 - - - Other multimedia device - - - - - 5 - - - Memory controller. - - - - - 00 - - - RAM - - - - - 01 - - - Flash - - - - - 80 - - - Other memory controller. - - - - - 6 - - - Bridge IOAs. - - - - - 00 - - - Host bridge - - - - - 01 - - - Reserved - - - - - 02 - - - Reserved - - - - - 03 - - - Reserved - - - - - 04 - - - PCI-to-PCI bridge - - - - - 05 - - - Reserved - - - - - 06 - - - Reserved - - - - - 07 - - - Reserved - - - - - 80 - - - Other bridge device. - - - - - 7 - - - Simple communication controllers. - - - - - 00 - - - Serial controllers. - - - - - 01 - - - Parallel port. - - - - - 80 - - - Other communication controllers. - - - - - 8 - - - Generic system peripherals - - - - - 00 - - - PIC - - - - - 01 - - - DMA Controller. - - - - - 02 - - - System timer - - - - - 03 - - - Real-Time Clock (RTC) controller - - - - - 80 - - - Other system peripherals - - - - - 9 - - - Input devices - - - - - 00 - - - Keyboard controller - - - - - 01 - - - Digitizer (pen). - - - - - 02 - - - Mouse controller - - - - - 80 - - - Other input controllers. - - - - - A - - - Docking stations - - - - - 00 - - - Generic docking station - - - - - 80 - - - Other type of docking station - - - - - B - - - Processors - - - - - 20 - - - PA compliant (PowerPC and successors) - - - - - 40 - - - Co-processor - - - - - C - - - Serial bus controllers - - - - - 03 - - - Universal Serial Bus (USB) - - - - - 04 - - - Fibre Channel - - - - -
- - - Table 158. S2-S3-S4 Definition for Devices/FRUs not Defined in - the PCI Specification - - - - - - - - - Base ClassS2 - - - - - Sub-ClassS3-S4 - - - - - Description - - - - - - - - 0 - - - 10 - - - AC Power - - - - - 11 - - - DC Power - - - - - 20 - - - Temperature Related Problem - - - - - 21 - - - Fans - - - - - 30-3x - - - Cables - - - - - 40-4x - - - Terminators - - - - - 50 - - - Operator panels - - - - - 60-6x - - - Reserved - - - - - 70-7x - - - Reserved - - - - - 90-9x - - - Reserved - - - - - A0 - - - Boot firmware Heartbeat - - - - - B0 - - - O/S Heartbeat - - - - - D0 - - - Unknown device - - - - - E0 - - - Security - - - - - 1 - - - A0 - - - SCSI Drives (generic) - - - - - B0 - - - IDE Drives - - - - - C0 - - - RAID Drives - - - - - D0 - - - SSA Drives - - - - - E0 - - - Tapes SCSI - - - - - E1 - - - Tapes IDE - - - - - ED - - - SCSI Changer - - - - - EE - - - Other SCSI Device - - - - - EF - - - Diskette drive - - - - - F0 - - - CDROM SCSI - - - - - F1 - - - CDROM IDE - - - - - F2 - - - Read/Write Optical SCSI - - - - - F3 - - - Read/Write Optical IDE - - - - - F4-FF - - - Reserved for other media devices - - - - - 5 - - - A0 - - - L2 Cache Controller including integrated SRAM - - - - - A1 - - - L2 Cache SRAM - - - - - A8 - - - NVRAM - - - - - A9 - - - CMOS - - - - - AA - - - Quartz/EEPROM - - - - - B0-Bx - - - Memory cards - - - - - Cyy - - - Memory DIMMs (yy = memory PD bits) - - - - - 7 - - - A0 - - - I2C bus - - - - - 8 - - - A0 - - - Power Management Functions - - - - - 9 - - - A0-Ax - - - Keyboards - - - - - B0-Bx - - - Mouse(s) - - - - - C0-Cx - - - Dials - - - - - D0 - - - Tablet - - - - - D1-Dx - - - Reserved for other input devices - - - - - B - - - A0 - - - Service processor - - - - -
- -
- - diff --git a/RTAS/pom.xml b/RTAS/pom.xml deleted file mode 100644 index 7c096f4..0000000 --- a/RTAS/pom.xml +++ /dev/null @@ -1,148 +0,0 @@ - - - - - org.openpowerfoundation.docs - workgroup-pom - 1.0.0-SNAPSHOT - ../pom.xml - - 4.0.0 - - - LoPAR-RTAS - - jar - - - LoPAR-RTAS - - - - - 0 - - - - - - - - - org.openpowerfoundation.docs - - openpowerdocs-maven-plugin - - - - generate-webhelp - - generate-webhelp - - generate-sources - - - ${comments.enabled} - LoPAR-RTAS - 1 - UA-17511903-1 - - appendix toc,title - article/appendix nop - article toc,title - book toc,title,figure,table,example,equation - book/appendix nop - book/chapter nop - chapter toc,title - chapter/section nop - section toc - part toc,title - qandadiv toc - qandaset toc - reference toc,title - set toc,title - - - 1 - 3 - 1 - - - LoPAR_RTAS - - - LoPAR_RTAS - - - workgroupNotes - - - - - - workgroupConfidential - - - - - - review - - - - - - - - true - . - - - bk_main.xml - - - - - ${basedir}/../glossary/glossary-terms.xml - 1 - www.openpowerfoundation.org - - - - - - diff --git a/Virtualization/app_bibliography.xml b/Virtualization/app_bibliography.xml deleted file mode 100644 index e0bed27..0000000 --- a/Virtualization/app_bibliography.xml +++ /dev/null @@ -1,284 +0,0 @@ - - - - - Bibliography - This section lists documents which were referenced in this specification or which provide - additional information, and some useful information for obtaining these documents. Referenced - documents are listed below. When any of the following standards are superseded by an approved - revision, the revision shall apply. - - - - - - Linux on Power Architecture Reference: Platform and Device Tree - - - - - Linux on Power Architecture Reference: Device Tree - - - - - Linux on Power Architecture Reference: Error Recovery and Logging - - - - - - - Linux on Power Architecture Reference: Runtime Abstraction Services (RTAS) - - - - - Power ISA - - - - - IEEE 1275, IEEE Standard for Boot (Initialization Configuration) Firmware: - Core Requirements and Practices - IEEE part number DS02683, ISBN 1-55937-426-8 - - - - - Core Errata, IEEE P1275.7/D4 - - - - - Open Firmware Recommended Practice:OBP-TFTP - Extension - - - - - Open Firmware Recommended Practice: Device - Support Extensions - - - - - PCI Bus binding to: IEEE Std 1275-1994, Standard - for Boot (Initialization, Configuration) Firmware - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping - - - - - Open Firmware: Recommended Practice - Forth Source - and FCode Image Support, Version 1.0 - - - - - Open Firmware: Recommended Practice - Interrupt - Mapping, Version 1.0 - - - - - Open Firmware: Recommended Practice - TFTP Booting - Extensions, Version 0.8 - - - - - Open Firmware: Recommended Practice - - Interposition, Version 0.2 - - - - - MS-DOS Programmer's Reference - Published by Microsoft - - - - - Peering Inside the PE: A Tour of the Win32 Portable - Executable File Format - Found in the March, 1994 issue of Microsoft Systems Journal - - - - - ISO-9660, Information processing -- Volume and - file structure of CD-ROM for information interchange - Published by International Organization for Standardization - - - - - System V Application Binary Interface, PowerPC - Processor Supplement - By Sunsoft - - - - - ISO Standard 8879:1986, Information Processing - -- Text and Office Systems -- Standard Generalized Markup Language (SGML) - - - - - IEEE 996, A Standard for an Extended Personal Computer - Back Plane Bus - - - - - PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - PCI-to-PCI Bridge Architecture Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design conventional PCI related components or platforms. See the - PCI SIG website for the most current version of this document. - - - - - PCI Standard Hot-Plug Controller and Subsystem - Specification - - - - - PCI-X Protocol Addendum to the PCI Local Bus Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI-X related components or platforms. See the PCI SIG website for the most - current version of this document. - - - - - PCI Express Base Specification - All designers are responsible for assuring that they use the most current version of this document - at the time that they design PCI Express related components or platforms. See the PCI SIG website for - the most current version of this document. - - - - - PCI Express to PCI/PCI-X Bridge Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express related components or platforms. See the PCI SIG website for the most current - version of this document. - - - - - System Management BIOS (SMBIOS) Reference - Specification - - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - (List Number Reserved for Compatibility) - - - - - IBM RS/6000® Division, Product Topology Data System, - Product Development Guide - Version 2.1 - - - - - Single Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at - the time that they design PCI Express SR-IOV related components or platforms. See the PCI SIG website - for the most current version of this document. - - - - - Multi-Root I/O Virtualization and Sharing Specification - All designers are responsible for assuring that they use the most current version of this document at the - time that they design PCI Express MR-IOV related components or platforms. See the PCI SIG website for the - most current version of this document. - - - - - - diff --git a/Virtualization/app_glossary.xml b/Virtualization/app_glossary.xml deleted file mode 100644 index a662dda..0000000 --- a/Virtualization/app_glossary.xml +++ /dev/null @@ -1,1282 +0,0 @@ - - - - - Glossary - This glossary contains an alphabetical list of terms, phrases, and abbreviations used in this document. - - - - Term - Definition - - - - AC - Alternating current - - - - ACR - Architecture Change Request - - - - AD - Address Data line - - - - Adapter - A device which attaches a device to a bus or which converts one - bus to another; for example, an I/O Adapter (IOA), a PCI Host Bridge (PHB), - or a NUMA fabric attachment device. - - - - - addr - Address - - - - Architecture - The hardware/software interface definition or software module to - software module interface definition. - - - - ASCII - American National Standards Code for Information - Interchange - - - - ASR - Address Space Register - - - - BAT - Block Address Translation - - - - BE - Big-Endian or Branch Trace Enable bit in the - MSR (MSRBE) - - - - BIO - Bottom of Peripheral Input/Output Space - - - - BIOS - Basic Input/Output system - - - - BIST - Built in Self Test - - - - Boundedly undefined - Describes some addresses and registers which when referenced provide - one of a small set of predefined results. - - - - BPA - Bulk Power Assembly. Refers to components used for power distribution - from a central point in the rack. - - - - BPM - Bottom of Peripheral Memory - - - - BSCA - Bottom of System Control Area - - - - BSM - Bottom of System Memory - - - - BUID - Bus Unit Identifier. The high-order part of an interrupt source number - which is used for hardware routing purposes by the platform. - - - - CCIN - Custom Card Identification Number - - - - CD-ROM - Compact Disk Read-Only Memory - - - - CIS - Client Interface Service - - - - CMO - Cooperative Memory Over-commitment option. See - for more information. - - - - - CMOS - Complimentary Metal Oxide Semiconductor - - - - Conventional PCI - Behavior or features that conform to . - - - - CPU - Central Processing Unit - - - - CR - Condition Register - - - - CTR - Count Register - - - - DABR - Data Address Breakpoint Register - - - - DAR - Data Address Register - - - - DASD - Direct Access Storage Device (a synonym for “hard disk”) - - - - DBAT - Data Block Address Translation - - - - DC - Direct current - - - - DEC - Decrementer - - - - DIMM - Dual In-line Memory Module - - - - DMA - Direct Memory Access - - - - DMA Read - A data transfer from System Memory to I/O. A DMA Read Request - is the inbound operation and the DMA Read Reply (or Read Completion) is the - outbound data coming back from a DMA Read Request. - - - - DMA Write - A data transfer to System Memory from I/O or a Message Signalled Interrupt (MSI) DMA Write. This is an inbound operation. - - - - DOS - Disk OS - - - - DR - Data Relocate bit in MSR (MSRDR) - - - - DRA - Deviation Risk Assessment - - - - DRAM - Dynamic Random Access Memory - - - - DRC - Delayed Read Completion. A transaction that has completed - on the destination bus and is now moving toward the originating bus to complete. - DR Connector. - - - - DR entity - An entity that can participate in DR operations. That is, an entity - that can be added or removed from the platform while the platform power is on and the - system remains operational. - - - - DRR - Delayed Read Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - DSISR - Data Storage Interrupt Status Register - - - - DWR - Delayed Write Request. A transaction that must complete on the destination bus before completing on the originating bus. - - - - EA - Effective Address - - - - EAR - External Access Register - - - - ECC - Error Checking and Correction - - - - EE - External interrupt Enable bit in the MSR (MSREE) - - - - EEH - Enhance I/O Error Handling - - - - EEPROM - Electrically Erasable Programmable Read Only Memory - - - - EPOW - Environment and Power Warning - - - - - Error Log indicator An amber indicator that indicates that the user needs to - look at the error log or problem determination procedures, in order to determine the cause. - Previously called System Information (Attention). - - - - FCode - A computer programming language defined by the OF standard which is semantically - similar to the Forth programming language, but is encoded as a sequence of binary byte codes - representing a defined set of Forth words. - - - - FE0 - Floating-point Exception mode 0 bit in the MSR (MSRFE0) - - - - FE1 - Floating-point Exception mode 1bit in the MSR (MSRFE1) - - - - FIR - Fault Isolation Registers - - - - FLR - Function Level Reset (see PCI Express documentation). An optional reset for PCI Express - functions that allows resetting a single function of a multi-function IOA. - - - - FP - Floating-Point available bit in the MSR (MSRFP) - - - - FPSCR - Floating-Point Status And Control Register - - - - FRU - Field Replaceable Unit - - - - FSM - Finite State Machine - - - - GB - Gigabytes - as used in this document it is 2 raised to the power of 30 - - - - HB - Host Bridge - - - - HMC - Hardware Management Console - used generically to refer to the system - component that performs platform administration function where ever physically located. - The HMC is outside of this architecture and may be implemented in multiple ways. - Examples include: a special HMC applications in another system, an external appliance, - or in an LPAR partition using the Virtual Management Channel (VMC) interface to the - hypervisor. - - - - Hz - Hertz - - - - IBAT - Instruction block address translation - - - - ID - Identification - - - - IDE - Integrated Device Electronics - - - - IDU - Interrupt Delivery Unit - - - - IEEE - Institute of Electrical and Electronics Engineers - - - - I2C - Inter Integrated-circuit Communications - - - - I/O - nput/Output - - - - I/O bus master - Any entity other than a processor, cache, - memory controller, or host bridge which supplies both address and data in - write transactions or supplies the address and is the sink for the data in - read transactions. - - - - I/O device - Generally refers to any entity that is connected - to an IOA (usually through a cable), but in some cases may refer to the IOA - itself (that is, a device in the device tree that happens to be used for I/O - operations). - - - - I/O Drawer - An enclosure in a rack that holds at least one PHB and at - least one IOA. - - - - ILE - Interrupt Little-Endian bit in MSR (MSRILE) - - - - Instr - Instruction - - - - Interrupt Number - See Interrupt Vector below. - - - - Interrupt Vector - The identifier associated with a specific interrupt source. - The identifier’s value is loaded into the source’s Interrupt Vector Register and - is read from the Interrupt Delivery Unit’s Interrupt Acknowledge Register. - - - - IOA - I/O Adapter. A device which attaches to a physical bus which is capable - of supporting I/O (a physical IOA) or logical bus (a virtual IOA). The term “IOA” - without the usage of the qualifier “physical” or “virtual” will be - used to designate a physical IOA. Virtual IOAs are defined further in - . - In PCI terms, an IOA may be defined by a unique combination of its assigned - bus number and device number, but not necessarily including its function number. - That is, an IOA may be a single or multi-function device, unless otherwise specified by - the context of the text. In the context of a PCIe I/O Virtualized (IOV) device (not to be - confused with a virtual IOA), an IOA is a single or multiple function device (for example, a - PCIe Virtual Function (VF) or multiple VFs). An IOA function may or may not have its own set of - resources, that is may or may not be in its own Partitionable Endpoint (PE) domain - (see also - ). - - - - - IOA function - That part of an IOA that deals with a specific part of the - IOA as defined by the configuration space “Function” part of Bus/Device/Function. - For single-function IOAs, the IOA Function and the IOA are synonymous. - - - - IP - Interrupt Prefix bit in MSR (MSRIP) - - - - IPI - Interprocessor Interrupt - - - - IR - Instruction Relocate bit in MSR register (MSRIR) or infrared - - - - ISF - Interrupt 64-bit processor mode bit in the MSR (MSRISF) - - - - ISO - International Standards Organization - - - - ISR - Interrupt Source Register - - - - ISU - Interrupt Source Unit - - - - KB - Kilobytes - as used in this document it is 2 raised to the power of 10 - - - - KHz - Kilo Hertz - - - - LAN - Local Area Network - - - - LCD - Liquid Crystal Display - - - - LE - Little-Endian bit in MSR (MSRLE) or Little-Endian - - - - LED - Light Emitting Diode - - - - LMB - Logical Memory Block. The Block of logical memory addresses associated with a dynamically - reconfigurable memory node. - - - - Load - A Load Request is the outbound (from the processor) operation - and the Load Reply is the inbound data coming back from a - Load Request. When it relates to I/O operations, this is an - MMIO Load . - - - - LR - Link Register - - - - LSb - Least Significant bit - - - - LSB - Least Significant Byte - - - - LSI - Level Sensitive Interrupt - - - - LUN - Logical Unit Number - - - - L1 - Primary cache - - - - L2 - Secondary cache - - - - MB - Megabytes - as used in this document it is 2 raised to the power of 20 - - - - ME - Machine check Enable - - - - MMIO - Memory Mapped I/O. This refers to the mapping of the address space required - by an I/O device for Load or Store operations into - the system’s address space. - - - - MES - Miscellaneous Equipment Specification - - - - MFM - Modified frequency modulation - - - - MHz - Mega Hertz - - - - MOD - Address modification bit in the MSR - (MSRMOD) - - - - MP - Multiprocessor - - - - MSb - Most Significant bit - - - - MSB - Most Significant Byte - - - - MSI - Message Signalled Interrupt - - - - MSR - Machine State Register - - - - MTT - Multi-TCE-Table option. See - . - - - - - N/A - Not Applicable - - - - Nibble - Refers to the first or last four bits in an 8 bit byte - - - - NUMA - Non-Uniform Memory Access - - - - NUMA fabric - Mechanism and method for connecting the multiple nodes of a NUMA system - - - - NVRAM - Nonvolatile Random Access Memory - - - - OF - Open Firmware - - - - OP - Operator - - - - OS - Operating System - - - - OUI - Organizationally Unique Identifier - - - - PA - Processor Architecture - - - - PAP - Privileged Access Password - - - - LoPAR - Used within the Linux on Power Architecture - Reference documents to denote: (1) the architectural requirements specified - by the Linux on Power Architecture Reference document, (2) the Linux on Power Architecture - Reference documents themself, and (3) as an adjective to qualify an entity as being - related to this architecture. - - - - Partitionable Endpoint - This refers to the I/O granule that may be treated as one for - purposes of assignment to an OS (for example, to an LPAR partition). May be an - I/O adapter (IOA), or groups of IOAs and bridges, or portions of IOAs. PE granularity - supported by the hardware may be finer than is supported by the firmware. Grouping - of multiple PEs into one DR entity may limit assignment of a the separate PEs to different - LPAR partitions. See also DR entity. - - - - PC - Personal Computer - - - - PCI - Peripheral Component Interconnect. An all-encompassing term referring to - conventional PCI, PCI-X, and PCI Express. - - - - PCI bus - A general term referring to either the PCI Local Bus, as - specified in and - for conventional PCI and PCI-X, or a PCI Express link, as specified in - for PCI Express. - - - - PCI Express - Behavior or features that conform to - . - - - - PCI link - A PCI Express link, as specified in . - - - - PCI-X - Behavior or features that conform to . - - - - PD - Presence Detect - - - - PE - When referring to the body of the LoPAR, this refers to a Partitionable - Endpoint. - - PE has a different meaning relative to device tree bindings - - (see - for that definition). - - - - - PEM - Partition Energy Management option. See - - . - - - - - Peripheral I/O Space - The range of real addresses which are assigned - to the I/O Space of a Host Bridge (HB) and which are sufficient to contain all of - the Load and Store address space requirements of all the devices in the I/O Space - of the I/O bus that is generated by the HB. A keyboard controller is an example of - a device which may require Peripheral I/O Space addresses. - - - - Peripheral Memory Space - The range of real addresses which are assigned to the Memory - Space of a Host Bridge (HB) and which are sufficient to contain all of the Load and - Store address space requirements of the devices in the Memory Space of the I/O bus - that is generated by the HB. The frame buffer of a graphics adapter is an example - of a device which may require Peripheral Memory Space addresses. - - - - Peripheral Space - Refers to the physical address space which may - be accessed by a processor, but which is controlled by a host bridge. At least one - peripheral space must be present and it is referred to by the suffix 0. A host bridge - will typically provide access to at least a memory space and possibly to an I/O - space. - - - - PHB - PCI Host Bridge - - - - PIC - Programmable Interrupt Controller - - - - PIR - Processor Identification Register - - - - Platform - Refers to the hardware plus firmware portion of a system composed of hardware, - firmware, and OS. - - - - Platform firmware - Refers to all firmware on a system including the software or firmware in a - support processor. - - - - Plug-in I/O card - A card which can be plugged into an I/O - connector in a platform and which contains one or more IOAs and potentially - one or more I/O bridges or switches. - - - - Plug-in Card - An entity that plugs into a physical slot. - - - - PMW - Posted memory write. A transaction that has complete on the - originating bus before completing on the destination bus - - - - PnP - Plug and Play - - - - POP - Power On Password - - - - POST - Power-On Self Test - - - - PR - Privileged bit in the MSR (MSRPR) - - - - Processor Architecture - Used throughout this document to - mean compliance with the requirements specified in - . - - - - Processor revision number - A 16-bit number that distinguishes between various releases - of a particular processor version, for example different engineering change - levels. - - - - PVN - Processor Version Number. Uniquely determines the particular - processor and PA version. - - - - PVR - Processor Version Register. A register in each processor - that identifies its type. The contents of the PVR include the processor - version number and processor revision number. - - - - RAID - Redundant Array of Independent Disks - - - - RAM - Random Access Memory - - - - RAS - Reliability, Availability, and Serviceability - - - - Real address - A real address results from doing address - translation on an effective address when address translation is enabled. - If address translation is not enabled, the real address is the same as the - effective address. An attempt to fetch from, load from, or store to a real - address that is not physically present in the machine may result in a - machine check interrupt. - - - - Reserved - The term “reserved” is used within this - document to refer to bits in registers or areas in the address space - which should not be referenced by software except as described in this - document. - - - - Reserved for firmware use - Refers to a given location or bit which may not be used by - software, but are used by firmware. - - - - Reserved for future use - Refers to areas of address space or bits in registers which may be - used by future versions of this architecture. - - - - RI - Recoverable interrupt bit in the MSR (MSRRI) - - - - RISC - Reduced Instruction Set Computing - - - - RMA - Real Mode Area. The first block of logical memory addresses - owned by a logical partition, containing the storage that may be accessed with - translate off. - - - - ROM - Read Only Memory - - - - Root Complex - A PCI Express root complex as specified in - . - - - - RPN - Real Page Number - - - - RTAS - Run-Time Abstraction Services - - - - RTC - Real Time Clock - - - - SAE - Log Service Action Event log - - - - SCC - Serial Communications Controller - - - - SCSI - Small Computer System Interface - - - - SE - Single-step trace enabled bit in the MSR - (MSRSE) - - - - Service Focal Point - The common point of control in the system for handling all - service actions - - - - Serviceable Event - Serviceable Events are platform, - global, regional and local error events that require a service action - and possibly a call home when the serviceable event must be handled by a - service representative or at least reported to the service provider. - Activation of the Error Log indicator notifies the customer of the event - and the event indicates to the customer that there must be some intervention - to rectify the problem. The intervention may be a service action that the - customer can perform or it may require a service provider. - - - - SES - Storage Enclosure Services (can also mean SCSI Enclosure - Services in relation to SCSI storage) - - - - SF - Processor 32-bit or 64-bit processor mode bit in the MSR - (MSRSF) - - - - SFP - Service Focal Point - - - - Shrink-wrap OS - A single version of an OS that runs on all - compliant platforms. - - - - Shrink-wrap Application - A single version of an application program - that runs on all compliant platforms with the applicable OS. - - - - SMP - Symmetric multiprocessor - - - - SMS - System Management Services - - - - Snarf - An industry colloquialism for cache-to-cache - transfer. A typical scenario is as follows: (1) cache miss from cache A, - (2) line found modified in cache B, (3) cache B performs castout of modified - line, and (4) cache A allocates the modified line as it is being written back - to memory. - - - - Snoop - The act of interrogating a cache for the presence of a - line, usually in response to another party on a shared bus attempting to - allocate that line. - - - - SPRG - Special Purpose Registers for General use - - - - SR - System Registers - - - - SRC - Service Reference Code - - - - SRN - Service Request Number - - - - Store - A Store Request is an - outbound (from the processor) operation. When it relates to I/O - operations, this is an MMIO Store. - - - - System - Refers to the collection of hardware, system firmware, - and OS software which comprise a computer model. - - - - System address space - The total range of addressability as established by the - processor implementation. - - - - System Control Area - Refers to a range of addresses which - contains the system ROM(s) and an unarchitected, reserved, platform-dependent - area used by firmware and Run-Time Abstraction services for control of the - platform. The ROM areas are defined by the OF properties in the - openprom and os-rom nodes - of the OF device tree. - - - - System Information (Attention) indicator - See Error Log indicator. - - - - System firmware - Refers to the collection of all firmware on a system - including OF, RTAS and any legacy firmware. - - - - System Memory - Refers to those areas of memory which form - a coherency domain with respect to the PA processor or processors that - execute application software on a system. - - - - System software - Refers to the combination of OS software, - device driver software, and any hardware abstraction software, but - excludes the application software. - - - - TB - Time Base - - - - TCE - Translation Control Entry - - - - TLB - Translation Look-aside Buffer - - - - TOD - Time Of Day - - - - TOSM - Top of system memory - - - - TPM - Top of Peripheral Memory - Trusted Platform Module - - - - tty - Teletypewriter or ASCII character driven - terminal device - - - - UI - User Interface - - - - USB - Universal Serial Bus - - - - v - Volt - - - - VGA - Video Graphics Array - - - - VMC - Virtual Management Channel - - - - VPD - Vital Product Data - - - - VPNH - Virtual Processor Home Node option. See - . - - - - - - - - - - - - - - diff --git a/Virtualization/bk_main.xml b/Virtualization/bk_main.xml deleted file mode 100644 index cc943ec..0000000 --- a/Virtualization/bk_main.xml +++ /dev/null @@ -1,349 +0,0 @@ - - - - - Virtualization - Linux on Power Architecture Reference - - - - - System Software Work Group - - syssw-chair@openpowerfoundation.org - - OpenPOWER Foundation - - - - 2016, 2018, 2020 - OpenPOWER Foundation - - - Revision 0.5_pre5 - OpenPOWER - - - - - - Copyright details are filled in by the template. - - - - - The purpose of this document is to provide firmware and software - architectural details for the virtualization components associated with an OpenPOWER Systems. - The base content for this document was contributed to the OpenPOWER Foundation in the - IBM Linux on Power Architecture Platform Reference (LoPAPR) Draft - document which detailed Linux running on PowerVM. While this information is not always - immediately applicable to new OpenPOWER modes of bare metal or KVM, many of the - concepts and interfaces remain in some form. Until such time as the document addresses - these new OpenPOWER modes and components, it will remain versioned less than 1.0. It should - also be noted that the original document had numerous contributors inside IBM. - - This document is a Standard Track, Work Group Specification work product owned by the - System Software Workgroup and handled in compliance with the requirements outlined in the - OpenPOWER Foundation Work Group (WG) Process document. It was - created using the Master Template Guide version 0.9.5. Comments, - questions, etc. can be submitted to the public mailing list for this document at - TBD. - - - - - - 2020-04-06 - - - - Revision 0.5_pre5 - Updates to include latest PAPR ACRs (2.9) as follows: - - - Add H_VIOCTL subfunctions for VNIC failover support - - - Add H_VIOCTL subfunction for virtual ethernet MAC scan functionality - - - Add H_VIOCTL subfunctions for virtual scsi and FC mobility preparation functionality - - - ibm,current-associativity-domain property - - - HPT resizing option - KVM only - - - Add Coherent Platform Facilities (CAPI) - - - XIVE Exploitation - - - Add 'OCC online/offline' events to 'IE' error log subsection - - - LPM Redundancy Phase II: Redundancy - - - Add optional sub-queue support to VFC on P9 and newer - - - Increase max num-entries for H_SEND_SUB_CRQ_INDIRECT to 128 - - - Add Virtual Serial Multiplex adapter interfaces - - - Maximum size of Dispatch Trace Log Buffer - - - Eliminate requirement for clearing TCP checksum field for ILLAN checksum calculation - - - Continued Extension of H_Send_Logical_LAN for large send packets - - - Add LPM Capablity keyword to RTAS AIX Support system parameter - - - XIVE Exploitation addition: Add ESB Reset Status to RTAS ibm,read-slot-reset-state2 - - - Add NVDIMM Protection and Encryption State system parameters - - - Change or Remove 0x9 and 0xA event subtypes for 'IE' error log subsection - - - - - Additional, post PAPR 2.9 ACRs as follows: - - - Reserve a range of hcalls to to support Ultravisor - - - Add New CAS Bit For SRIOV Virtual Function (VF) Dynamic DMA Window (DDW) Support - - - Updates to support vTPM 2.0 - - - Update XIVE Legacy hcalls to add H_Function - - - Add NVDIMM Secure Erase Command system parameter - - - Update H_REGISTER_VPA to add H_STATE return code for VPA and SLB shadow buffer. - - - Extend Firmware Assisted Dump for ISA Version 3.0 - - - Add a new return code, H_NOT_AVAILABLE, to start-cpu rtas call - - - Document already-implemented NVRAM variables - - - Update ibm,dynamic-memory-vN flags to include a "Hotplugged Memory" flag - - - - - - - - 2019-01-08 - - - - Revision 0.5_pre4 - Update document type to Work Group Note. Final review ready. - - - - - - 2018-07-30 - - - - Revision 0.5_pre3 - Updates to documentation in preparation for System SW WG review: - - - Reset document version to 0.5 - - - Improved Abstract - - - - - - - - 2017-10-11 - - - - Revision 2.0_pre2 - Updates to include latest PAPR ACRs (2.8) as follows: - - - ISA 2.07 privileged doorbell extensions (9/16/2012) - - - POWER ISA Name Change Category Vector.XOR to Vector.CRYPTO (11/4/2012) - - - Enable Multiple Redirected RDMA mappings per page (3/5/2013) - - - Add Block Invalidate Option (3/5/2013) - - - Implementation Dependent Optimizations (3/13/2013) - - - System Firmware Service Entitlement Date (Warranty Date) Check (4/3/2013) - - - New Function for ibm,change-msi to specify 32 bit MSI (5/14/2013) - - - Remove Client-Architecture-Support bit for UUID option (4/16/2013) - - - AddClient Architecture Support bit for RTAS ibm,change-msi (5/28/2013) - - - Add VNIC Server (5/24/2014) - - - VPA changes for P8 (EBB) (5/24/2013) - - - Add an hcall to clean up the entire MMU hashtable (11/20/2013) - - - Add LPCR[ILE] support to H_SET_MODE (5/31/2013) - - - New Root Node Properties (1/12/2016) - - - Extended Firmware Assisted Dump for P8 Registers (1/24/2014) - - - Sufficient H_COP_OP output buffer (6/21/2014) - - - Extend H_SEND_LOGICAL_LAN for large send packets (6/29/2014) - - - Extend H_GET_MPP_X reporting coalesced pages (8/24/2014) - - - Update ibm,pcie-link-speed-stats property to support PCIe 3.0 link speeds (6/12/2015) - - - Extend ibm,get-system-parameters RTAS to report Energy Management Tuning Parameters (3/18/2015) - - - Additional System Parameters related to mgmt of FW Service Entitlement Warranty period (6/22/2015) - - - Additional System Parameter to read LPAR Name string (10/7/2015) - - - Redesign of properties for DRC information and dynamic memory (7/23/2015) - - - Add additional logical loction code sections (3/4/2016) - - - Add ibm,vnic-client-mac to support vNIC failover (2/29/2016) - - - hcall for registering the process table (3/21/2016) - - - New device tree property for UUID (3/21/2016) - - - Changes for Hotplug RTAS Events (10/24/2016) - - - Support 64-bit PE TCEs in ibm,query-pe-dma-window (7/14/2016) - - - - - - - - 2017-05-18 - - - - Revision 2.0_pre1 - initial conversion from IBM document. Extracted from - Linux on Power Architecture Platform Reference (LoPAPR) version 1.1 dated March 24, - 2016 -- Chapter 14 (Logical Partitioning Option), Chapter 13 (Dynamic Reconfiguration - Option), Chapter 17 (Virtualized Input/Output), Appendix A (SPLPAR Characteristics - Definitions), Appendix D (A Protocol for a Virtual TTY Interface), Appendix E - (A Protocol for VSCSI Communications), Appendix F (A Protocol for VMC Communications), - Appendix J (Platform Dependent hcalls), and Appendix K (A Protocol for VNIC Communications) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Virtualization/pom.xml b/Virtualization/pom.xml deleted file mode 100644 index 9e2df62..0000000 --- a/Virtualization/pom.xml +++ /dev/null @@ -1,148 +0,0 @@ - - - - - org.openpowerfoundation.docs - workgroup-pom - 1.0.0-SNAPSHOT - ../pom.xml - - 4.0.0 - - - LoPAR-Virtualization - - jar - - - LoPAR-Virtualization - - - - - 0 - - - - - - - - - org.openpowerfoundation.docs - - openpowerdocs-maven-plugin - - - - generate-webhelp - - generate-webhelp - - generate-sources - - - ${comments.enabled} - LoPAR-Virtualization - 1 - UA-17511903-1 - - appendix toc,title - article/appendix nop - article toc,title - book toc,title,figure,table,example,equation - book/appendix nop - book/chapter nop - chapter toc,title - chapter/section nop - section toc - part toc,title - qandadiv toc - qandaset toc - reference toc,title - set toc,title - - - 1 - 3 - 1 - - - LoPAR_Virtualization - - - LoPAR_Virtualization - - - workgroupNotes - - - - - - workgroupConfidential - - - - - - review - - - - - - - - true - . - - - bk_main.xml - - - - - ${basedir}/../glossary/glossary-terms.xml - 1 - www.openpowerfoundation.org - - - - - -