The specific goals of this specification are as follows: To create a stable platform architecture to be used by platforms based on processors defined by . Processor implementations based on this architecture include IBM POWER8™ processors and their successors. To create an architecture which will allow platforms to operate with previous versions of the OS (“n-1” capability). To leverage existing and future industry-standard buses and interfaces. To provide a flexible address map. Another key attribute of this specification is the relocatability of devices and subsystems within the Processor Architecture (PA) address space. Subsystem address information, which defines where I/O Adapters (IOAs) reside, is detected by the OF and passed to the OS in the device tree. This architecture accommodates the use of multiple identical buses and IOAs in the same platform without address conflicts. To build upon the OF boot environment defined in . To provide an architecture which can evolve as technology changes. To minimize the support cost for multiple OS versions through the definition of common platform abstraction techniques. Common and compatible approaches to the abstraction of hardware will reduce the burden on hardware developers who produce differentiated machines. To architect a mechanism for error handling, error reporting, and fault isolation. This architecture provides for the implementation of more robust systems, if desired by the system developers. To architect a mechanism for Dynamic Reconfiguration of the hardware. To provide an architecture which allows for the logical partitioning of system resources, in order to execute multiple concurrent OS instances.