This glossary contains an alphabetical list of terms, phrases, and abbreviations used in this document. Term Definition AC Alternating current ACR Architecture Change Request AD Address Data line Adapter A device which attaches a device to a bus or which converts one bus to another; for example, an I/O Adapter (IOA), a PCI Host Bridge (PHB), or a NUMA fabric attachment device. addr Address Architecture The hardware/software interface definition or software module to software module interface definition. ASCII American National Standards Code for Information Interchange ASR Address Space Register BAT Block Address Translation BE Big-Endian or Branch Trace Enable bit in the MSR (MSRBE) BIO Bottom of Peripheral Input/Output Space BIOS Basic Input/Output system BIST Built in Self Test Boundedly undefined Describes some addresses and registers which when referenced provide one of a small set of predefined results. BPA Bulk Power Assembly. Refers to components used for power distribution from a central point in the rack. BPM Bottom of Peripheral Memory BSCA Bottom of System Control Area BSM Bottom of System Memory BUID Bus Unit Identifier. The high-order part of an interrupt source number which is used for hardware routing purposes by the platform. CCIN Custom Card Identification Number CD-ROM Compact Disk Read-Only Memory CIS Client Interface Service CMO Cooperative Memory Over-commitment option. See for more information. CMOS Complimentary Metal Oxide Semiconductor Conventional PCI Behavior or features that conform to . CPU Central Processing Unit CR Condition Register CTR Count Register DABR Data Address Breakpoint Register DAR Data Address Register DASD Direct Access Storage Device (a synonym for “hard disk”) DBAT Data Block Address Translation DC Direct current DEC Decrementer DIMM Dual In-line Memory Module DMA Direct Memory Access DMA Read A data transfer from System Memory to I/O. A DMA Read Request is the inbound operation and the DMA Read Reply (or Read Completion) is the outbound data coming back from a DMA Read Request. DMA Write A data transfer to System Memory from I/O or a Message Signalled Interrupt (MSI) DMA Write. This is an inbound operation. DOS Disk OS DR Data Relocate bit in MSR (MSRDR) DRA Deviation Risk Assessment DRAM Dynamic Random Access Memory DRC Delayed Read Completion. A transaction that has completed on the destination bus and is now moving toward the originating bus to complete. DR Connector. DR entity An entity that can participate in DR operations. That is, an entity that can be added or removed from the platform while the platform power is on and the system remains operational. DRR Delayed Read Request. A transaction that must complete on the destination bus before completing on the originating bus. DSISR Data Storage Interrupt Status Register DWR Delayed Write Request. A transaction that must complete on the destination bus before completing on the originating bus. EA Effective Address EAR External Access Register ECC Error Checking and Correction EE External interrupt Enable bit in the MSR (MSREE) EEH Enhance I/O Error Handling EEPROM Electrically Erasable Programmable Read Only Memory EPOW Environment and Power Warning Error Log indicator An amber indicator that indicates that the user needs to look at the error log or problem determination procedures, in order to determine the cause. Previously called System Information (Attention). FCode A computer programming language defined by the OF standard which is semantically similar to the Forth programming language, but is encoded as a sequence of binary byte codes representing a defined set of Forth words. FE0 Floating-point Exception mode 0 bit in the MSR (MSRFE0) FE1 Floating-point Exception mode 1bit in the MSR (MSRFE1) FIR Fault Isolation Registers FLR Function Level Reset (see PCI Express documentation). An optional reset for PCI Express functions that allows resetting a single function of a multi-function IOA. FP Floating-Point available bit in the MSR (MSRFP) FPSCR Floating-Point Status And Control Register FRU Field Replaceable Unit FSM Finite State Machine GB Gigabytes - as used in this document it is 2 raised to the power of 30 HB Host Bridge HMC Hardware Management Console - used generically to refer to the system component that performs platform administration function where ever physically located. The HMC is outside of this architecture and may be implemented in multiple ways. Examples include: a special HMC applications in another system, an external appliance, or in an LPAR partition using the Virtual Management Channel (VMC) interface to the hypervisor. Hz Hertz IBAT Instruction block address translation ID Identification IDE Integrated Device Electronics IDU Interrupt Delivery Unit IEEE Institute of Electrical and Electronics Engineers I2C Inter Integrated-circuit Communications I/O nput/Output I/O bus master Any entity other than a processor, cache, memory controller, or host bridge which supplies both address and data in write transactions or supplies the address and is the sink for the data in read transactions. I/O device Generally refers to any entity that is connected to an IOA (usually through a cable), but in some cases may refer to the IOA itself (that is, a device in the device tree that happens to be used for I/O operations). I/O Drawer An enclosure in a rack that holds at least one PHB and at least one IOA. ILE Interrupt Little-Endian bit in MSR (MSRILE) Instr Instruction Interrupt Number See Interrupt Vector below. Interrupt Vector The identifier associated with a specific interrupt source. The identifier’s value is loaded into the source’s Interrupt Vector Register and is read from the Interrupt Delivery Unit’s Interrupt Acknowledge Register. IOA I/O Adapter. A device which attaches to a physical bus which is capable of supporting I/O (a physical IOA) or logical bus (a virtual IOA). The term “IOA” without the usage of the qualifier “physical” or “virtual” will be used to designate a physical IOA. Virtual IOAs are defined further in . In PCI terms, an IOA may be defined by a unique combination of its assigned bus number and device number, but not necessarily including its function number. That is, an IOA may be a single or multi-function device, unless otherwise specified by the context of the text. In the context of a PCIe I/O Virtualized (IOV) device (not to be confused with a virtual IOA), an IOA is a single or multiple function device (for example, a PCIe Virtual Function (VF) or multiple VFs). An IOA function may or may not have its own set of resources, that is may or may not be in its own Partitionable Endpoint (PE) domain (see also ). IOA function That part of an IOA that deals with a specific part of the IOA as defined by the configuration space “Function” part of Bus/Device/Function. For single-function IOAs, the IOA Function and the IOA are synonymous. IP Interrupt Prefix bit in MSR (MSRIP) IPI Interprocessor Interrupt IR Instruction Relocate bit in MSR register (MSR IR) or infrared ISF Interrupt 64-bit processor mode bit in the MSR (MSRISF) ISO International Standards Organization ISR Interrupt Source Register ISU Interrupt Source Unit KB Kilobytes - as used in this document it is 2 raised to the power of 10 KHz Kilo Hertz LAN Local Area Network LCD Liquid Crystal Display LE Little-Endian bit in MSR (MSRLE) or Little-Endian LED Light Emitting Diode LMB Logical Memory Block. The Block of logical memory addresses associated with a dynamically reconfigurable memory node. Load A Load Request is the outbound (from the processor) operation and the Load Reply is the inbound data coming back from a Load Request. When it relates to I/O operations, this is an MMIO Load . LR Link Register LSb Least Significant bit LSB Least Significant Byte LSI Level Sensitive Interrupt LUN Logical Unit Number L1 Primary cache L2 Secondary cache MB Megabytes - as used in this document it is 2 raised to the power of 20 ME Machine check Enable MMIO Memory Mapped I/O. This refers to the mapping of the address space required by an I/O device for Load or Store operations into the system’s address space. MES Miscellaneous Equipment Specification MFM Modified frequency modulation MHz Mega Hertz MOD Address modification bit in the MSR (MSRMOD) MP Multiprocessor MSb Most Significant bit MSB Most Significant Byte MSI Message Signalled Interrupt MSR Machine State Register MTT Multi-TCE-Table option. See . N/A Not Applicable Nibble Refers to the first or last four bits in an 8 bit byte NUMA Non-Uniform Memory Access NUMA fabric Mechanism and method for connecting the multiple nodes of a NUMA system NVRAM Nonvolatile Random Access Memory OF Open Firmware OP Operator OS Operating System OUI Organizationally Unique Identifier PA Processor Architecture PAP Privileged Access Password LoPAR Used within the Linux on Power Architecture Reference documents to denote: (1) the architectural requirements specified by the Linux on Power Architecture Reference document, (2) the Linux on Power Architecture Reference documents themself, and (3) as an adjective to qualify an entity as being related to this architecture. Partitionable Endpoint This refers to the I/O granule that may be treated as one for purposes of assignment to an OS (for example, to an LPAR partition). May be an I/O adapter (IOA), or groups of IOAs and bridges, or portions of IOAs. PE granularity supported by the hardware may be finer than is supported by the firmware. Grouping of multiple PEs into one DR entity may limit assignment of a the separate PEs to different LPAR partitions. See also DR entity. PC Personal Computer PCI Peripheral Component Interconnect. An all-encompassing term referring to conventional PCI, PCI-X, and PCI Express. PCI bus A general term referring to either the PCI Local Bus, as specified in and for conventional PCI and PCI-X, or a PCI Express link, as specified in for PCI Express. PCI Express Behavior or features that conform to . PCI link A PCI Express link, as specified in . PCI-X Behavior or features that conform to . PD Presence Detect PE When referring to the body of the LoPAR, this refers to a Partitionable Endpoint. PEM Partition Energy Management option. See . Peripheral I/O Space The range of real addresses which are assigned to the I/O Space of a Host Bridge (HB) and which are sufficient to contain all of the Load and Store address space requirements of all the devices in the I/O Space of the I/O bus that is generated by the HB. A keyboard controller is an example of a device which may require Peripheral I/O Space addresses. Peripheral Memory Space The range of real addresses which are assigned to the Memory Space of a Host Bridge (HB) and which are sufficient to contain all of the Load and Store address space requirements of the devices in the Memory Space of the I/O bus that is generated by the HB. The frame buffer of a graphics adapter is an example of a device which may require Peripheral Memory Space addresses. Peripheral Space Refers to the physical address space which may be accessed by a processor, but which is controlled by a host bridge. At least one peripheral space must be present and it is referred to by the suffix 0. A host bridge will typically provide access to at least a memory space and possibly to an I/O space. PHB PCI Host Bridge PIC Programmable Interrupt Controller PIR Processor Identification Register Platform Refers to the hardware plus firmware portion of a system composed of hardware, firmware, and OS. Platform firmware Refers to all firmware on a system including the software or firmware in a support processor. Plug-in I/O card A card which can be plugged into an I/O connector in a platform and which contains one or more IOAs and potentially one or more I/O bridges or switches. Plug-in Card An entity that plugs into a physical slot. PMW Posted memory write. A transaction that has complete on the originating bus before completing on the destination bus PnP Plug and Play POP Power On Password POST Power-On Self Test PR Privileged bit in the MSR (MSRPR) Processor Architecture Used throughout this document to mean compliance with the requirements specified in . Processor revision number A 16-bit number that distinguishes between various releases of a particular processor version, for example different engineering change levels. PVN Processor Version Number. Uniquely determines the particular processor and PA version. PVR Processor Version Register. A register in each processor that identifies its type. The contents of the PVR include the processor version number and processor revision number. RAID Redundant Array of Independent Disks RAM Random Access Memory RAS Reliability, Availability, and Serviceability Real address A real address results from doing address translation on an effective address when address translation is enabled. If address translation is not enabled, the real address is the same as the effective address. An attempt to fetch from, load from, or store to a real address that is not physically present in the machine may result in a machine check interrupt. Reserved The term “reserved” is used within this document to refer to bits in registers or areas in the address space which should not be referenced by software except as described in this document. Reserved for firmware use Refers to a given location or bit which may not be used by software, but are used by firmware. Reserved for future use Refers to areas of address space or bits in registers which may be used by future versions of this architecture. RI Recoverable interrupt bit in the MSR (MSRRI) RISC Reduced Instruction Set Computing RMA Real Mode Area. The first block of logical memory addresses owned by a logical partition, containing the storage that may be accessed with translate off. ROM Read Only Memory Root Complex A PCI Express root complex as specified in . RPN Real Page Number RTAS Run-Time Abstraction Services RTC Real Time Clock SAE Log Service Action Event log SCC Serial Communications Controller SCSI Small Computer System Interface SE Single-step trace enabled bit in the MSR (MSRSE) Service Focal Point The common point of control in the system for handling all service actions Serviceable Event Serviceable Events are platform, global, regional and local error events that require a service action and possibly a call home when the serviceable event must be handled by a service representative or at least reported to the service provider. Activation of the Error Log indicator notifies the customer of the event and the event indicates to the customer that there must be some intervention to rectify the problem. The intervention may be a service action that the customer can perform or it may require a service provider. SES Storage Enclosure Services (can also mean SCSI Enclosure Services in relation to SCSI storage) SF Processor 32-bit or 64-bit processor mode bit in the MSR (MSRSF) SFP Service Focal Point Shrink-wrap OS A single version of an OS that runs on all compliant platforms. Shrink-wrap Application A single version of an application program that runs on all compliant platforms with the applicable OS. SMP Symmetric multiprocessor SMS System Management Services Snarf An industry colloquialism for cache-to-cache transfer. A typical scenario is as follows: (1) cache miss from cache A, (2) line found modified in cache B, (3) cache B performs castout of modified line, and (4) cache A allocates the modified line as it is being written back to memory. Snoop The act of interrogating a cache for the presence of a line, usually in response to another party on a shared bus attempting to allocate that line. SPRG Special Purpose Registers for General use SR System Registers SRC Service Reference Code SRN Service Request Number Store A Store Request is an outbound (from the processor) operation. When it relates to I/O operations, this is an MMIO Store. System Refers to the collection of hardware, system firmware, and OS software which comprise a computer model. System address space The total range of addressability as established by the processor implementation. System Control Area Refers to a range of addresses which contains the system ROM(s) and an unarchitected, reserved, platform-dependent area used by firmware and Run-Time Abstraction services for control of the platform. The ROM areas are defined by the OF properties in the openprom and os-rom nodes of the OF device tree. System Information (Attention) indicator See Error Log indicator. System firmware Refers to the collection of all firmware on a system including OF, RTAS and any legacy firmware. System Memory Refers to those areas of memory which form a coherency domain with respect to the PA processor or processors that execute application software on a system. System software Refers to the combination of OS software, device driver software, and any hardware abstraction software, but excludes the application software. TB Time Base TCE Translation Control Entry TLB Translation Look-aside Buffer TOD Time Of Day TOSM Top of system memory TPM Top of Peripheral Memory Trusted Platform Module tty Teletypewriter or ASCII character driven terminal device UI User Interface USB Universal Serial Bus v Volt VGA Video Graphics Array VMC Virtual Management Channel VPD Vital Product Data VPNH Virtual Processor Home Node option. See .