Interrupt Controller

PowerPC External Interrupt Option The PowerPC External Interrupt option is based upon a subset of the PowerPC External Interrupt Architecture. The PowerPC External Interrupt Architecture contains a register-level architectural definition of an interrupt control structure. This architecture defines means for assigning properties such as priority, destination, etc., to I/O and interprocessor interrupts, as well as an interface for presenting them to processors. It supports both specific and distributed methods for interrupt delivery. See also A PowerPC External Interrupt.htm#38341.--> In NUMA platform configurations, the interrupt controllers may be configured in disjoint domains. The firmware makes the server numbers visible to any single OS image appear to come from a single space without duplication. This may be done by appropriately initializing the interrupt presentation controllers or the firmware may translate the server numbers presented to it in RTAS calls before entering them into the interrupt controller registers. The OS is made aware that certain interrupts are only served by certain servers by the inclusion of the “ibm,interrupt-domain” property in the interrupt controller nodes.

PowerPC External Interrupt Option Requirements The following are the requirements for the PowerPC External Interrupt option. Additional requirements and information relative to the MSI option, when implemented with this option, are listed in . R1--1. For the PowerPC External Interrupt option: Platforms must implement interrupt architectures that are in register-level architectural compliance with A PowerPC External Interrupt. R1--2. For the PowerPC External Interrupt option: The platform’s OF device tree must include one or more PowerPC External Interrupt Presentation node(s), as children of the root node. R1--3. For the PowerPC External Interrupt option: The platform’s OF device tree must include an “ibm,ppc-interrupt-server#s” and an “ibm,ppc-interrupt-gserver#s” property as defined for each processor in the processor’s /cpus/cpu node. R1--4. For the PowerPC External Interrupt option: The various “ibm,ppc-interrupt-server#s” property values seen by a single OS image must be all unique. R1--5. For the PowerPC External Interrupt option: If an OS image sees multiple global interrupt server queues, the “ibm,ppc-interrupt-gserver#s” properties associated with the various queues must have unique values. R1--6. For the PowerPC External Interrupt option: The platform’s OF device tree must include a PowerPC External Interrupt Source Controller node, as defined for each Bus Unit Controller (BUC) that can generate PowerPC External Interrupt Architecture interrupts, as a child of the platform’s root node. R1--7. For the PowerPC External Interrupt option: The platform’s OF device tree must conform to the and include the appropriate mapping and interrupt properties to allow the mapping of all non-zero XISR values (interrupt#) to the corresponding node generating the interrupt. R1--8. For the PowerPC External Interrupt option: The PowerPC External Interrupt Presentation Controller node must not contain the “used-by-rtas” property. R1--9. For the PowerPC External Interrupt option: The PowerPC External Interrupt Source Controller node must contain the “used-by-rtas” property. R1--10. For the PowerPC External Interrupt option: If the interrupt hardware is configured such that, viewed from any given OS image, any interrupt source controller cannot direct interrupts to any interrupt presentation controller, then the platform must include the “ibm,interrupt-domain” property in all interrupt source and presentation controller nodes for that OS so that the OS can determine the servers that may be valid targets for any given interrupt. R1--11. For the PowerPC External Interrupt option: All interrupt controller registers must be accessed via Caching-Inhibited, Memory Coherence not required and Guarded Storage mapping. R1--12. For the PowerPC External Interrupt option: The platform must manage the Available Processor Mask Register so that global interrupts (server number field of the eXternal Interrupt Vector Entry (XIVE) set to a value from “ibm,ppc-interrupt-gserver#s”) are only sent to one of the active processors. R1--13. For the PowerPC External Interrupt option: The platform must initialize the interrupt priority in each XIVE to the least favored level (0xFF), enable any associated IER bit for interrupt sources owned by the OS, and set the Current Processor Priority Register to the Most favored level (0x00) prior to the transfer of control to the OS so that no interrupts are signaled to a processor until the OS has taken explicit action. R1--14. For the PowerPC External Interrupt option: Any implemented PowerPC External Interrupt Architecture registers that are not reported in specific interrupt source or destination controller nodes (such as the APM register) must be included in the “reg” property of the /reserved node. R1--15. For the PowerPC External Interrupt option: The interrupt source controller must prevent signalling new interrupts when the XIVE interrupt priority field is set to the least favored level. R1--16. For the PowerPC External Interrupt option: Interrupt controllers that do not implement the behavior of Requirement , must provide an Interrupt Enable Register (IER) which can be manipulated by RTAS, R1--17. For the PowerPC External Interrupt option: The platform must assign the Bus Unit Identifiers (BUIDs) such that they form a compact address space. That is, while the first BUID value is arbitrary, subsequent BUIDs should be contiguous. R1--18. For the PowerPC External Interrupt option: Platforms implementing interrupt server number fields greater than 8 bits must include the “ibm,interrupt-server#-size” property in the interrupt source controller node. R1--19. For the PowerPC External Interrupt option: Platforms implementing interrupt buid number fields greater than 9 bits must include the “ibm,interrupt-buid-size” property in the interrupt presentation controller node. R1--20. For the PowerPC External Interrupt option: Platforms must include the “ibm,interrupt-server-ranges” property in the interrupt presentation controller node.

PowerPC External Interrupt Option Properties See for property definitions.

MSI Option The Message Signaled Interrupt (MSI) or Enhanced MSI (MSI-X) capability of PCI IOAs in many cases allows for greater flexibility in assignment of external interrupts to IOA functions than the predecessor Level Sensitive Interrupt (LSI) capability, and in some cases treats MSIs as a resource pool that can be reassigned based on availability of MSIs and the need of an IOA function for more interrupts than initially assigned. Platforms that implement the MSI option implement the ibm,change-msi and ibm,query-interrupt-source-number RTAS calls. These RTAS calls manage interrupts in a platform that implements the MSI option. In particular, these calls assign additional MSI resources to an IOA function (as defined by its PCI configuration address: PHB_Unit_ID_Hi, PHB_Unit_ID_Low, and config_addr), when supported by the platform. See for more information on theses RTAS calls for MSI management. This architecture will refer generically to the MSI and MSI-X capabilities as simply “MSI,” except where differentiation is required. In this architecture, MSIs and LSIs are what the IOA function signals, and what the software sees for that signal is ultimately the LSI or MSI source number. The interrupt source numbers returned by the ibm,query-interrupt-source-number RTAS call are the numbers used to control the interrupt as in the ibm,get-xive, ibm,set-xive, ibm,int-on, and ibm,int-off RTAS calls. PCI-X and PCI Express IOA functions that signal interrupts are required by the PCI specifications to implement either the MSI or MSI-X interrupt capabilities, or both. For PCI Express, it is expected that IOAs will only support MSI or MSI-X (that is, no support for LSIs). When both MSI and MSI-X are implemented by an IOA function, the MSI method will be configured by the platform, but may be overridden by the OS or device driver, via the ibm,change-msi RTAS call, to be MSI-X or, if assigned by the firmware, to LSI (by removal of the MSIs assigned). summarizes the LSI and MSI support. LSI and MSI Support Requirements and Initial Assignment IOA Type LSI required by PCI specifications? MSI or MSI-Xrequired by PCI specifications? Bridge between IOA and PHB Possible platform support Initial interrupt assignmentAssignment means to allocate the platform resources and to enable the interrupt in the IOA function’s configuration space. If PHB does not support MSI option (Not including PCI Express HBs) If PHB supports MSI option (Including all PCI Express HBs) PCI When interrupts are required No (allowed; optional) - LSI LSI or MSI LSIIf MSIs are to be supported, the device driver must enable via the ibm,change-msi RTAS call. PCI-X Encouraged when interrupts are required, for backward platform compatibility Yes - LSI LSI or MSI LSIIf MSIs are to be supported, the device driver must enable via the ibm,change-msi RTAS call. PCI Express Discouraged (expect IOAs to not implement in most cases) Yes None or PCI Express switch only n/a MSI MSIMSI as an initial assignment means that one or more MSIs are reported as being available for the IOA function. In addition, LSIs may also be reported but not enabled, in which case if the device driver removes the assigned MSIs, the assigned LSI are enabled by the platform firmware in the IOA function’s configuration space. Reverse bridge (primary, PCI Express secondary) LSI or not supported If PCI Express IOA function does not support LSI, then this combination is not supported. LSI If PCI Express IOA function does not support LSI, then this combination is not supported. or MSI LSI If the PCI Express IOA function does not support LSI, then the platform will set the initial interrupt assignment to MSI, and if the device driver does not support MSI, then the IOA function will not be configurable (that is, conversion from MSI to LSI through the bridge is not supported by this architecture). If LSI is the initial assignment, then if MSIs are to be supported, device driver must enable via the ibm,change-msi RTAS call.

The ibm,change-msi RTAS call is used to query the initial number of MSIs assigned to a PCI configuration address and to request a change in the number of MSIs assigned. The MSIs interrupt source numbers assigned to an IOA function are returned via the ibm,query-interrupt-source-number RTAS call. In addition, when the ibm,query-interrupt-source-number RTAS call is implemented, it may be used to query the LSI source numbers, also. The ibm,query-interrupt-source-number RTAS call is called iteratively, once for each interrupt assigned to the IOA function. When an IOA function receives an initial assignment of an LSI, the interrupt number for that LSI may also be obtained through the same OF device tree properties that are used to report interrupt information when the ibm,query-interrupt-source-number RTAS call is not implemented. R1--1. The platform must implement the MSI option if the platform contains at least one PCI Express HB. Architecture and Software Note: The MSI option may also be implemented in the absence of any PCI Express HBs. In that case, the implementation of the MSI option is via the presence of the implementation of the associated ibm,change-msi and ibm,query-interrupt-source-number RTAS calls. R1--2. For the MSI option: The platform must implement the PowerPC External Interrupt option. R1--3. For the MSI option: The platform must implement the ibm,change-msi and ibm,query-interrupt-source-number RTAS calls. R1--4. For the MSI option: The platform must initially assign LSI or MSIs to IOA functions as defined in and must enable the assigned interrupts in the IOA function’s configuration space (the interrupts remains disabled at the PHB, and must be enabled by the device driver though the ibm,set-xive and ibm,int-on RTAS calls. R1--5. For the MSI option: The platform must provide a minimum of one MSI per IOA function (that is per each unique PCI configuration address, including the Function #) to be supported beneath the interrupt source controller, and any given MSI and MSI source number must not be shared between functions or within one function (even within the same PE). R1--6. For the MSI option: The platform must provide at least one MSI port (the address written by the MSI) per Partitionable Endpoint (PE). Platform Implementation Note: Requirement in conjunction with Requirement may have certain ramifications on the design. Depending on the implementation, a unique MSI port per IOA function may be required, and not just a unique port per PE. R1--7. For the MSI option with the LPAR option: The platform must prevent a PE from creating an interrupt to a partition other than those to which the PE is authorized by the platform to interrupt. R1--8. For the MSI option: The platform must set the PCI configuration space MSI registers properly in an IOA at all the following times: Initial boot time During the ibm,configure-connector RTAS call During the ibm,change-msi or ibm,query-interrupt-source-number RTAS call R1--9. For the MSI option: The platform must initialize any bridges necessary to appropriately route interrupts at all the following times: At initial boot time During the ibm,configure-connector RTAS call During the ibm,configure-bridge RTAS call During the ibm,change-msi or ibm,query-interrupt-source-number RTAS call R1--10. For the MSI option: The platform must provide the “ibm,req#msi” property for any IOA function which is requesting MSIs; at initial boot time and during the ibm,configure-connector RTAS call. R1--11. For the MSI option: The platform must remember and recover on error recovery any previously allocated and setup interrupt information in the platform-owned hardware. Software and Platform Implementation Note: In Requirement , it is possible that some interrupts may be lost as part of the error recovery, and software should be implemented to take into consideration that possibility.