You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

51620 lines
1.6 MiB

<!--
Copyright (c) 2019-2021 OpenPOWER Foundation
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<chapter version="5.0" xml:lang="en" xmlns="http://docbook.org/ns/docbook" xmlns:xi="http://www.w3.org/2001/XInclude"
xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
<!-- Chapter Title goes here. -->
<title>Vector Intrinsic Reference</title>
<section>
<title>How to Use This Reference</title>
<para>
This chapter contains reference material for each supported
vector intrinsic. The information for each intrinsic includes:
</para>
<itemizedlist>
<listitem>
<para>
The intrinsic name and extended name;
</para>
</listitem>
<listitem>
<para>
A type-free example of the intrinsic's usage;
</para>
</listitem>
<listitem>
<para>
A description of the intrinsic's purpose;
</para>
</listitem>
<listitem>
<para>
A description of the value(s) returned from the intrinsic,
if any;
</para>
</listitem>
<listitem>
<para>
A description of any unusual characteristics of the
intrinsic when different target endiannesses are in force.
If the semantics of the intrinsic in big-endian and
little-endian modes are identical, the description will read
"None.";
</para>
</listitem>
<listitem>
<para>
Optionally, additional explanatory notes about the
intrinsic; and
</para>
</listitem>
<listitem>
<para>
A table of supported type signatures for the intrinsic.
</para>
</listitem>
</itemizedlist>
<para>
Most intrinsics are overloaded, supporting multiple type
signatures. The types of the input arguments always determine
the type of the result argument; that is, it is not possible to
define two intrinsic overloads with the same input argument
types and different result argument types.
</para>
<para>
The type-free example of the intrinsic's usage uses the
convention that <emphasis role="bold">r</emphasis> represents
the result of the intrinsic, and <emphasis
role="bold">a</emphasis>, <emphasis role="bold">b</emphasis>,
etc., represent the input arguments. The allowed type
combinations of these variables are shown as rows in the table
of supported type signatures.
</para>
<para>
Each row contains at least one example implementation. This
shows one way that a conforming compiler might achieve the
intended semantics of the intrinsic, but compilers are not
required to generate this code specifically. The letters
<emphasis role="bold">r</emphasis>, <emphasis
role="bold">a</emphasis>, <emphasis role="bold">b</emphasis>,
etc., in the examples represent vector registers containing the
values of those variables. The letters <emphasis
role="bold">t</emphasis>, <emphasis role="bold">u</emphasis>,
etc., represent vector registers containing temporary
intermediate results. The same register is assumed to be used
for each instance of one of these letters.
</para>
<para>
When implementations differ for big- and little-endian targets,
separate example implementations are shown for each endianness.
</para>
<para>
The implementations show a sequence of instructions that may be
used in the implementation of a particular intrinsic, and
usually include vector instructions. When trying to
determine which intrinsic to use, it can be useful to have a
cross-reference from a specific vector instruction to the
intrinsics whose implementations make use of it. This manual
contains such a cross-reference (<xref
linkend="section_isa_intrin_xref" />) for the programmer's
convenience.
</para>
<para>
For some intrinsics, restrictions are shown in the
implementation table for some of the rows. Possible
restrictions include:
</para>
<itemizedlist>
<listitem>
<para>
<emphasis role="bold">ISA 3.0 or later</emphasis>. This
form is only available starting with PowerISA 3.0,
corresponding to POWER9 servers. The Power Vector Library
(see <xref linkend="VIPR.intro.links" /> provides equivalent
POWER7/POWER8 implementations for many ISA 3.0 vector
instructions, which may be preferred for portability.
</para>
</listitem>
<listitem revisionflag="added">
<para>
<emphasis role="bold">ISA 3.1 or later</emphasis>. This form
is only available starting with PowerISA 3.1, corresponding to
POWER10 servers.
</para>
</listitem>
<listitem>
<para>
<emphasis role="bold">Deprecated</emphasis>. This form of
the intrinsic is currently available, but may be removed in
the future. Programmers are discouraged from using it.
</para>
</listitem>
</itemizedlist>
<section>
<title>Terminology</title>
<para>
Some intrinsic descriptions indicate that either
<emphasis>modular</emphasis> arithmetic or
<emphasis>saturating</emphasis> arithmetic is used. This
refers to what happens when an operation overflows the number
of available bits. A modular operation that overflows
truncates the result on the left, also known as wrapping the
result. A saturating operation that overflows produces the
largest (or smallest) possible result representable in the
output element type.
</para>
<para>
Operands are sometimes represented as having a <code>const
int</code> type. In such cases, the programmer is expected to
provide an integer literal. When the literal has specific
required bounds, this is often represented instead by such
phrases as "5-bit signed literal" or "2-bit unsigned literal"
to specify them. In such cases, compilers are encouraged to
at least warn upon detecting an out-of-range value. Providing
a variable when a literal is required is a compile-time error.
</para>
</section>
</section>
<?hard-pagebreak?>
<section xml:id="VIPR.reference.vecfns">
<title>Built-In Vector Functions</title>
2 years ago
<section xml:id="vec_abs">
<title>vec_abs</title>
<subtitle>Vector Absolute Value</subtitle>
<programlisting>
r = vec_abs (a)
</programlisting>
<para><emphasis role="bold">Purpose:</emphasis>
Returns a vector <emphasis role="bold">r</emphasis> that contains the
absolute values of the contents of the vector
<emphasis role="bold">a</emphasis>.
</para>
<para><emphasis role="bold">Result value:</emphasis>
The value of each element of <emphasis role="bold">r</emphasis> is the
absolute value of the corresponding element of
<emphasis role="bold">a</emphasis>. For integer vectors, the arithmetic
is modular.
</para>
<para><emphasis role="bold">Endian considerations:</emphasis>
None.
</para>
<indexterm>
<primary>vspltisw</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>vsububm</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>vmaxsb</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>vsubuwm</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>vmaxsw</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>vsubudm</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>vmaxsd</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>xvabssp</primary>
<secondary>vec_abs</secondary>
</indexterm>
<indexterm>
<primary>xvabsdp</primary>
<secondary>vec_abs</secondary>
</indexterm>
<table frame="all">
<title>Supported type signatures for vec_abs</title>
<tgroup cols="3">
<colspec colname="c1" colwidth="20*" />
<colspec colname="c2" colwidth="20*" />
<colspec colname="c3" colwidth="20*" />
<thead>
<row>
<entry align="center">
<para>
<emphasis role="bold">r</emphasis>
</para>
</entry>
<entry align="center">
<para>
<emphasis role="bold">a</emphasis>
</para>
</entry>
<entry align="center">
<para>
<emphasis role="bold">Example Implementation</emphasis>
</para>
</entry>
</row>
</thead>
<tbody>
<row>
<entry align="center" valign="middle">
<para>vector signed char</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed char</para>
</entry>
<entry>
<programlisting>
vspltisw t,0
vsububm t,t,a
vmaxsb r,t,a
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed short</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed short</para>
</entry>
<entry>
<programlisting>
vspltisw t,0
vsubuhm t,t,a
vmaxsh r,t,a
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry>
<programlisting>
vspltisw t,0
vsubuwm t,t,a
vmaxsw r,t,a
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed long long</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed long long</para>
</entry>
<entry>
<programlisting>
vspltisw t,0
vsubudm t,t,a
vmaxsd r,t,a
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector float</para>
</entry>
<entry align="center" valign="middle">
<para>vector float</para>
</entry>
<entry>
<programlisting>
xvabssp r,a
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector double</para>
</entry>
<entry align="center" valign="middle">
<para>vector double</para>
</entry>
<entry>
<programlisting>
xvabsdp r,a
</programlisting>
</entry>
</row>
</tbody>
</tgroup>
</table>
2 years ago
</section>
<?hard-pagebreak?>
2 years ago
<section xml:id="vec_absd">
<title>vec_absd</title>
<subtitle>Vector Absolute Difference</subtitle>
<programlisting>
r = vec_absd (a, b)
</programlisting>
<para><emphasis role="bold">Purpose:</emphasis>
Computes the absolute difference of two vectors.
</para>
<para><emphasis role="bold">Result value:</emphasis>
The value of each element of <emphasis role="bold">r</emphasis> is the
absolute difference of the corresponding elements of <emphasis
role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>, using
modular arithmetic.
</para>
<para><emphasis role="bold">Endian considerations:</emphasis>
None.
</para>
<indexterm>
<primary>vabsdub</primary>
<secondary>vec_absd</secondary>
</indexterm>
<indexterm>
<primary>vabsduh</primary>
<secondary>vec_absd</secondary>
</indexterm>
<indexterm>
<primary>vabsduw</primary>
<secondary>vec_absd</secondary>
</indexterm>
<table frame="all">
<title>Supported type signatures for vec_absd</title>
<tgroup cols="5">
<colspec colname="c1" colwidth="20*" />
<colspec colname="c2" colwidth="20*" />
<colspec colname="c3" colwidth="20*" />
<colspec colname="c4" colwidth="20*" />
<colspec colname="c5" colwidth="20*" />
<thead>
<row>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">r</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">a</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">b</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">Example Implementation</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">Restrictions</emphasis>
</para>
</entry>
</row>
</thead>
<tbody>
<row>
<entry align="center" valign="middle">
<para>vector unsigned char</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned char</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned char</para>
</entry>
<entry>
<programlisting>
vabsdub r,a,b
</programlisting>
</entry>
<entry align="center" valign="middle">
<para>ISA 3.0 or later</para>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned short</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned short</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned short</para>
</entry>
<entry>
<programlisting>
vabsduh r,a,b
</programlisting>
</entry>
<entry align="center" valign="middle">
<para>ISA 3.0 or later</para>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry>
<programlisting>
vabsduw r,a,b
</programlisting>
</entry>
<entry align="center" valign="middle">
<para>ISA 3.0 or later</para>
</entry>
</row>
</tbody>
</tgroup>
</table>
2 years ago
</section>
<?hard-pagebreak?>
2 years ago
<section xml:id="vec_abss">
<title>vec_abss</title>
<subtitle>Vector Absolute Value Saturated</subtitle>
<programlisting>
r = vec_abss (a)
</programlisting>
<para><emphasis role="bold">Purpose:</emphasis>
Returns a vector <emphasis role="bold">r</emphasis> that contains the
saturated absolute values of the contents of the vector
<emphasis role="bold">a</emphasis>.
</para>
<para><emphasis role="bold">Result value:</emphasis>
The value of each element of <emphasis role="bold">r</emphasis> is the
saturated absolute value of the corresponding element of
<emphasis role="bold">a</emphasis>.
</para>
<para><emphasis role="bold">Endian considerations:</emphasis>
None.
</para>
<indexterm>
<primary>vspltisb</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vsubsbs</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vmaxsb</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vspltish</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vsubshs</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vmaxsh</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vspltisw</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vsubsws</primary>
<secondary>vec_abss</secondary>
</indexterm>
<indexterm>
<primary>vmaxsw</primary>
<secondary>vec_abss</secondary>
</indexterm>
<table frame="all">
<title>Supported type signatures for vec_abss</title>
<tgroup cols="3">
<colspec colname="c1" colwidth="20*" />
<colspec colname="c2" colwidth="20*" />
<colspec colname="c3" colwidth="20*" />
<thead>
<row>
<entry align="center">
<para>
<emphasis role="bold">r</emphasis>
</para>
</entry>
<entry align="center">
<para>
<emphasis role="bold">a</emphasis>
</para>
</entry>
<entry align="center">
<para>
<emphasis role="bold">Example Implementation</emphasis>
</para>
</entry>
</row>
</thead>
<tbody>
<row>
<entry align="center" valign="middle">
<para>vector signed char</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed char</para>
</entry>
<entry>
<programlisting>
vspltisb t,0
vsubsbs t,t,a
vmaxsb r,t,a
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed short</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed short</para>
</entry>
<entry>
<programlisting>
vspltish t,0
vsubshs t,t,a
vmaxsh r,t,a
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry>
<programlisting>
vspltisw t,0
vsubsws t,t,a
vmaxsw r,t,a
</programlisting>
</entry>
</row>
</tbody>
</tgroup>
</table>
2 years ago
</section>
<?hard-pagebreak?>
2 years ago
<section xml:id="vec_add">
<title>vec_add</title>
<subtitle>Vector Addition</subtitle>
<programlisting>
r = vec_add (a, b)
</programlisting>
<para><emphasis role="bold">Purpose:</emphasis>
Computes the sum of two vectors.
</para>
<para><emphasis role="bold">Result value:</emphasis>
The value of each element of <emphasis role="bold">r</emphasis> is the
sum of the corresponding elements of <emphasis
role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>. Modular
arithmetic is used for both signed and unsigned integers.
</para>
<para><emphasis role="bold">Endian considerations:</emphasis>
None.
</para>
<indexterm>
<primary>vaddubm</primary>
<secondary>vec_add</secondary>
</indexterm>
<indexterm>
<primary>vadduhm</primary>
<secondary>vec_add</secondary>
</indexterm>
<indexterm>
<primary>vadduwm</primary>
<secondary>vec_add</secondary>
</indexterm>
<indexterm>
<primary>vaddudm</primary>
<secondary>vec_add</secondary>
</indexterm>
<indexterm>
<primary>vadduqm</primary>
<secondary>vec_add</secondary>
</indexterm>
<indexterm>
<primary>xvaddsp</primary>
<secondary>vec_add</secondary>
</indexterm>
<indexterm>
<primary>xvadddp</primary>
<secondary>vec_add</secondary>
</indexterm>
<table frame="all">
<title>Supported type signatures for vec_add</title>
<tgroup cols="4">
<colspec colname="c1" colwidth="20*" />
<colspec colname="c2" colwidth="20*" />
<colspec colname="c3" colwidth="20*" />
<colspec colname="c4" colwidth="20*" />
<thead>
<row>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">r</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">a</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">b</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">Example Implementation</emphasis>
</para>
</entry>
</row>
</thead>
<tbody>
<row>
<entry align="center" valign="middle">
<para>vector signed char</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed char</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed char</para>
</entry>
<entry>
<programlisting>
vaddubm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned char</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned char</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned char</para>
</entry>
<entry>
<programlisting>
vaddubm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed short</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed short</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed short</para>
</entry>
<entry>
<programlisting>
vadduhm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned short</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned short</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned short</para>
</entry>
<entry>
<programlisting>
vadduhm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry>
<programlisting>
vadduwm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry>
<programlisting>
vadduwm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed long long</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed long long</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed long long</para>
</entry>
<entry>
<programlisting>
vaddudm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned long long</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned long long</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned long long</para>
</entry>
<entry>
<programlisting>
vaddudm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed __int128</para>
</entry>
<entry>
<programlisting>
vadduqm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned __int128</para>
</entry>
<entry>
<programlisting>
vadduqm r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector float</para>
</entry>
<entry align="center" valign="middle">
<para>vector float</para>
</entry>
<entry align="center" valign="middle">
<para>vector float</para>
</entry>
<entry>
<programlisting>
xvaddsp r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector double</para>
</entry>
<entry align="center" valign="middle">
<para>vector double</para>
</entry>
<entry align="center" valign="middle">
<para>vector double</para>
</entry>
<entry>
<programlisting>
xvadddp r,a,b
</programlisting>
</entry>
</row>
</tbody>
</tgroup>
</table>
2 years ago
</section>
<?hard-pagebreak?>
2 years ago
<section xml:id="vec_addc">
<title>vec_addc</title>
<subtitle>Vector Add Carrying</subtitle>
<programlisting>
r = vec_addc (a, b)
</programlisting>
<para><emphasis role="bold">Purpose:</emphasis>
Returns a vector of carries produced by adding two vectors.
</para>
<para><emphasis role="bold">Result value:</emphasis>
The value of each element of <emphasis role="bold">r</emphasis> is the
carry produced by adding the corresponding elements of <emphasis
role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> (1
if there is a carry, 0 otherwise).
</para>
<para><emphasis role="bold">Endian considerations:</emphasis>
None.
</para>
<indexterm>
<primary>vaddcuw</primary>
<secondary>vec_addc</secondary>
</indexterm>
<indexterm>
<primary>vaddcuq</primary>
<secondary>vec_addc</secondary>
</indexterm>
<table frame="all">
<title>Supported type signatures for vec_addc</title>
<tgroup cols="4">
<colspec colname="c1" colwidth="20*" />
<colspec colname="c2" colwidth="20*" />
<colspec colname="c3" colwidth="20*" />
<colspec colname="c4" colwidth="20*" />
<thead>
<row>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">r</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">a</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">b</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">Example Implementation</emphasis>
</para>
</entry>
</row>
</thead>
<tbody>
<row>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed int</para>
</entry>
<entry>
<programlisting>
vaddcuw r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned int</para>
</entry>
<entry>
<programlisting>
vaddcuw r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector signed __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector signed __int128</para>
</entry>
<entry>
<programlisting>
vaddcuq r,a,b
</programlisting>
</entry>
</row>
<row>
<entry align="center" valign="middle">
<para>vector unsigned __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned __int128</para>
</entry>
<entry align="center" valign="middle">
<para>vector unsigned __int128</para>
</entry>
<entry>
<programlisting>
vaddcuq r,a,b
</programlisting>
</entry>
</row>
</tbody>
</tgroup>
</table>
2 years ago
</section>
<?hard-pagebreak?>
2 years ago
<section xml:id="vec_adde">
<title>vec_adde</title>
<subtitle>Vector Add Extended</subtitle>
<programlisting>
r = vec_adde (a, b, c)
</programlisting>
<para><emphasis role="bold">Purpose:</emphasis>
Returns a vector formed as the sum of two vectors and a carry vector.
</para>
<para><emphasis role="bold">Result value:</emphasis>
The value of each element of <emphasis role="bold">r</emphasis> is
produced by adding the corresponding elements of <emphasis
role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> with
a carry specified in the corresponding element of <emphasis
role="bold">c</emphasis> (1 if there is a carry, 0 otherwise).
</para>
<para><emphasis role="bold">Endian considerations:</emphasis>
None.
</para>
<para><emphasis role="bold">Notes:</emphasis>
Code generated for this intrinsic should ensure only the
low-order bit of <emphasis role="bold">c</emphasis> participates
in the sum.
</para>
<indexterm>
<primary>vspltisw</primary>
<secondary>vec_adde</secondary>
</indexterm>
<indexterm>
<primary>vadduwm</primary>
<secondary>vec_adde</secondary>
</indexterm>
<indexterm>
<primary>xxland</primary>
<secondary>vec_adde</secondary>
</indexterm>
<indexterm>
<primary>vaddeuqm</primary>
<secondary>vec_adde</secondary>
</indexterm>
<table frame="all">
<title>Supported type signatures for vec_adde</title>
<tgroup cols="5">
<colspec colname="c1" colwidth="20*" />
<colspec colname="c2" colwidth="20*" />
<colspec colname="c3" colwidth="20*" />
<colspec colname="c4" colwidth="20*" />
<colspec colname="c5" colwidth="20*" />
<thead>
<row>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">r</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">a</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">b</emphasis>
</para>
</entry>
<entry align="center" valign="middle">
<para>
<emphasis role="bold">c</emphasis>