Address a few review comments from Will Schmidt.

master
Bill Schmidt 3 years ago
parent 49e3ac00e5
commit 03b142e07a

@ -381,7 +381,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
AIX, POWER7, POWER8, POWER9, and Power10 are trademarks or AIX, POWER7, POWER8, POWER9, and Power10 are trademarks or
registered trademarks of International Business Machines registered trademarks of International Business Machines
Corporation. Linux is a registered trademark of Linus Corporation. Linux is a registered trademark of Linus
Torvalds. Intel is s registered trademark of Intel Corporation Torvalds. Intel is a registered trademark of Intel Corporation
or its subsidiaries. AltiVec is a trademark of Freescale or its subsidiaries. AltiVec is a trademark of Freescale
Semiconductor, Inc. Semiconductor, Inc.
</para> </para>

@ -254,9 +254,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
Access to the portability APIs occurs automatically when Access to the portability APIs occurs automatically when
including one of the corresponding Intel header files, such as including one of the corresponding Intel header files, such as
<code>&lt;mmintrin.h&gt;</code>. <phrase <code>&lt;mmintrin.h&gt;</code>. <phrase
revisionflag="added">You must also compile with revisionflag="added">To enable the portability headers, you
<code>-DNO_WARN_X86_INTRINSICS</code> to opt into using the must compile with
headers.</phrase> <code>-DNO_WARN_X86_INTRINSICS</code>.</phrase>
</para> </para>
</section> </section>
<section xml:id="VIPR.techniques.pveclib"> <section xml:id="VIPR.techniques.pveclib">

@ -10255,7 +10255,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
None. None.
</para> </para>
<para><emphasis role="bold">Review status:</emphasis> <para><emphasis role="bold">Review status:</emphasis>
Not yet reviewed. Reviewed by Will Schmidt.
</para> </para>
<indexterm> <indexterm>
@ -19618,7 +19618,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
not address an element boundary. not address an element boundary.
</para> </para>
<para><emphasis role="bold">Review status:</emphasis> <para><emphasis role="bold">Review status:</emphasis>
Not yet reviewed. Reviewed by Will Schmidt.
</para> </para>
<indexterm> <indexterm>
@ -41617,11 +41617,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
<emphasis role="bold">a</emphasis> and <emphasis <emphasis role="bold">a</emphasis> and <emphasis
role="bold">b</emphasis>, with <emphasis role="bold">b</emphasis>, with <emphasis
role="bold">a</emphasis> on the left. Let <emphasis role="bold">a</emphasis> on the left. Let <emphasis
role="bold">v'</emphasis> be <emphasis role="bold">v</emphasis> role="bold">w</emphasis> be <emphasis role="bold">v</emphasis>
shifted left by the number of bits specified by <emphasis shifted left by the number of bits specified by <emphasis
role="bold">c</emphasis>. Then <emphasis role="bold">c</emphasis>. Then <emphasis
role="bold">r</emphasis> is set to the leftmost 128 bits of role="bold">r</emphasis> is set to the leftmost 128 bits of
<emphasis role="bold">v'</emphasis>. <emphasis role="bold">w</emphasis>.
</para> </para>
<para><emphasis role="bold">Endian considerations:</emphasis> <para><emphasis role="bold">Endian considerations:</emphasis>
The semantics of this built-in function differ for big-endian The semantics of this built-in function differ for big-endian
@ -41632,7 +41632,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
0 and 7, inclusive. 0 and 7, inclusive.
</para> </para>
<para><emphasis role="bold">Review status:</emphasis> <para><emphasis role="bold">Review status:</emphasis>
Not yet reviewed. Reviewed by Will Schmidt.
</para> </para>
<indexterm> <indexterm>
@ -43843,7 +43843,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
None. None.
</para> </para>
<para><emphasis role="bold">Review status:</emphasis> <para><emphasis role="bold">Review status:</emphasis>
Not yet reviewed. Reviewed by Will Schmidt.
</para> </para>
<indexterm> <indexterm>
@ -43952,7 +43952,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
targets, and right-to-left for little-endian targets. targets, and right-to-left for little-endian targets.
</para> </para>
<para><emphasis role="bold">Review status:</emphasis> <para><emphasis role="bold">Review status:</emphasis>
Not yet reviewed. Reviewed by Will Schmidt.
</para> </para>
<indexterm> <indexterm>
@ -45129,11 +45129,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
<emphasis role="bold">a</emphasis> and <emphasis <emphasis role="bold">a</emphasis> and <emphasis
role="bold">b</emphasis>, with <emphasis role="bold">b</emphasis>, with <emphasis
role="bold">a</emphasis> on the left. Let <emphasis role="bold">a</emphasis> on the left. Let <emphasis
role="bold">v'</emphasis> be <emphasis role="bold">v</emphasis> role="bold">w</emphasis> be <emphasis role="bold">v</emphasis>
shifted right by the number of bits specified by <emphasis shifted right by the number of bits specified by <emphasis
role="bold">c</emphasis>. Then <emphasis role="bold">c</emphasis>. Then <emphasis
role="bold">r</emphasis> is set to the rightmost 128 bits of role="bold">r</emphasis> is set to the rightmost 128 bits of
<emphasis role="bold">v'</emphasis>. <emphasis role="bold">w</emphasis>.
</para> </para>
<para><emphasis role="bold">Endian considerations:</emphasis> <para><emphasis role="bold">Endian considerations:</emphasis>
The semantics of this built-in function differ for big-endian The semantics of this built-in function differ for big-endian
@ -45144,7 +45144,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
0 and 7, inclusive. 0 and 7, inclusive.
</para> </para>
<para><emphasis role="bold">Review status:</emphasis> <para><emphasis role="bold">Review status:</emphasis>
Not yet reviewed. Reviewed by Will Schmidt.
</para> </para>
<indexterm> <indexterm>

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