diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml
index 262d9fa..b514a1d 100644
--- a/Intrinsics_Reference/ch_vec_reference.xml
+++ b/Intrinsics_Reference/ch_vec_reference.xml
@@ -5224,34 +5224,41 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
role="bold">a.
Endian considerations:
- None.
+ Differences in element numbering require different implementations
+ for big- and little-endian code generation.
Supported type signatures for vec_doublee
-
+
+
-
+
r
-
+
a
- Example Implementation
+ Example LE Implementation
+
+ Example BE Implementation
+
+
+
Restrictions
@@ -5268,7 +5275,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,1
+ xvcvsxwdp r,t
+
+
+
+
+ xvcvsxwdp r,a
+
@@ -5284,7 +5298,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,1
+ xvcvuxwdp r,t
+
+
+
+
+ xvcvuxwdp r,a
+
@@ -5300,7 +5321,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,1
+ xvcvspdp r,t
+
+
+
+
+ xvcvspdp r,a
+
@@ -5331,34 +5359,41 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
role="bold">a.
Endian considerations:
- None.
+ Differences in element numbering require different implementations
+ for big- and little-endian code generation.
Supported type signatures for vec_doubleh
-
+
+
-
+
r
-
+
a
- Example Implementation
+ Example LE Implementation
+
+ Example BE Implementation
+
+
+
Restrictions
@@ -5375,7 +5410,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,3
+ xxsldwi u,a,t,2
+ xvcvsxwdp r,u
+
+
+
+
+ xxsldwi t,a,a,1
+ xxsldwi u,t,a,3
+ xvcvsxwdp r,u
@@ -5391,7 +5435,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,3
+ xxsldwi u,a,t,2
+ xvcvuxwdp r,u
+
+
+
+
+ xxsldwi t,a,a,1
+ xxsldwi u,t,a,3
+ xvcvuxwdp r,u
@@ -5407,7 +5460,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,3
+ xxsldwi u,a,t,2
+ xvcvspdp r,u
+
+
+
+
+ xxsldwi t,a,a,1
+ xxsldwi u,t,a,3
+ xvcvspdp r,u
@@ -5438,34 +5500,41 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
role="bold">a.
Endian considerations:
- None.
+ Differences in element numbering require different implementations
+ for big- and little-endian code generation.
Supported type signatures for vec_doublel
-
+
+
-
+
r
-
+
a
- Example Implementation
+ Example LE Implementation
+
+ Example BE Implementation
+
+
+
Restrictions
@@ -5482,7 +5551,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,1
+ xxsldwi u,t,a,3
+ xvcvsxwdp r,u
+
+
+
+
+ xxsldwi t,a,a,3
+ xxsldwi u,a,t,2
+ xvcvsxwdp r,u
@@ -5498,7 +5576,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,1
+ xxsldwi u,t,a,3
+ xvcvuxwdp r,u
+
+
+
+
+ xxsldwi t,a,a,3
+ xxsldwi u,a,t,2
+ xvcvuxwdp r,u
@@ -5514,7 +5601,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xxsldwi t,a,a,1
+ xxsldwi u,t,a,3
+ xvcvspdp r,u
+
+
+
+
+ xxsldwi t,a,a,3
+ xxsldwi u,a,t,2
+ xvcvspdp r,u
@@ -5545,34 +5641,41 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
role="bold">a.
Endian considerations:
- None.
+ Differences in element numbering require different implementations
+ for big- and little-endian code generation.
Supported type signatures for vec_doubleo
-
+
+
-
+
r
-
+
a
- Example Implementation
+ Example LE Implementation
+
+ Example BE Implementation
+
+
+
Restrictions
@@ -5589,7 +5692,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xvcvsxwdp r,a
+
+
+
+
+
+ xxsldwi t,a,a,1
+ xvcvsxwdp r,t
@@ -5605,7 +5715,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xvcvuxwdp r,a
+
+
+
+
+
+ xxsldwi t,a,a,1
+ xvcvuxwdp r,t
@@ -5621,7 +5738,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- [TBD]
+ xvcvspdp r,a
+
+
+
+
+
+ xxsldwi t,a,a,1
+ xvcvspdp r,t
@@ -6005,40 +6129,52 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
The element numbering within a register is left-to-right for big-endian
targets, and right-to-left for little-endian targets.
+ Notes:
+ Prior to ISA 3.0, less efficient code sequences must be used to
+ implement vec_extract.
+
Supported type signatures for vec_extract
-
+
-
-
-
+
+
+
+
-
+
r
-
+
a
-
+
b
- Example LE Implementation
+ Example ISA 3.0 LE
+ Implementation
- Example BE Implementation
+ Example ISA 3.0 BE
+ Implementation
+
+
+
+
+ Restrictions
@@ -6056,14 +6192,408 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- vexptefp r,a
+ vextubrx t,b,a
+ extsb r,t
- vexptefp r,a
+ vextublx t,b,a
+ extsb r,t
+
+
+
+
+
+
+
+
+ unsigned char
+
+
+ vector bool char
+
+
+ signed int
+
+
+
+ vextubrx t,b,a
+
+
+ vextublx t,b,a
+
+
+
+
+
+
+
+
+ unsigned char
+
+
+ vector unsigned char
+
+
+ signed int
+
+
+
+ vextubrx t,b,a
+
+
+
+
+ vextublx t,b,a
+
+
+
+
+
+
+
+
+ signed int
+
+
+ vector signed int
+
+
+ signed int
+
+
+
+ slwi t,b,2
+ vextuwrx u,t,a
+ extsw r,u
+
+
+
+
+ slwi t,b,2
+ vextuwlx u,t,a
+ extsw r,u
+
+
+
+
+
+
+
+
+ unsigned int
+
+
+ vector bool int
+
+
+ signed int
+
+
+
+ slwi t,b,2
+ vextuwrx r,t,a
+
+
+
+
+ slwi t,b,2
+ vextuwlx r,t,a
+
+
+
+
+
+
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ signed int
+
+
+
+ slwi t,b,2
+ vextuwrx r,t,a
+
+
+
+
+ slwi t,b,2
+ vextuwlx r,t,a
+
+
+
+
+
+
+
+
+ signed long long
+
+
+ vector signed long long
+
+
+ signed int
+
+
+
+ xori t,b,0x1
+ rldic u,t,6,57
+ mtvsrdd v,u,u
+ vslo w,a,v
+ mfvsrd r,w
+
+
+
+
+ rldic t,b,6,57
+ mtvsrdd u,t,t
+ vslo v,a,u
+ mfvsrd r,v
+
+
+
+
+
+
+
+
+
+ unsigned long long
+
+
+ vector bool long long
+
+
+ signed int
+
+
+
+ xori t,b,0x1
+ rldic u,t,6,57
+ mtvsrdd v,u,u
+ vslo w,a,v
+ mfvsrd r,w
+
+
+
+
+ rldic t,b,6,57
+ mtvsrdd u,t,t
+ vslo v,a,u
+ mfvsrd r,v
+
+
+
+
+
+
+
+
+
+ unsigned long long
+
+
+ vector unsigned long long
+
+
+ signed int
+
+
+
+ xori t,b,0x1
+ rldic u,t,6,57
+ mtvsrdd v,u,u
+ vslo w,a,v
+ mfvsrd r,w
+
+
+
+
+ rldic t,b,6,57
+ mtvsrdd u,t,t
+ vslo v,a,u
+ mfvsrd r,v
+
+
+
+
+
+
+
+
+
+ signed short
+
+
+ vector signed short
+
+
+ signed int
+
+
+
+ slwi t,b,1
+ vextuhrx u,t,a
+ extsh r,u
+
+
+
+
+ slwi t,b,1
+ vextuhlx u,t,a
+ extsh r,u
+
+
+
+
+
+
+
+
+ unsigned short
+
+
+ vector bool short
+
+
+ signed int
+
+
+
+ slwi t,b,1
+ vextuhrx r,t,a
+
+
+
+
+ slwi t,b,1
+ vextuhlx r,t,a
+
+
+
+
+
+
+
+
+ unsigned short
+
+
+ vector unsigned short
+
+
+ signed int
+
+
+
+ slwi t,b,1
+ vextuhrx r,t,a
+
+
+
+
+ slwi t,b,1
+ vextuhlx r,t,a
+
+
+
+
+
+
+
+
+ double
+
+
+ vector double
+
+
+ signed int
+
+
+
+ xori t,b,0x1
+ rldic u,t,6,57
+ mtvsrdd v,u,u
+ vslo r,a,v
+
+
+
+
+ rldic t,b,6,57
+ mtvsrdd u,t,t
+ vslo r,a,u
+
+
+
+
+
+
+
+
+
+ float
+
+
+ vector float
+
+
+ signed int
+
+
+
+ rldicl t,b,0,62
+ subfic u,t,3
+ sldi v,u,5
+ mtvsrdd w,v,v
+ vslo x,a,w
+ xscvspdp r,x
+
+
+
+
+
+ sldi t,b,5
+ mtvsrdd u,t,t
+ vslo v,a,u
+ xscvspdp r,v
+
+
+
+
+
+
+
+
+
+ _Float16
+
+
+ vector _Float16
+
+
+ signed int
+
+
+ Not yet available
+
+
+ Not yet available
+
+
+ ISA 3.0 or later
+ Phased in
+
@@ -6074,19 +6604,23 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
vec_extract_exp
- Vector ... Spelled Out Name TBD
+ Vector Extract Exponent
- r = vec_extract_exp (ARG1)
+ r = vec_extract_exp (a)
Purpose:
Extracts an exponent from a floating-point number.
- Result value: Each element of the returned integer vector is extracted from the exponent field of the corresponding floating-point vector element.
-The extracted exponents of ARG1 are returned as
- right-justified unsigned integers containing biased exponents, in
- accordance with the exponent representation specified by IEEE
- 754, without further processing.
+ Result value:
+ Each element of r is extracted
+ from the exponent field of the corresponding floating-point
+ vector element of a.
+
+ The extracted exponents of a
+ are returned as right-justified unsigned integers containing biased
+ exponents, in accordance with the exponent representation specified
+ by IEEE 754, without further processing.
Endian considerations:
None.
@@ -6107,7 +6641,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- ARG1
+ a
@@ -6127,9 +6661,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
vector double
- sample implementation TBD
+
+ xvxexpdp r,a
+
-
+
ISA 3.0 or later
@@ -6141,9 +6677,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
vector float
- sample implementation TBD
+
+ xvxexpsp r,a
+
-
+
ISA 3.0 or later