diff --git a/Intrinsics_Reference/bk_main.xml b/Intrinsics_Reference/bk_main.xml
index d2b51a0..18a2e52 100644
--- a/Intrinsics_Reference/bk_main.xml
+++ b/Intrinsics_Reference/bk_main.xml
@@ -32,7 +32,7 @@
xml:id="bk_main">
- POWER Vector Intrinsic Programming Reference
+ Power Vector Intrinsic Programming Reference
diff --git a/Intrinsics_Reference/ch_biendian.xml b/Intrinsics_Reference/ch_biendian.xml
index 6b27880..26e0723 100644
--- a/Intrinsics_Reference/ch_biendian.xml
+++ b/Intrinsics_Reference/ch_biendian.xml
@@ -110,6 +110,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.biendian">
vector int x = (vector int) (4, -1, 3, 6);
vector double g = (vector double) { 3.5, -24.6 };
+
+ Current C comiplers do not support literals for
+ __int128 types. When constructing a vector
+ __int128 constant from smaller literals such as
+ int or long long, you must test for
+ endianness and reverse the order of the smaller literals for
+ little-endian mode.
+
@@ -584,6 +592,18 @@ register vector double vd = vec_splats(*double_ptr);
+
+
+ Note that each element in a vector has the same representation
+ in both big- and little-endian element orders. That is, an
+ int is always 32 bits, with the sign bit in the
+ high-order position. Programmers must be aware of this when
+ programming with mixed data types, such as an instruction that
+ multiplies two short elements to produce an
+ int element. Always access entire elements to
+ avoid potential endianness issues.
+
+
@@ -1174,7 +1194,9 @@ register vector double vd = vec_splats(*double_ptr);
reorder entire elements of a vector. If you must use vec_perm
for another purpose, your code must include a test for
endianness and separate algorithms for big- and
- little-endian.
+ little-endian. Examples of this may be seen in the Power
+ Vector Library project (see ).
diff --git a/Intrinsics_Reference/ch_intro.xml b/Intrinsics_Reference/ch_intro.xml
index ca9052a..9111954 100644
--- a/Intrinsics_Reference/ch_intro.xml
+++ b/Intrinsics_Reference/ch_intro.xml
@@ -79,16 +79,23 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
linkend="VIPR.intro.unified" />). The VSRs can represent all
the data types representable by the VRs, and can also be treated
as containing two 64-bit integers or two 64-bit double-precision
- floating-point values.
+ floating-point values. However, ISA support for two 64-bit
+ integers in VSRs was limited until Version 2.07 (POWER8) of the
+ Power ISA, and only the VRs are supported for these
+ instructions.
Both the VMX and VSX instruction sets have been expanded for the
POWER8 and POWER9 processor families. Starting with POWER8,
a VSR can now contain a single 128-bit integer; and starting
with POWER9, a VSR can contain a single 128-bit floating-point
- value. The VMX and VSX instruction sets together may be
- referred to as the Power SIMD (single-instruction,
- multiple-data) instructions.
+ value. Again, the ISA currently only supports 128-bit
+ operations on values in the VRs.
+
+
+ The VMX and VSX instruction sets together may be referred to as
+ the Power SIMD (single-instruction, multiple-data)
+ instructions.
Little-Endian Linux
@@ -162,6 +169,50 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
+
+ Where to Report Bugs
+
+ This reference provides guidance on using vector intrinsics that
+ are supported by all compatible compilers. If you find a
+ problem when using one of the intrinsics with a compatible
+ compiler, please report a bug! Bug reporting procedures differ
+ depending on which compiler you're using.
+
+
+
+
+ GCC. The reporting
+ procedure for bugs against the GNU Compiler Collection is
+ described at https://gcc.gnu.org/bugs/.
+ The GCC bugzilla tracker is located at https://gcc.gnu.org/bugzilla/.
+
+
+
+
+ Clang/LLVM. The
+ reporting procedure for bugs against the Clang compiler is
+ described at https://llvm.org/docs/HowToSubmitABug.html.
+ The LLVM bug tracking system is located at https://bugs.llvm.org/enter_bug.cgi.
+
+
+
+
+ The XL compilers.
+
+
+
+ Reporting procedures for XL bugs on Linux are yet to be
+ determined.
+
+
+
+
+
+
Useful Links
diff --git a/Intrinsics_Reference/ch_techniques.xml b/Intrinsics_Reference/ch_techniques.xml
index 5cab64e..0475c10 100644
--- a/Intrinsics_Reference/ch_techniques.xml
+++ b/Intrinsics_Reference/ch_techniques.xml
@@ -148,12 +148,19 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
described here, you should look for an equivalent one in this
manual and change your code to use that.
+
+ Where an intrinsic may not be available from all compilers or at
+ all ISA levels, this information is called out in the
+ description of the intrinsic in .
+
There are also other vector APIs that may be of use to you (see
). In particular, the
Power Vector Library (see ) provides additional
- portability across compiler versions.
+ portability across compiler versions, as well as interfaces that
+ hide cases where assembly language is needed.
diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml
index 466fba7..09ee225 100644
--- a/Intrinsics_Reference/ch_vec_reference.xml
+++ b/Intrinsics_Reference/ch_vec_reference.xml
@@ -123,7 +123,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
ISA 3.0 or later. This
form is only available starting with PowerISA 3.0,
- corresponding to POWER9 servers.
+ corresponding to POWER9 servers. The Power Vector Library
+ (see provides equivalent
+ POWER7/POWER8 implementations for many ISA 3.0 vector
+ instructions, which may be preferred for portability.
@@ -150,7 +153,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
-
+ Built-In Vector Functions