diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index 19f8792..16270dd 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -25116,23 +25116,44 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_xl_len - Vector ... Spelled Out Name TBD + Vector Load with Length - r = vec_xl_len (ARG1, ARG2) + r = vec_xl_len (a, b) Purpose: Loads a vector of a specified byte length. - Result value: Loads the number of bytes specified by ARG2 from the address specified in ARG1. Initializes elements in order from the byte stream (as defined by the endianness of the operating environment). Any bytes of elements that cannot be initialized from the number of loaded bytes have a zero value. -At least 0 and at most 16 bytes will be loaded. The length - is specified by the least-significant byte of ARG2, as min (mod - (ARG2, 256), 16). The behavior is undefined if the length - argument is outside of the range 0–255, or if it is not a - multiple of the vector element size. + Result value: Loads the number of + bytes specified by b from the address + specified in a. Initializes elements in + order from the byte stream (as defined by the endianness of the target). + Any bytes of elements that cannot be initialized from the + number of loaded bytes have a zero value. + Between 0 and 16 bytes, inclusive, will be loaded. The length is + specified by the least-significant byte of b, as min (b mod 256, 16). The behavior + is undefined if the length argument is outside of + the range 0–255, or if it is not a multiple of the vector element + size. Endian considerations: None. + Notes: + + + + vec_xl_len should not be used to load from cache-inhibited memory. + + + + + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred. + + + Supported type signatures for vec_xl_len @@ -25144,25 +25165,26 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - - Example Implementation + + Example + Implementation - + Restrictions @@ -25179,7 +25201,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25196,7 +25221,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25213,7 +25241,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25230,7 +25261,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25247,7 +25281,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25264,7 +25301,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25281,7 +25321,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25298,7 +25341,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25315,7 +25361,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25332,7 +25381,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25349,7 +25401,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25366,7 +25421,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later @@ -25383,10 +25441,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lxvl r,a,t + ISA 3.0 or later + Deferred @@ -25398,20 +25460,27 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_xl_len_r - Vector ... Spelled Out Name TBD + Vector Load with Length Right-Justified - r = vec_xl_len_r (ARG1, ARG2) + r = vec_xl_len_r (a, b) Purpose: - - - Result value: Loads the number of bytes specified by ARG2 from the address specified in ARG1, right justified with the first byte to the left and the last to the right. Initializes elements in order from the byte stream (as defined by the endianness of the operating environment). Any bytes of elements that cannot be initialized from the number of loaded bytes have a zero value. -At least 0 and at most 16 bytes will be loaded. The length - is specified by the least-significant byte of ARG2, as min (mod - (ARG2, 256), 16). The behavior is undefined if the length - argument is outside of the range 0–255, or if it is not a - multiple of the vector element size. + Loads a vector of a specified byte length, right-justified. + + Result value: Loads the number of + bytes specified by b from the address + specified in a, right justified in + r. Initializes elements in order from + the byte stream (as defined by the endianness of the target). + Any bytes of elements that cannot be initialized from the + number of loaded bytes have a zero value. + Between 0 and 16 bytes, inclusive, will be loaded. The length + is specified by the least-significant byte of b, as min (b mod 256, 16). The + behavior is undefined if the length argument is outside of the range + 0–255. Endian considerations: None. @@ -25426,25 +25495,26 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - - Example Implementation + + Example + Implementation - + Restrictions @@ -25461,7 +25531,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,b,56 + lvsl u,0,b + lxvll v,a,t + vperm r,v,v,u + ISA 3.0 or later @@ -25476,15 +25551,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_xor - Vector ... Spelled Out Name TBD + Vector Exclusive OR - r = vec_xor (ARG1, ARG2) + r = vec_xor (a, b) Purpose: Performs a bitwise XOR of the given vectors. - Result value: The result is the bitwise XOR of ARG1 and ARG2. + Result value: v is the bitwise + exclusive OR of a and b. Endian considerations: None. @@ -25498,22 +25575,22 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - + Example Implementation @@ -25530,7 +25607,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxlxor r,a,b + @@ -25544,7 +25623,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + xxlxor r,a,b + @@ -25558,7 +25639,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxlxor r,a,b + @@ -25572,7 +25655,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxlxor r,a,b + @@ -25586,7 +25671,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + xxlxor r,a,b + @@ -25600,7 +25687,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxlxor r,a,b + @@ -25614,7 +25703,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxlxor r,a,b + @@ -25628,7 +25719,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + xxlxor r,a,b + @@ -25642,7 +25735,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxlxor r,a,b + @@ -25656,7 +25751,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxlxor r,a,b + @@ -25670,7 +25767,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + xxlxor r,a,b + @@ -25684,7 +25783,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxlxor r,a,b + @@ -25698,7 +25799,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xxlxor r,a,b + @@ -25712,7 +25815,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xxlxor r,a,b + @@ -26043,7 +26148,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ISA 3.0 or later + Deferred @@ -26055,21 +26160,30 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_xst_be - Vector ... Spelled Out Name TBD + VSX Unaligned Store as Big Endian - r = vec_xst_be (ARG1, ARG2, ARG3) + vec_xst_be (a, b, c) Purpose: - In little-endian environments, stores the elements of the 16-byte vector ARG1 starting with the highest-numbered element at the memory address specified by the displacement ARG1 and the pointer ARG2. In big-endian environments, this operator performs the same operation as VEC_XST. + Stores a vector to an address using big-endian + element order, regardless of the endianness of the target machine. - Result value: In little-endian mode, stores the elements of the vector in sequential order, with the highest-numbered element stored at the lowest data address and the lowest-numbered element of the vector at the highest address. All elements are stored in little-endian data format. -This function adds the displacement and the pointer R-value - to obtain the address for the store operation. It does not - truncate the affected address to a multiple of 16 bytes. + Result value: The values of + b and c are added, and the value of a is stored to the resultant address using + big-endian element order. Endian considerations: - None. + In big-endian mode, this acts just like the vec_xst intrinsic. In + little-endian mode, the lowest data address receives the + highest-numbered element of a, and + the highest data address receives the lowest-numbered element of + a. + Notes: + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred.
Supported type signatures for vec_xst_be @@ -26082,39 +26196,36 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + - r + a - + - ARG1 + b - + - ARG2 + c - - - ARG3 - + + Example ISA 3.0 LE + Implementation - - Example Implementation + + Example ISA 3.0 BE + Implementation - + Restrictions - - void - vector signed char @@ -26125,16 +26236,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed char * - sample implementation TBD + + stxvb16x a,b,c + + + + + stxv a,b,c + - - void - vector unsigned char @@ -26145,16 +26260,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned char * - sample implementation TBD + + stxvb16x a,b,c + + + + + stxv a,b,c + - - void - vector signed int @@ -26165,16 +26284,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed int * - sample implementation TBD + + stxvw4x a,b,c + + + + + stxv a,b,c + - - void - vector unsigned int @@ -26185,16 +26308,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned int * - sample implementation TBD + + stxvw4x a,b,c + + + + + stxv a,b,c + - - void - vector signed __int128 @@ -26205,16 +26332,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed __int128 * - sample implementation TBD + + stxv a,b,c + + + + + stxv a,b,c + - - void - vector unsigned __int128 @@ -26225,16 +26356,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned __int128 * - sample implementation TBD + + stxv a,b,c + + + + + stxv a,b,c + - - void - vector signed long long @@ -26245,16 +26380,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed long long * - sample implementation TBD + + stxvd2x a,b,c + + + + + stxv a,b,c + - - void - vector unsigned long long @@ -26265,16 +26404,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned long long * - sample implementation TBD + + stxvd2x a,b,c + + + + + stxv a,b,c + - - void - vector signed short @@ -26285,16 +26428,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed short * - sample implementation TBD + + stxvh8x a,b,c + + + + + stxv a,b,c + - - void - vector unsigned short @@ -26305,16 +26452,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned short * - sample implementation TBD + + stxvh8x a,b,c + + + + + stxv a,b,c + - - void - vector double @@ -26325,16 +26476,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> double * - sample implementation TBD + + stxvd2x a,b,c + + + + + stxv a,b,c + - - void - vector float @@ -26345,16 +26500,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> float * - sample implementation TBD + + stxvw4x a,b,c + + + + + stxv a,b,c + - - void - vector _Float16 @@ -26365,10 +26524,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> _Float16 * - sample implementation TBD + + stxvb16x a,b,c + + + + + stxv a,b,c + - ISA 3.0 or later + Deferred @@ -26380,68 +26546,69 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_xst_len - Vector ... Spelled Out Name TBD + Vector Store with Length - r = vec_xst_len (ARG1, ARG2, ARG3) + vec_xst_len (a, b, c) Purpose: Stores a vector of a specified byte length. - Result value: Stores the number of bytes specified by ARG3 of the vector ARG1 to the address specified in ARG2. The bytes are obtained starting from the lowest-numbered byte of the lowest-numbered element (as defined by the endianness of the operating environment). All bytes of an element are accessed before proceeding to the next higher element. -At least 0 and at most 16 bytes will be stored. The length - is specified by the least-significant byte of ARG3, as min (mod - (ARG3, 256), 16). The behavior is undefined if the length - argument is outside of the range 0–255, or if it is not a - multiple of the vector element size. + Operation: Stores the number of + bytes specified by c of the vector + a to the address specified in + b. The bytes are obtained starting from + the lowest-numbered byte of the lowest-numbered element (as defined by + the endianness of the target). All bytes of an element + are accessed before proceeding to the next higher element. + Between 0 and 16 bytes, inclusive, will be stored. The length + is specified by the least-significant byte of c, as min (c mod 256, 16). The behavior + is undefined if the length argument is outside of the range 0–255, + or if it is not a multiple of the vector element size. Endian considerations: None. + Notes: + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred.
Supported type signatures for vec_xst_len - + - - - - r - - - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c - + Example Implementation - + Restrictions - - void - vector signed char @@ -26452,16 +26619,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector unsigned char @@ -26472,16 +26639,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector signed int @@ -26492,16 +26659,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector unsigned int @@ -26512,16 +26679,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector signed __int128 @@ -26532,16 +26699,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector unsigned __int128 @@ -26552,16 +26719,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector signed long long @@ -26572,16 +26739,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector unsigned long long @@ -26592,16 +26759,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector signed short @@ -26612,16 +26779,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector unsigned short @@ -26632,16 +26799,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector double @@ -26652,16 +26819,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector float @@ -26672,16 +26839,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later - - void - vector _Float16 @@ -26692,10 +26859,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + sldi t,c,56 + stxvl a,b,t + ISA 3.0 or later + Deferred @@ -26707,68 +26878,63 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_xst_len_r - Vector ... Spelled Out Name TBD + Vector Store with Length Right-Justified - r = vec_xst_len_r (ARG1, ARG2, ARG3) + vec_xst_len_r (a, b, c) Purpose: Stores a right-justified vector of a specified byte length. - Result value: Stores the number of bytes specified by ARG3 of the right-justified vector ARG1 to the address specified by ARG2. -At least 0 and at most 16 bytes will be stored. The length - is specified by the least-significant byte of ARG3, as min (mod - (ARG2, 256), 16). The behavior is undefined if the length - argument is outside of the range 0–255, or if it is not a - multiple of the vector element size. + Operation: Stores the number of + bytes specified by c of the + right-justified vector a to the address + specified by b. + Between 0 and 16 bytes, inclusive, will be stored. The length is + specified by the least-significant byte of c, as min (b mod 256, 16). The + behavior is undefined if the length argument is outside of the range + 0–255. Endian considerations: None.
Supported type signatures for vec_xst_len_r - + - - - - r - - - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c - + Example Implementation - + Restrictions - - void - vector unsigned char @@ -26779,7 +26945,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> size_t - sample implementation TBD + + lvsr t,0,c + sldi u,c,56 + vperm v,a,a,t + stxvll v,b,u + ISA 3.0 or later