From 7827422d711ccaff20a8fb4b5567c061bf92c3f8 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Sun, 30 Dec 2018 12:42:21 -0600 Subject: [PATCH] Completed copying entries from Appendix A. Signed-off-by: Bill Schmidt --- Intrinsics_Reference/ch_vec_reference.xml | 411 +++++++++++++++++----- 1 file changed, 324 insertions(+), 87 deletions(-) diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index dba150b..1091dc6 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -6888,18 +6888,33 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_cipher_be - Vector ... Spelled Out Name TBD + Vector AES Cipher Big-Endian - r = vec_cipher_be (ARG1, ARG2) + r = vec_cipher_be (a, b) Purpose: - Performs one round of the AES cipher operation on an intermediate state state_array by using a given round_key. + Performs one round of the AES cipher operation on an intermediate state + array a by using a given round key + b. + + + Result value: r contains the + resulting intermediate state, after one round of the AES cipher + operation on intermediate state array a, + using the round key specified by b. Endian considerations: - None. + All element and bit numberings of the AES cipher operation use + big-endian (i.e., left-to-right) order, reflecting the underlying + hardware insruction. Unlike most of the vector intrinsics in this + chapter, vec_cipher_be does not follow the bi-endian + programming model. + + Notes: This intrinsic may + not yet be available in all implementations. Supported type signatures for vec_cipher_be @@ -6917,12 +6932,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -6942,7 +6957,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vcipher r,a,b + @@ -6954,18 +6971,33 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_cipherlast_be - Vector ... Spelled Out Name TBD + Vector AES Cipher Last Big-Endian - r = vec_cipherlast_be (ARG1, ARG2) + r = vec_cipherlast_be (a, b) Purpose: - Performs the final round of the AES cipher operation on an intermediate state state_array using the specified round_key. + Performs the final round of the AES cipher operation on an intermediate + state array a using the specified + round key b. + + + Result value: r contains the + resulting final state, after the final round of the AES cipher + operation on intermediate state array a, + using the round key specified by b. Endian considerations: - None. + All element and bit numberings of the AES cipher-last operation use + big-endian (i.e., left-to-right) order, reflecting the underlying + hardware insruction. Unlike most of the vector intrinsics in this + chapter, vec_cipherlast_be does not follow the bi-endian + programming model. + + Notes: This intrinsic may + not yet be available in all implementations.
Supported type signatures for vec_cipherlast_be @@ -6983,12 +7015,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -7008,7 +7040,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vcipherlast r,a,b + @@ -15808,17 +15842,25 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_mfvscr - Vector ... Spelled Out Name TBD + Vector Move From Vector Status and Control Register r = vec_mfvscr () Purpose: - Copies the contents of the Vector Status and Control Register into the result vector. + Copies the contents of the Vector Status and Control Register into the + result vector. + + Result value: The high-order 16 + bits of the VSCR are copied into the seventh element of r, using big-endian (left-to-right) order. The + low-order 16 bits of the VSCR are copied into the eighth element of + r, using big-endian order. All other + elements of r are set to zero. - Result value: The high-order 16 bits of the VSCR are copied into the seventh element of the result. The low-order 16 bits of the VSCR are copied into the eighth element of the result. All other elements are set to zero. Endian considerations: - None. + The contents of the VSCR are placed in the low-order 32 bits of the + result vector, regardless of endianness.
@@ -15834,7 +15876,8 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - Example Implementation + Example + Implementation @@ -15844,7 +15887,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + mfvscr a + @@ -16513,14 +16558,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_mtvscr - Vector ... Spelled Out Name TBD + Vector Move to Vector Status and Control Register - r = vec_mtvscr (ARG1) + r = vec_mtvscr (a) Purpose: - Copies the given value into the Vector Status and Control Register. The low-order 32 bits of ARG1 are copied into the VSCR. + Copies the given value into the Vector Status and Control Register. + The low-order 32 bits of a are copied + into the VSCR. + + Result value: None. Endian considerations: None. @@ -16541,11 +16590,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - Example Implementation + Example + Implementation @@ -16558,7 +16608,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + mtvscr a + @@ -16569,7 +16621,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + mtvscr a + @@ -16580,7 +16634,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + mtvscr a + @@ -16591,7 +16647,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + mtvscr a + @@ -16602,7 +16660,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + mtvscr a + @@ -16613,7 +16673,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + mtvscr a + @@ -16624,7 +16686,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector pixel - sample implementation TBD + + mtvscr a + @@ -16635,7 +16699,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + mtvscr a + @@ -16646,7 +16712,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + mtvscr a + @@ -16657,7 +16725,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + mtvscr a + @@ -17696,24 +17766,38 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
- - + vec_ncipher_be - Vector ... Spelled Out Name TBD + Vector AES Inverse Cipher Big-Endian - r = vec_ncipher_be (ARG1, ARG2) + r = vec_ncipher_be (a, b) Purpose: - Performs one round of the AES inverse cipher operation on an intermediate state state_array using a given round_key. + Performs one round of the AES inverse cipher operation on an + intermediate state array a by using a + given round key b. + + + Result value: r contains the + resulting intermediate state, after one round of the AES inverse cipher + operation on intermediate state array a, + using the round key specified by b. Endian considerations: - None. + All element and bit numberings of the AES inverse cipher operation use + big-endian (i.e., left-to-right) order, reflecting the underlying + hardware insruction. Unlike most of the vector intrinsics in this + chapter, vec_ncipher_be does not follow the bi-endian + programming model. + + Notes: This intrinsic may + not yet be available in all implementations. Supported type signatures for vec_ncipher_be @@ -17731,12 +17815,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -17756,7 +17840,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vncipher r,a,b + @@ -17768,18 +17854,33 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_ncipherlast_be - Vector ... Spelled Out Name TBD + Vector AES Inverse Cipher Last Big-Endian - r = vec_ncipherlast_be (ARG1, ARG2) + r = vec_ncipherlast_be (a, b) Purpose: - Performs the final round of the AES inverse cipher operation on an intermediate state state_array using the specified round_key. + Performs the final round of the AES inverse cipher operation on an + intermediate state array a using the + specified round key b. + + + Result value: r contains the + resulting final state, after the final round of the AES inverse cipher + operation on intermediate state array a, + using the round key specified by b. Endian considerations: - None. + All element and bit numberings of the AES inverse cipher-last operation + use big-endian (i.e., left-to-right) order, reflecting the underlying + hardware insruction. Unlike most of the vector intrinsics in this + chapter, vec_ncipherlast_be does not follow the bi-endian + programming model. + + Notes: This intrinsic may + not yet be available in all implementations.
Supported type signatures for vec_ncipherlast_be @@ -17797,12 +17898,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -17822,7 +17923,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vncipherlast r,a,b + @@ -20807,17 +20910,33 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_pmsum_be - Vector ... Spelled Out Name TBD + Vector Polynomial Multiply-Sum Big-Endian - r = vec_pmsum_be (ARG1, ARG2) + r = vec_pmsum_be (a, b) Purpose: - Performs the exclusive-OR operation (implementing polynomial addition) on each even-odd pair of the polynomial-multiplication result of the corresponding elements. + Performs the exclusive-OR operation (implementing polynomial addition) + on each even-odd pair of the polynomial-multiplication result of the + corresponding elements of a and + b. + + Result value: Each element + i of r is + computed by an exclusive-OR operation of the polynomial + multiplication of input elements 2 × i of + a and b and input elements 2 × + i + 1 of a and + b. Endian considerations: - None. + All element numberings in the above description denote big-endian + (i.e., left-to-right) order, reflecting the underlying hardware + insruction. Unlike most of the vector intrinsics in this chapter, + vec_pmsum_be does not follow the bi-endian + programming model.
@@ -20829,22 +20948,22 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - + Example Implementation @@ -20861,7 +20980,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vpmsumh r,a,b + @@ -20875,7 +20996,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vpmsumd r,a,b + @@ -20889,7 +21012,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vpmsumw r,a,b + @@ -20903,7 +21028,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpmsumb r,a,b + @@ -22658,18 +22785,32 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sbox_be - Vector ... Spelled Out Name TBD + Vector AES SubBytes Big-Endian - r = vec_sbox_be (ARG1) + r = vec_sbox_be (a) Purpose: - Performs the SubBytes operation, as defined in Federal Information Processing Standards FIPS-197, on a state_array. + Performs the SubBytes operation, as defined in Federal Information + Processing Standards FIPS-197, on a state_array contained in + a. + + Result value: r contains the + result of the SubBytes operation, as defined in Federal Information + Processing Standard FIPS-197, on the state array represented by + a. Endian considerations: - None. + All element numberings of the SubBytes operation use + big-endian (i.e., left-to-right) order, reflecting the underlying + hardware insruction. Unlike most of the vector intrinsics in this + chapter, vec_sbox_be does not follow the bi-endian + programming model. + + Notes: This intrinsic may + not yet be available in all implementations.
Supported type signatures for vec_sbox_be @@ -22686,7 +22827,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -22703,7 +22844,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsbox r,a + @@ -23447,17 +23590,107 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_shasigma_be - Vector ... Spelled Out Name TBD + Vector SHA Sigma Big-Endian - r = vec_shasigma_be (ARG1, ARG2, ARG3) + r = vec_shasigma_be (a, b, c) Purpose: - Performs a Secure Hash computation in accordance with Federal Information Processing Standards FIPS-180-3. + Performs a Secure Hash computation in accordance with Federal + Information Processing Standards FIPS-180-3. + Result value: Each element of + r contains the SHA256 or SHA512 hash + as follows. + + + The result of the SHA-256 function (r[i] for + i = 0 to 3) is: + + + + σ0(a[i]), if b is 0 and bit i of + the 4-bit c is 0. + + + + + σ1(a[i]), if b is 0 and bit i of + the 4-bit c is 1. + + + + + Σ0(a[i]), if b is nonzero and bit i + of the 4-bit c is 0. + + + + + Σ1(a[i]), if b is nonzero and bit i + of the 4-bit c is 1. + + + + + The result of the SHA-512 function (r[i] for + i = 0 to 1) is: + + + + σ0(a[i]), if b is 0 and bit 2 × + i of the 4-bit c is 0. + + + + + σ1(a[i]), if b is 0 and bit 2 × + i of the 4-bit c is 1. + + + + + Σ0(a[i]), if b is nonzero and bit 2 × + i of the 4-bit c is 0. + + + + + Σ1(a[i]), if b is nonzero and bit 2 × + i of the 4-bit c is 1. + + + + Endian considerations: - None. + All element numberings in the above description denote big-endian + (i.e., left-to-right) order, reflecting the underlying hardware + insruction. Unlike most of the vector intrinsics in this chapter, + vec_pmsum_be does not follow the bi-endian + programming model.
@@ -23470,27 +23703,27 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c - + Example Implementation @@ -23504,13 +23737,15 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - const int + const int - const int + const int - sample implementation TBD + + vshasigmaw r,a,b,c + @@ -23527,7 +23762,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vshasigmaw r,a,b,d +