From 81e159f662ba67248171a7bd8fefce5069b027cc Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 20 Jul 2021 13:04:09 -0500 Subject: [PATCH] Comply with latest branding guidelines Also includes a few fixes for comments from Paul Clarke. Signed-off-by: Bill Schmidt --- Intrinsics_Reference/ch_intro.xml | 53 ++++++++++++++++++----- Intrinsics_Reference/ch_mma_reference.xml | 4 +- Intrinsics_Reference/ch_techniques.xml | 4 +- Intrinsics_Reference/ch_vec_reference.xml | 36 +++++++-------- 4 files changed, 64 insertions(+), 33 deletions(-) diff --git a/Intrinsics_Reference/ch_intro.xml b/Intrinsics_Reference/ch_intro.xml index 78f02f8..7f7da4e 100644 --- a/Intrinsics_Reference/ch_intro.xml +++ b/Intrinsics_Reference/ch_intro.xml @@ -23,13 +23,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
A Brief History - The history of vector programming on Power processors begins + The history of vector programming on Power processors begins with the AIM (Apple, IBM, Motorola) alliance in the 1990s. The AIM partners developed the Power Vector Media Extension (VMX) to accelerate multimedia applications, particularly image processing. VMX is the name still used by IBM for this instruction set. Freescale (formerly Motorola) used the - trademark "AltiVec," while Apple at one time called it "Velocity + trademark AltiVec, while Apple at one + time called it "Velocity Engine." While VMX remains the most official name, the term AltiVec is still in common use today. Freescale's AltiVec Technology Programming Interface Manual (the "AltiVec PIM") is @@ -68,11 +72,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro"> also included AltiVec support, and was used in the Apple PowerMac G5. IBM initially omitted support for VMX from its server-class computers, but added support for it in the POWER6 - server family. + processor-based server + family. IBM extended VMX by introducing the Vector-Scalar Extension - (VSX) for the POWER7 family of processors. VSX adds sixty-four + (VSX) for the POWER7 family of + processors. VSX adds sixty-four 128-bit vector-scalar registers (VSRs); however, to optimize the amount of per-process register state, the registers overlap with the VRs and the scalar floating-point registers (FPRs) (see the data types representable by the VRs, and can also be treated as containing two 64-bit integers or two 64-bit double-precision floating-point values. However, ISA support for two 64-bit - integers in VSRs was limited until Version 2.07 (POWER8) of the + integers in VSRs was limited until Version 2.07 (POWER8) of the Power ISA, and only the VRs are supported for these instructions. Both the VMX and VSX instruction sets have been expanded for the - POWER8 and POWER9 processor families. Starting with POWER8, + POWER8, POWER9, and Power10 processor + families. Starting with POWER8, a VSR can now contain a single 128-bit integer; and starting with POWER9, a VSR can contain a single 128-bit IEEE floating-point value. Again, the ISA currently only supports 128-bit @@ -103,7 +115,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro"> The Power architecture has supported operation in either big-endian (BE) or little-endian (LE) mode from the beginning. However, IBM's Power servers were only shipped - with big-endian operating systems (AIX, Linux, i5/OS) prior to + with big-endian operating systems (AIX, IBM i, Linux) prior to the introduction of POWER8. With POWER8, IBM began supporting little-endian Linux distributions for the first time, and introduced a new application binary interface (the @@ -135,7 +150,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
The Unified Vector Register Set - In OpenPOWER-compliant processors, floating-point and vector + In OpenPOWER-compliant + processors, floating-point and vector operations are implemented using a unified vector-scalar model. As shown in and , there are 64 vector-scalar registers; each @@ -202,13 +219,13 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro"> The XL and OpenXL + revisionflag="added">and Open XL compilers. For XL and OpenXL compilers provided + revisionflag="added">and Open XL compilers provided with the Linux Community Edition, you can provide feedback to the XL compiler team via email (compinfo@cn.ibm.com); for other editions of - XL and OpenXL + XL and Open XL compilers, please open a Case. @@ -291,7 +308,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro"> - POWER10 Processor User's Manual. + Power10 Processor User's Manual. Not @@ -358,6 +375,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
+
+ Trademarks + + AIX, POWER7, POWER8, POWER9, and Power10 are trademarks or + registered trademarks of International Business Machines + Corporation. Linux is a registered trademark of Linus + Torvalds. Intel is s registered trademark of Intel Corporation + or its subsidiaries. AltiVec is a trademark of Freescale + Semiconductor, Inc. + +
+
Conformance to this Specification diff --git a/Intrinsics_Reference/ch_mma_reference.xml b/Intrinsics_Reference/ch_mma_reference.xml index 822f606..fdbd04f 100644 --- a/Intrinsics_Reference/ch_mma_reference.xml +++ b/Intrinsics_Reference/ch_mma_reference.xml @@ -109,7 +109,7 @@ - __vector_pair __builtin_vsx_lxvp (long long a, const __vector_pair* b) + __vector_pair __builtin_vsx_lxvp (signed long a, const __vector_pair* b) @@ -121,7 +121,7 @@ - void __builtin_vsx_stxvp (__vector_pair s, long long a, const __vector_pair* b) + void __builtin_vsx_stxvp (__vector_pair s, signed long a, const __vector_pair* b) diff --git a/Intrinsics_Reference/ch_techniques.xml b/Intrinsics_Reference/ch_techniques.xml index b391b4e..b636b3d 100644 --- a/Intrinsics_Reference/ch_techniques.xml +++ b/Intrinsics_Reference/ch_techniques.xml @@ -229,7 +229,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques"> Recent versions of the GCC, Clang, and Open XL compilers for Power provide "drop-in" portability headers for portions - of the Intel Architecture Instruction Set Extensions (see Intel Architecture + Instruction Set Extensions (see ). These headers mirror the APIs of Intel headers having the same names. As of this writing, support is provided for the MMX and SSE layers, up through diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index f5a50cf..3b9c920 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -125,8 +125,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> ISA 3.0 or later. This form is only available starting with PowerISA 3.0, - corresponding to POWER9 servers. The Power Vector Library - (see provides equivalent + corresponding to Power servers built with POWER9 + architecture. The Power Vector Library (see provides equivalent POWER7/POWER8 implementations for many ISA 3.0 vector instructions, which may be preferred for portability. @@ -135,10 +136,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> ISA 3.1 or later. This form is only available starting with PowerISA 3.1, corresponding to - POWER10 servers. The Power Vector Library (see provides equivalent - POWER7/POWER8/POWER9 implementations for many ISA 3.1 vector - instructions, which may be preferred for portability. + Power servers built with Power10 architecture. The Power + Vector Library (see + provides equivalent POWER7/POWER8/POWER9 implementations for + many ISA 3.1 vector instructions, which may be preferred for + portability. @@ -44622,8 +44624,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> Purpose: - Return a non-zero value if and only if the input vector contains - a zero element. + Tests whether the input vector contains a zero element. Result value: r is given a non-zero value if @@ -44637,12 +44638,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> Notes: - Use this built-in in preference to vec_nez when - the test guards a call to vec_stril. This allows - compilers to generate the most efficient code. + Use this built-in in preference to vec_cmpnez + when the test guards a call to vec_stril. This + allows compilers to generate the most efficient code. Review status: - Not yet reviewed. + Reviewed by Paul Clarke. @@ -44987,8 +44988,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> Purpose: - Return a non-zero value if and only if the input vector contains - a zero element. + Tests whether the input vector contains a zero element. Result value: r is given a non-zero value if @@ -45002,12 +45002,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> Notes: - Use this built-in in preference to vec_nez when - the test guards a call to vec_strir. This allows - compilers to generate the most efficient code. + Use this built-in in preference to vec_cmpnez + when the test guards a call to vec_strir. This + allows compilers to generate the most efficient code. Review status: - Not yet reviewed. + Reviewed by Paul Clarke.