diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index 07a58d1..b0c7ca6 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -2023,7 +2023,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> Result value: When the type of a is vector unsigned char or vector unsigned __int128: - + For each i @@ -2063,7 +2063,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> When the type of a is vector unsigned long long: - + For each doubleword element i @@ -2073,7 +2073,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> of a: - + For each j @@ -2326,7 +2326,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> the corresponding element of b and greater than or equal to the negated value of the corresponding element of b. Otherwise: - + If an element of b is greater @@ -8451,7 +8451,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> targets, and right-to-left for little-endian targets. Notes: - + No Power compilers yet support the vector _Float16 type, so that interface is currently deferred. @@ -11708,7 +11708,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> None. Notes: - + The example implementation for vector char assumes that the @@ -13138,15 +13138,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_nor - Vector ... Spelled Out Name TBD + Vector NOR - r = vec_nor (ARG1, ARG2) + r = vec_nor (a, b) Purpose: Performs a bitwise NOR of the given vectors. - Result value: The result is the bitwise NOR of ARG1 and ARG2. + Result value: r is the bitwise NOR + of a and b. Endian considerations: None. @@ -13167,12 +13169,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -13192,7 +13194,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxlnor r,a,b + @@ -13206,7 +13210,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + xxlnor r,a,b + @@ -13220,7 +13226,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxlnor r,a,b + @@ -13234,7 +13242,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxlnor r,a,b + @@ -13248,7 +13258,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + xxlnor r,a,b + @@ -13262,7 +13274,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxlnor r,a,b + @@ -13276,7 +13290,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxlnor r,a,b + @@ -13290,7 +13306,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + xxlnor r,a,b + @@ -13304,7 +13322,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxlnor r,a,b + @@ -13318,7 +13338,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxlnor r,a,b + @@ -13332,7 +13354,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + xxlnor r,a,b + @@ -13346,7 +13370,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxlnor r,a,b + @@ -13360,7 +13386,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xxlnor r,a,b + @@ -13374,7 +13402,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xxlnor r,a,b + @@ -13386,15 +13416,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_or - Vector ... Spelled Out Name TBD + Vector OR - r = vec_or (ARG1, ARG2) + r = vec_or (a, b) Purpose: Performs a bitwise OR of the given vectors. - Result value: The result is the bitwise OR of ARG1 and ARG2. + Result value: r is the bitwise OR + of a and b. Endian considerations: None. @@ -13415,12 +13447,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -13440,7 +13472,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxlor r,a,b + @@ -13454,7 +13488,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + xxlor r,a,b + @@ -13468,7 +13504,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxlor r,a,b + @@ -13482,7 +13520,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxlor r,a,b + @@ -13496,7 +13536,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + xxlor r,a,b + @@ -13510,7 +13552,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxlor r,a,b + @@ -13524,7 +13568,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxlor r,a,b + @@ -13538,7 +13584,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + xxlor r,a,b + @@ -13552,7 +13600,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxlor r,a,b + @@ -13566,7 +13616,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxlor r,a,b + @@ -13580,7 +13632,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + xxlor r,a,b + @@ -13594,7 +13648,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxlor r,a,b + @@ -13608,7 +13664,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xxlor r,a,b + @@ -13622,7 +13680,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xxlor r,a,b + @@ -13634,15 +13694,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_orc - Vector ... Spelled Out Name TBD + Vector OR with Complement - r = vec_orc (ARG1, ARG2) + r = vec_orc (a, b) Purpose: - Performs a bitwise OR of the first vector with the negated second vector. + Performs a bitwise OR of the first vector with the bitwise-complemented + second vector. - Result value: The result is the bitwise OR of ARG1 and the bitwise negation of ARG2. + Result value: r is the bitwise OR + of a and the bitwise complement of + b. Endian considerations: None. @@ -13663,12 +13726,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -13688,7 +13751,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxlorc r,a,b + @@ -13702,7 +13767,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + xxlorc r,a,b + @@ -13716,7 +13783,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxlorc r,a,b + @@ -13730,7 +13799,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxlorc r,a,b + @@ -13744,7 +13815,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + xxlorc r,a,b + @@ -13758,7 +13831,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxlorc r,a,b + @@ -13772,7 +13847,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxlorc r,a,b + @@ -13786,7 +13863,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + xxlorc r,a,b + @@ -13800,7 +13879,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxlorc r,a,b + @@ -13814,7 +13895,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxlorc r,a,b + @@ -13828,7 +13911,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + xxlorc r,a,b + @@ -13842,7 +13927,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxlorc r,a,b + @@ -13856,7 +13943,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xxlorc r,a,b + @@ -13870,7 +13959,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xxlorc r,a,b + @@ -13882,49 +13973,66 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_pack - Vector ... Spelled Out Name TBD + Vector Pack - r = vec_pack (ARG1, ARG2) + r = vec_pack (a, b) Purpose: - Packs information from each element of two vectors into the result vector. + Packs information from each element of two vectors into the result + vector. - Result value: For integer types, the value of each element of the result vector is taken from the low-order half of the corresponding element of the result of concatenating ARG1 and ARG2. -For floating-point types, the value of each element of the - result vector is the corresponding element of the result of - concatenating ARG1 and ARG2, rounded to the result type. + Result value: Let v represent the concatenation of vectors + a and b. For integer types, the value of each element + of r is taken from the low-order half + of the corresponding element of v. For + floating-point types, the value of each element of r is the corresponding element of v, rounded to the result type. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets. + + Notes: + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred. Also, the + pack-double-to-float interface produces incorrect code. Issue 417. + Supported type signatures for vec_pack - + + - + r - + - ARG1 + a - + - ARG2 + b - Example Implementation + Example LE Implementation + + + Example BE Implementation Restrictions @@ -13943,7 +14051,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + vpkuhum r,b,a + + + + + vpkuhum r,a,b + @@ -13960,7 +14075,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + vpkuhum r,b,a + + + + + vpkuhum r,a,b + @@ -13977,7 +14099,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vpkuhum r,b,a + + + + + vpkuhum r,a,b + @@ -13994,7 +14123,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + vpkudum r,b,a + + + + + vpkudum r,a,b + @@ -14011,7 +14147,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + vpkudum r,b,a + + + + + vpkudum r,a,b + @@ -14028,7 +14171,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vpkudum r,b,a + + + + + vpkudum r,a,b + @@ -14045,7 +14195,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + vpkuwum r,b,a + + + + + vpkuwum r,a,b + @@ -14062,7 +14219,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vpkuwum r,b,a + + + + + vpkuwum r,a,b + @@ -14079,7 +14243,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vpkuwum r,b,a + + + + + vpkuwum r,a,b + @@ -14095,11 +14266,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - + sample implementation TBD - - + + sample implementation TBD + + + Broken @@ -14112,11 +14286,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - + sample implementation TBD - ISA 3.0 or later + sample implementation TBD + + + Deferred @@ -14128,48 +14305,60 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_pack_to_short_fp32 - Vector ... Spelled Out Name TBD + Vector Pack 32-bit Float to Short - r = vec_pack_to_short_fp32 (ARG1, ARG2) + r = vec_pack_to_short_fp32 (a, b) Purpose: - Packs eight single-precision 32-bit floating-point numbers into a vector of eight 16-bit floating-point numbers. - - Result value: The value is a vector consisting of eight 16-bit elements, each representing a 16-bit floating-point number that was created by converting the corresponding single-precision value to half-precision. + Packs eight single-precision 32-bit floating-point numbers from two + source vectors into a vector of eight 16-bit floating-point numbers. + + Result value: Let v represent the 16-element concatenation of + a and b. Each value of r contains the result of converting the + corresponding single-precision element of v to half-precision. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets.
Supported type signatures for vec_pack_to_short_fp32 - + + - + r - + - ARG1 + a - + - ARG2 + b - - Example Implementation + + Example LE Implementation - + + Example BE Implementation + + Restrictions @@ -14186,7 +14375,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + vctuxs t,a,0 + vctuxs u,b,0 + vpkswss r,u,t + + + + + vctuxs t,a,0 + vctuxs u,b,0 + vpkswss r,t,u + ISA 3.0 or later @@ -14201,56 +14401,67 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_packpx - Vector ... Spelled Out Name TBD + Vector Pack Pixel - r = vec_packpx (ARG1, ARG2) + r = vec_packpx (a, b) Purpose: - Packs information from each element of two vectors into the result vector. + Packs information from each element of two vectors into the result + vector. - Result value: The value of each element of the result vector is taken from the corresponding element of the result of concatenating ARG1 and ARG2 as follows: - - - The least-significant bit of the high-order byte is - stored into the first bit of the result element. - - - The least-significant 5 bits of each of the remaining - bytes are stored into the remaining portion of the result - element. - - + Result value: Let v be the concatenation of a and b. The + value of each element of r is taken + from the corresponding element of v as + follows: + + + The least-significant bit of the high-order byte is + stored into the first bit of the result element. + + + The least-significant 5 bits of each of the remaining + bytes are stored into the remaining portion of the result + element. + + Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets.
Supported type signatures for vec_packpx - + + - + r - + - ARG1 + a - + - ARG2 + b - - Example Implementation + + Example LE Implementation + + + Example BE Implementation @@ -14266,7 +14477,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vpkpx r,b,a + + + + + vpkpx r,a,b + @@ -14277,46 +14495,57 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - vec_packs - Vector ... Spelled Out Name TBD + vec_packs + Vector Pack Saturated - r = vec_packs (ARG1, ARG2) + r = vec_packs (a, b) Purpose: - Packs information from each element of two vectors into the result vector, using saturated values. - - Result value: The value of each element of the result vector is the saturated value of the corresponding element of the result of concatenating ARG1 and ARG2. + Packs information from each element of two vectors into the result + vector, using saturated values. + + Result value: Let v be the concatenation of a and b. The + value of each element of r is the + saturated value of the corresponding element of v. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets.
Supported type signatures for vec_packs - + + - + r - + - ARG1 + a - + - ARG2 + b - - Example Implementation + + Example LE Implementation + + + Example BE Implementation @@ -14332,7 +14561,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + vpkshss r,b,a + + + + + vpkshss r,a,b + @@ -14346,7 +14582,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vpkuhus r,b,a + + + + + vpkuhus r,a,b + @@ -14360,7 +14603,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + vpksdss r,b,a + + + + + vpksdss r,a,b + @@ -14374,7 +14624,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vpkudus r,b,a + + + + + vpkudus r,a,b + @@ -14388,7 +14645,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vpkswss r,b,a + + + + + vpkswss r,a,b + @@ -14402,11 +14666,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vpkuwus r,b,a + + + + + vpkuwus r,a,b + - +
@@ -14414,45 +14685,56 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_packsu - Vector ... Spelled Out Name TBD + Vector Pack Saturated Unsigned - r = vec_packsu (ARG1, ARG2) + r = vec_packsu (a, b) Purpose: - Packs information from each element of two vectors into the result vector, using unsigned saturated values. - - Result value: The value of each element of the result vector is the saturated value of the corresponding element of the result of concatenating ARG1 and ARG2. + Packs information from each element of two vectors into the result + vector, using unsigned saturated values. + + Result value: Let v be the concatenation of a and b. The + value of each element of r is the + saturated value of the corresponding element of v. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets. Supported type signatures for vec_packsu - + + - + r - + - ARG1 + a - + - ARG2 + b - Example Implementation + Example LE Implementation + + + Example BE Implementation @@ -14468,7 +14750,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + vpkshus r,b,a + + + + + vpkshus r,a,b + @@ -14482,7 +14771,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vpkuhus r,b,a + + + + + vpkuhus r,a,b + @@ -14496,7 +14792,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + vpksdus r,b,a + + + + + vpksdus r,a,b + @@ -14510,7 +14813,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vpkudus r,b,a + + + + + vpkudus r,a,b + @@ -14524,7 +14834,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vpkswus r,b,a + + + + + vpkswus r,a,b + @@ -14538,7 +14855,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vpkuwus r,b,a + + + + + vpkuwus r,a,b + @@ -14550,15 +14874,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_parity_lsbb - Vector ... Spelled Out Name TBD + Vector Parity over Least-Significant Bits of Bytes - r = vec_parity_lsbb (ARG1) + r = vec_parity_lsbb (a) Purpose: Compute parity on the least-significant bit of each byte. - Result value: Returns a vector with each element containing the parity of the low-order bit of each of the bytes in that element. + Result value: Each element of + r contains the parity computed over the + low-order bit of each of the bytes in the corresponding element of + a. Endian considerations: None. @@ -14579,7 +14906,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -14599,7 +14926,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vprtybw r,a + ISA 3.0 or later @@ -14613,7 +14942,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vprtybw r,a + ISA 3.0 or later @@ -14627,7 +14958,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed __int128 - sample implementation TBD + + vprtybq r,a + ISA 3.0 or later @@ -14641,7 +14974,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned __int128 - sample implementation TBD + + vprtybq r,a + ISA 3.0 or later @@ -14655,7 +14990,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + vprtybd r,a + ISA 3.0 or later @@ -14669,7 +15006,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vprtybd r,a + ISA 3.0 or later @@ -14684,54 +15023,84 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_perm - Vector ... Spelled Out Name TBD + Vector Permute - r = vec_perm (ARG1, ARG2, ARG3) + r = vec_perm (a, b, c) Purpose: - Returns a vector that contains some elements of two vectors, in the order specified by a third vector. - - Result value: Each byte of the result is selected by using the least-significant 5 bits of the corresponding byte of ARG3 as an index into the concatenated bytes of ARG1 and ARG2. + Returns a vector that contains elements selected from two input + vectors, in the order specified by a third input vector. + + Result value: Let v be the concatenation of a and b. Each + byte of r selected by using the + least-significant 5 bits of the corresponding byte of c as an index into v. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets. + Notes: + + + + The example little-endian code generation uses the vpermr instruction from ISA 3.0. For + earlier targets, the compiler must generate an extra instruction + to adjust the permute control vector c. + + + + + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred. + + +
Supported type signatures for vec_perm - + - + + - + r - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c - Example Implementation + Example LE Implementation + Example BE Implementation + + Restrictions @@ -14751,7 +15120,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14771,7 +15147,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14791,7 +15174,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14811,7 +15201,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14831,7 +15228,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14851,7 +15255,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14871,7 +15282,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14891,7 +15309,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14911,7 +15336,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14931,7 +15363,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14951,7 +15390,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14971,7 +15417,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -14991,7 +15444,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -15011,7 +15471,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -15031,7 +15498,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + @@ -15051,10 +15525,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpermr r,b,a,c + + + + + vperm r,a,b,c + - ISA 3.0 or later + Deferred @@ -15066,53 +15547,65 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_permxor - Vector ... Spelled Out Name TBD + Vector Permute and Exclusive-OR - r = vec_permxor (ARG1, ARG2, ARG3) + r = vec_permxor (a, b, c) Purpose: - Applies a permute and exclusive-OR operation on two vectors of byte elements. - - Result value: For each i (0 ≤ i < 16), let index1 be bits 0–3 and index2 be bits 4–7 of byte element i of mask ARG3. -Byte element i of the result is set to the exclusive-OR of - byte elements index1 of ARG1 and index2 of ARG2. + Applies a permute and exclusive-OR operation on two input vectors of byte + elements, with the selected elements identified by a third input vector. + + Result value: For each + i (0 ≤ i < 16), let + index1 be bits 0–3 and + index2 be bits 4–7 of byte element + i of c. Byte + element i of r + is set to the exclusive-OR of byte elements index1 + of a and index2 + of b. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets.
Supported type signatures for vec_permxor - + + - + r - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c - - Example Implementation + + Example LE Implementation + + + Example BE Implementation @@ -15131,7 +15624,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxlnor t,c,c + vpermxor r,a,b,t + + + + + vpermxor r,a,b,c + + @@ -15148,7 +15650,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + xxlnor t,c,c + vpermxor r,a,b,t + + + + + vpermxor r,a,b,c + + @@ -15165,7 +15676,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxlnor t,c,c + vpermxor r,a,b,t + + + + + vpermxor r,a,b,c + + @@ -15177,15 +15697,19 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_popcnt - Vector ... Spelled Out Name TBD + Vector Population Count - r = vec_popcnt (ARG1) + r = vec_popcnt (a) Purpose: - Returns a vector containing the number of bits set in each element of the input vector. + Returns a vector containing the number of bits set in each element of + the input vector. - Result value: The value of each element of the result is the number of bits set in the corresponding input element. + Result value: The value of each + element of r is the number of bits set + in the corresponding element of a. Endian considerations: None. @@ -15205,7 +15729,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -15222,7 +15746,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vpopcntb r,a + @@ -15233,7 +15759,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vpopcntb r,a + @@ -15244,7 +15772,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vpopcntw r,a + @@ -15255,7 +15785,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vpopcntw r,a + @@ -15266,7 +15798,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + vpopcntd r,a + @@ -15277,7 +15811,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vpopcntd r,a + @@ -15288,7 +15824,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + vpopcnth r,a + @@ -15299,7 +15837,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vpopcnth r,a + @@ -15311,15 +15851,19 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_re - Vector ... Spelled Out Name TBD + Vector Reciprocal Estimate - r = vec_re (ARG1) + r = vec_re (a) Purpose: - Returns a vector containing estimates of the reciprocals of the corresponding elements of the given vector. + Returns a vector containing estimates of the reciprocals of the + corresponding elements of the input vector. - Result value: Each element of the result contains the estimated value of the reciprocal of the corresponding element of ARG1. + Result value: Each element of + r contains the estimated value of the + reciprocal of the corresponding element of a. Endian considerations: None. @@ -15339,7 +15883,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -15350,24 +15894,28 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - vector float + vector double - vector float + vector double - sample implementation TBD + + xvredp r,a + - vector double + vector float - vector double + vector float - sample implementation TBD + + xvresp r,a + @@ -15379,18 +15927,35 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_recipdiv - Vector ... Spelled Out Name TBD + Vector Reciprocal Divide - r = vec_recipdiv (ARG1, ARG2) + r = vec_recipdiv (a, b) Purpose: - Returns a vector containing approximations of the division of the corresponding elements of ARG1 by the corresponding elements of ARG2. This implementation provides an implementation-dependent precision, which is commonly within 2 ulps for most of the numeric range expressible by the input operands. This built-in function does not correspond to a single IEEE operation and does not provide the overflow, underflow, and NaN propagation characteristics specified for IEEE division. (Precision may be a function of both the specified target processor model during compilation and the actual processor on which a program is executed.) + Returns a vector containing refined approximations of the division of + the corresponding elements of a by the + corresponding elements of b. This + built-in function provides an implementation-dependent precision, which + is commonly within 2 ulps (units in the last place) for most of the + numeric range expressible by + the input operands. This built-in function does not correspond to a + single IEEE operation and does not provide the overflow, underflow, and + NaN propagation characteristics specified for IEEE division. (Precision + may be a function of both the specified target processor model during + compilation and the actual processor on which a program is executed.) - Result value: Each element of the result vector contains a refined approximation of the division of the corresponding element of ARG1 by the corresponding element of ARG2. + Result value: Each element of + r contains a refined approximation of + the division of the corresponding element of a by the corresponding element of b. Endian considerations: None. + Notes: The example implementation + for vector double assumes that a register z + initially contains the double-precision floating-point value 1.0.
Supported type signatures for vec_recipdiv @@ -15408,12 +15973,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -15433,7 +15998,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xvredp t,b + xvnmsubadp z,b,t + xvmaddadp u,z,t + xvmuldp v,a,u + xvnmsubadp r/a,b,v + xvmaddmdp r/a,u,v + @@ -15447,7 +16019,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xvresp t,b + xvmulsp u,a,t + xvnmsubasp r/a,b,u + xvmaddmsp r/a,t,u + @@ -15459,18 +16036,36 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_revb - Vector ... Spelled Out Name TBD + Vector Reverse Bytes - r = vec_revb (ARG1) + r = vec_revb (a) Purpose: Reverse the bytes of each vector element of a vector. - Result value: Returns a vector where each vector element contains the corresponding byte-reversed vector element of the input vector. + Result value: Each element of + r contains the byte-reversed value of + the corresponding element of a. Endian considerations: None. + Notes: + + + + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred. + + + + + The examples shown are for ISA 3.0. More complex sequences are + required for earlier ISA levels. + + + +
Supported type signatures for vec_revb @@ -15481,20 +16076,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - - Example Implementation + + Example ISA 3.0 Implementation - + Restrictions @@ -15508,7 +16103,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + [none] + @@ -15522,7 +16119,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + [none] + @@ -15536,7 +16135,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + [none] + @@ -15550,7 +16151,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxbrw r,a + @@ -15564,7 +16167,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + xxbrw r,a + @@ -15578,7 +16183,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxbrw r,a + @@ -15592,7 +16199,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed __int128 - sample implementation TBD + + xxbrq r,a + @@ -15606,7 +16215,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned __int128 - sample implementation TBD + + xxbrq r,a + @@ -15620,7 +16231,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxbrd r,a + @@ -15634,7 +16247,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + xxbrd r,a + @@ -15648,7 +16263,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxbrd r,a + @@ -15662,7 +16279,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxbrh r,a + @@ -15676,7 +16295,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + xxbrh r,a + @@ -15690,7 +16311,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxbrh r,a + @@ -15704,7 +16327,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xxbrd r,a + @@ -15718,7 +16343,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xxbrw r,a + @@ -15732,10 +16359,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector _Float16 - sample implementation TBD + + xxbrh r,a + - ISA 3.0 or later + Deferred @@ -15747,18 +16376,40 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_reve - Vector ... Spelled Out Name TBD + Vector Reverse Elements - r = vec_reve (ARG1) + r = vec_reve (a) Purpose: Reverse the elements of a vector. - Result value: Returns a vector with the elements of the input vector in reversed order. + Result value: Returns a vector + with the elements of the input vector in reversed order. Endian considerations: - None. + The vpermr instruction is most naturally used to implement this built-in + function for a little-endian target, and the vperm instruction for a + big-endian target. This is not technically necessary, however, provided + the correct permute control vector is used. Note that use of vpermr + requires ISA 3.0. + Notes: + + + + The example implementations assume that the permute control + vector for the vperm or vpermr instruction is in a register + identified by pcv. The value of pcv differs based on the + element size. + + + + + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred. + + +
Supported type signatures for vec_reve @@ -15776,7 +16427,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -15796,7 +16447,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15810,7 +16463,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15824,7 +16479,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15838,7 +16495,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15852,7 +16511,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15866,7 +16527,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15880,7 +16543,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15894,7 +16559,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15908,7 +16575,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15922,7 +16591,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15936,7 +16607,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15950,7 +16623,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15964,7 +16639,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15978,7 +16655,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + vperm[r] r,a,a,pcv + @@ -15992,10 +16671,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector _Float16 - sample implementation TBD + + vperm[r] r,a,a,pcv + - ISA 3.0 or later + Deferred @@ -17397,7 +18078,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> Converts a vector of floating-point numbers to vector of signed integers. Result value: Target elements are obtained by truncating the source elements to the signed integers as follows: - + Target elements 0 and 1 from source 0 @@ -21831,7 +22512,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> If ARG1 is a pixel vector, the value of each element of the result is taken from the corresponding element of the most-significant half of ARG1 as follows: - + All bits in the first byte of the element of the result are set to the value of the first bit of the element of @@ -22036,7 +22717,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> If ARG1 is a pixel vector, the value of each element of the result is taken from the corresponding element of the least-significant half of ARG1 as follows: - + All bits in the first byte of the element of the result are set to the value of the first bit of the element of @@ -22302,7 +22983,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> Converts a vector of double-precision numbers to a vector of unsigned integers. Result value: Target elements are obtained by truncating the source elements to the unsigned integers as follows: - + Target elements 0 and 1 from source 0