From 85fe0254141f2aab5aa901df956ad9f144d8f127 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 19 Jun 2018 20:17:07 -0500 Subject: [PATCH] Updates through vec_sqrt. Signed-off-by: Bill Schmidt --- Intrinsics_Reference/ch_vec_reference.xml | 533 ++++++++++++++++------ 1 file changed, 405 insertions(+), 128 deletions(-) diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index 69a0888..368e8ab 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -19469,7 +19469,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_slo - Vector ... Spelled Out Name TBD + Vector Shift Left by Octets r = vec_slo (ARG1, ARG2) @@ -19477,9 +19477,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> Purpose: Left shifts a vector by a given number of bytes (octets). - Result value: The result is the contents of ARG1, shifted left by the number of bytes specified by the most-significant nibble of the least-significant byte + Result value: Vector r receives the contents of a, shifted left by the number of bytes specified + by bits 1:4 of the least-significant byte of b. Endian considerations: - None. + This intrinsic is not endian-neutral, so uses of + vec_sll in big-endian code must be rewritten for little-endian targets. + The shift count is in element 15 of b + for big-endian, but in element 0 of b + for little-endian. @@ -19498,12 +19506,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -19523,7 +19531,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19537,7 +19547,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19551,7 +19563,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19565,7 +19579,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19579,7 +19595,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19593,7 +19611,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19607,7 +19627,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19621,7 +19643,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19635,7 +19659,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19649,7 +19675,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19663,7 +19691,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19677,7 +19707,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19691,7 +19723,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19705,7 +19739,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19719,7 +19755,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19733,7 +19771,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19747,7 +19787,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19761,7 +19803,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19775,7 +19819,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vslo r,a,b + @@ -19789,7 +19835,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslo r,a,b + @@ -19801,17 +19849,29 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_slv - Vector ... Spelled Out Name TBD + Vector Shift Left Variable - r = vec_slv (ARG1, ARG2) + r = vec_slv (a, b) Purpose: Left-shifts a vector by a varying number of bits by element. - Result value: For each integer 0 + Result value: Let v be a 17-byte vector formed from a in bytes [0:15] and a zero byte in element 16. + Then each byte element i of r is determined as follows. The start bit + sb is obtained from bits 5:7 of byte element + i of a. Then + the contents of bits sb:sb+7 + of the halfword in byte elements + i:i+1 of v are placed into byte element + i of r. Endian considerations: - None. + All bit and byte element numbers are specified in big-endian order. + This intrinsic is not endian-neutral.
@@ -19824,25 +19884,25 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b Example Implementation - + Restrictions @@ -19859,7 +19919,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vslv r,a,b + ISA 3.0 or later @@ -19874,48 +19936,63 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splat - Vector ... Spelled Out Name TBD + Vector Splat - r = vec_splat (ARG1, ARG2) + r = vec_splat (a, b) Purpose: Returns a vector that has all of its elements set to a given value. - Result value: The value of each element of the result is the value of the element of ARG1 specified by ARG2, which should be an element number less than the number of elements supported for the respective ARG1 type. + Result value: The value of each + element of r is the value of the + element of a specified by b, which must be an element number less than the + number of elements supported for a's + type. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets. - + Notes: + No Power compilers yet support the vector _Float16 type, so those + interfaces are currently deferred. +
Supported type signatures for vec_splat - + - - + + + - + r - + - ARG1 + a - + - ARG2 + b - Example Implementation + Example LE + Implementation + Example BE + Implementation + + Restrictions @@ -19932,7 +20009,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vspltb r,a,15-b + + + + + vspltb r,a,b + @@ -19949,7 +20033,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vspltb r,a,15-b + + + + + vspltb r,a,b + @@ -19966,7 +20057,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vspltb r,a,15-b + + + + + vspltb r,a,b + @@ -19983,7 +20081,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxspltw r,a,3-b + + + + + xxspltw r,a,b + @@ -20000,7 +20105,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxspltw r,a,3-b + + + + + xxspltw r,a,b + @@ -20017,7 +20129,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxspltw r,a,3-b + + + + + xxspltw r,a,b + @@ -20034,7 +20153,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxpermdi r,a,a,(1-b)*3 + + + + + xxpermdi r,a,a,b + @@ -20051,7 +20177,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxpermdi r,a,a,(1-b)*3 + + + + + xxpermdi r,a,a,b + @@ -20068,7 +20201,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxpermdi r,a,a,(1-b)*3 + + + + + xxpermdi r,a,a,b + @@ -20085,7 +20225,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vsplth r,a,7-b + + + + + vsplth r,a,b + @@ -20102,7 +20249,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vsplth r,a,7-b + + + + + vsplth r,a,b + @@ -20119,7 +20273,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vsplth r,a,7-b + + + + + vsplth r,a,b + @@ -20136,7 +20297,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vsplth r,a,7-b + + + + + vsplth r,a,b + @@ -20153,7 +20321,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxpermdi r,a,a,(1-b)*3 + + + + + xxpermdi r,a,a,b + @@ -20170,7 +20345,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + xxspltw r,a,3-b + + + + + xxspltw r,a,b + @@ -20187,10 +20369,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> const int - sample implementation TBD + + vsplth r,a,7-b + + + + + vsplth r,a,b + - ISA 3.0 or later + Deferred @@ -20202,15 +20391,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splat_s8 - Vector ... Spelled Out Name TBD + Vector Splat to Signed Byte - r = vec_splat_s8 (ARG1) + r = vec_splat_s8 (a) Purpose: Returns a vector with all elements equal to the given value. - Result value: The bit pattern of ARG1 is interpreted as a signed value. Each element of the result is given this value. + Result value: + Each element of r is given the + sign-extended 5-bit value of a. + The range of this value is [-16:15]. Endian considerations: None. @@ -20230,7 +20422,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20244,10 +20436,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - const int + 5-bit signed literal - sample implementation TBD + + vspltisb r,a + @@ -20259,15 +20453,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splat_s16 - Vector ... Spelled Out Name TBD + Vector Splat to Signed Halfword - r = vec_splat_s16 (ARG1) + r = vec_splat_s16 (a) Purpose: Returns a vector with all elements equal to the given value. - Result value: Each element of the result has the value of ARG1. + Result value: + Each element of r is given the + sign-extended 5-bit value of a. + The range of this value is [-16:15]. Endian considerations: None. @@ -20287,7 +20484,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20301,10 +20498,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - const int + 5-bit signed literal - sample implementation TBD + + vspltish r,a + @@ -20316,15 +20515,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splat_s32 - Vector ... Spelled Out Name TBD + Vector Splat to Signed Word - r = vec_splat_s32 (ARG1) + r = vec_splat_s32 (a) Purpose: Returns a vector with all elements equal to the given value. - Result value: Each element of the result has the value of ARG1. + Result value: + Each element of r is given the + sign-extended 5-bit value of a. + The range of this value is [-16:15]. Endian considerations: None. @@ -20344,7 +20546,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20358,10 +20560,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - const int + 5-bit signed literal - sample implementation TBD + + vspltisw r,a + @@ -20373,15 +20577,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splat_u8 - Vector ... Spelled Out Name TBD + Vector Splat to Unsigned Byte - r = vec_splat_u8 (ARG1) + r = vec_splat_u8 (a) Purpose: Returns a vector with all elements equal to the given value. - Result value: The bit pattern of ARG1 is interpreted as an unsigned value. Each element of the result is given this value. + Result value: + The 5-bit signed value of a is + sign-extended to a byte and the resulting value is cast to an + unsigned char. This value is placed in each element of + r. The range of the original value is + [-16:15]. Endian considerations: None. @@ -20401,7 +20610,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20415,10 +20624,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - const int + 5-bit signed literal - sample implementation TBD + + vspltisb r,a + @@ -20430,15 +20641,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splat_u16 - Vector ... Spelled Out Name TBD + Vector Splat to Unsigned Halfword - r = vec_splat_u16 (ARG1) + r = vec_splat_u16 (a) Purpose: Returns a vector with all elements equal to the given value. - Result value: The bit pattern of ARG1 is interpreted as an unsigned value. Each element of the result is given this value. + Result value: + The 5-bit signed value of a is + sign-extended to a halfword and the resulting value is cast to an + unsigned short. This value is placed in each element of + r. The range of the original value is + [-16:15]. Endian considerations: None. @@ -20458,7 +20674,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20472,10 +20688,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - const int + 5-bit signed literal - sample implementation TBD + + vspltish r,a + @@ -20487,15 +20705,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splat_u32 - Vector ... Spelled Out Name TBD + Vector Splat to Unsigned Word - r = vec_splat_u32 (ARG1) + r = vec_splat_u32 (a) Purpose: Returns a vector with all elements equal to the given value. - Result value: The bit pattern of ARG1 is interpreted as an unsigned value. Each element of the result is given this value. + Result value: + The 5-bit signed value of a is + sign-extended to a word and the resulting value is cast to an + unsigned int. This value is placed in each element of + r. The range of the original value is + [-16:15]. Endian considerations: None. @@ -20515,7 +20738,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20529,10 +20752,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - const int + 5-bit signed literal - sample implementation TBD + + vspltisw r,a + @@ -20544,18 +20769,24 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_splats - Vector ... Spelled Out Name TBD + Vector Splat Scalar - r = vec_splats (ARG1) + r = vec_splats (a) Purpose: - Returns a vector with the value of each element set to ARG1. + Returns a vector with the value of each element set to the value of + the scalar input parameter. - Result value: Each element of the result is set to the value of the scalar input parameter. + Result value: Each element of + r is set to the value of a. Endian considerations: None. + Notes: + No Power compilers yet support the vector _Float16 type, so that + interface is currently deferred.
Supported type signatures for vec_splats @@ -20573,7 +20804,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20593,7 +20824,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed char - sample implementation TBD + + rlwinm t,a,0,0xff + mtvsrd u,t + vspltb r,u,7 + @@ -20607,7 +20842,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned char - sample implementation TBD + + rlwinm t,a,0,0xff + mtvsrd u,t + vspltb r,u,7 + @@ -20621,7 +20860,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed int - sample implementation TBD + + mtvsrd t,a + vspltb r,t,7 + @@ -20635,7 +20877,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned int - sample implementation TBD + + mtvsrd t,a + vspltb r,t,7 + @@ -20649,7 +20894,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed __int128 - sample implementation TBD + + mtvsrwz t,a + xxspltw r,t,1 + @@ -20663,7 +20911,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned __int128 - sample implementation TBD + + mtvsrwz t,a + xxspltw r,t,1 + @@ -20677,7 +20928,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed long long - sample implementation TBD + + mtvsrd t,a + xxpermdi r,t,t,0 + @@ -20691,7 +20945,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned long long - sample implementation TBD + + mtvsrd t,a + xxpermdi r,t,t,0 + @@ -20705,7 +20962,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> signed short - sample implementation TBD + + rlwinm t,a,0,0xffff + mtvsrd u,t + vsplth r,u,3 + @@ -20719,7 +20980,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> unsigned short - sample implementation TBD + + rlwinm t,a,0,0xffff + mtvsrd u,t + vsplth r,u,3 + @@ -20733,7 +20998,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> double - sample implementation TBD + + xxpermdi r,a,a,0 + @@ -20747,7 +21014,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> float - sample implementation TBD + + xxscvdpspn t,a + xxspltw r,t,0 + @@ -20764,7 +21034,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> sample implementation TBD - ISA 3.0 or later + Deferred @@ -20776,15 +21046,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sqrt - Vector ... Spelled Out Name TBD + Vector Square Root - r = vec_sqrt (ARG1) + r = vec_sqrt (a) Purpose: - Returns a vector containing the square root of each element in the given vector. + Returns a vector containing the square root of each element in the + source vector. - Result value: Each element of the result vector is the square root of the corresponding element of ARG1. + Result value: Each element of + r is the square root of the + corresponding element of a. Endian considerations: None. @@ -20804,7 +21077,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -20821,7 +21094,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xvsqrtdp r,a + @@ -20832,7 +21107,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xvsqrtsp r,a +