diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml
index ad8d9bb..b0d7ec7 100644
--- a/Intrinsics_Reference/ch_vec_reference.xml
+++ b/Intrinsics_Reference/ch_vec_reference.xml
@@ -10593,6 +10593,282 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_clr_first
+ Vector Clear First
+
+ r = vec_clr_first (a, b)
+
+
+ Purpose:
+ Clear the first N elements of a vector to zero.
+
+ Result value:
+ Let N be the value of b.
+ The first N elements of r are
+ set to zero. The remaining elements of r are copied from the corresponding
+ elements of a.
+
+
+ b must have a value between 1
+ and the number of elements of a, inclusive.
+
+ Endian considerations:
+ The element numbering within a register is left-to-right for
+ big-endian targets, and right-to-left for little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vclrlb
+ vec_clr_first
+
+
+ vclrrb
+ vec_clr_first
+
+
+
+ Supported type signatures for vec_clr_first
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ const int
+
+
+
+ vclrrb r,a,16-b
+
+
+
+
+ vclrlb r,a,16-b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ vclrrb r,a,16-b
+
+
+
+
+ vclrlb r,a,16-b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_clr_last
+ Vector Clear Last
+
+ r = vec_clr_last (a, b)
+
+
+ Purpose:
+ Clear the last N elements of a vector to zero.
+
+ Result value:
+ Let N be the value of b.
+ The last N elements of r are
+ set to zero. The remaining elements of r are copied from the corresponding
+ elements of a.
+
+
+ b must have a value between 1
+ and the number of elements of a, inclusive.
+
+ Endian considerations:
+ The element numbering within a register is left-to-right for
+ big-endian targets, and right-to-left for little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vclrlb
+ vec_clr_last
+
+
+ vclrrb
+ vec_clr_last
+
+
+
+ Supported type signatures for vec_clr_last
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ const int
+
+
+
+ vclrlb r,a,16-b
+
+
+
+
+ vclrrb r,a,16-b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ vclrlb r,a,16-b
+
+
+
+
+ vclrrb r,a,16-b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_cmpb
Vector Compare Bytes
@@ -14132,6 +14408,180 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+
+ vec_cntm
+ Vector Count Mask
+
+ r = vec_cntm (a, b)
+
+
+ Purpose:
+ Count the number of elements with their high-order bit equal to
+ a specific value.
+
+ Result value:
+ Let N be 7 when a is a vector
+ unsigned char, 6 when a is a
+ vector unsigned short, 5 when a
+ is a vector unsigned int, and 4 when a is a vector unsigned long long. Then
+ bits 0:N of r are set to the
+ number of elements in a whose
+ high-order bit is equal to b,
+ which must be either 0 or 1. Bits N+1:53 of r are set to 0.
+
+ Endian considerations:
+ None.
+
+ Notes:
+ The somewhat odd definition of the result value is intended to
+ allow r to be consumed
+ efficiently by the VSX Load Vector with Length
+ (lxvl) instruction.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vcntmbb
+ vec_cntm
+
+
+ vcntmbh
+ vec_cntm
+
+
+ vcntmbw
+ vec_cntm
+
+
+ vcntmbd
+ vec_cntm
+
+
+
+ Supported type signatures for vec_cntm
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ unsigned long long
+
+
+ vector unsigned char
+
+
+ const unsigned char
+
+
+
+ vcntmbb r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ unsigned long long
+
+
+ vector unsigned short
+
+
+ const unsigned char
+
+
+
+ vcntmbh r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ unsigned long long
+
+
+ vector unsigned int
+
+
+ const unsigned char
+
+
+
+ vcntmbw r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ unsigned long long
+
+
+ vector unsigned long long
+
+
+ const unsigned char
+
+
+
+ vcntmbd r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
vec_cnttz
@@ -17283,6 +17733,170 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_expandm
+ Vector Expand Mask
+
+ r = vec_expandm (a)
+
+
+ Purpose:
+ Create an element mask based on high-order bits in the input
+ elements.
+
+ Result value:
+ Each element of r is set to all
+ zeros if the high-order bit of the corresponding element of
+ a is equal to 0; otherwise it
+ is set to all ones.
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vexpandbm
+ vec_expandm
+
+
+ vexpandhm
+ vec_expandm
+
+
+ vexpandwm
+ vec_expandm
+
+
+ vexpanddm
+ vec_expandm
+
+
+ vexpandqm
+ vec_expandm
+
+
+
+ Supported type signatures for vec_expandm
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+
+ vexpandbm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+
+ vexpandhm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+
+ vexpandwm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+
+ vexpanddm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+
+ vexpandqm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_expte
Vector Exponential Estimate
@@ -18505,6 +19119,170 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_extractm
+ Vector Extract Mask
+
+ r = vec_extractm (a)
+
+
+ Purpose:
+ Collect the high-order bits of each element of the input
+ vector.
+
+ Result value:
+ The contents of the high-order bit of each element of a are concatenated and placed in the
+ rightmost bits of r, with other
+ bits of r set to 0.
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vextractbm
+ vec_extractm
+
+
+ vextracthm
+ vec_extractm
+
+
+ vextractwm
+ vec_extractm
+
+
+ vextractdm
+ vec_extractm
+
+
+ vextractqm
+ vec_extractm
+
+
+
+ Supported type signatures for vec_extractm
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ unsigned int
+
+
+ vector unsigned char
+
+
+
+ vextractbm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned short
+
+
+
+ vextracthm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+
+ vextractwm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned long long
+
+
+
+ vextractdm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned __int128
+
+
+
+ vextractqm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_extract4b
Vector Extract Four Bytes
@@ -21305,6 +22083,672 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_genbm
+ Vector Generate Byte Mask
+
+ r = vec_genbm (a)
+
+
+ Purpose:
+ Create an element mask for byte elements from a bit mask.
+
+ Result value:
+ For each integer i from 0 to 15, do the
+ following. Counting the leftmost element of r as the 0th element, and the rightmost
+ element as the 15th element, all bits of the
+ ith element of r are set to 0 if the
+ ith bit of the 16-bit value in a is equal to 0. All bits of the
+ ith element of r are set to 1 if the
+ ith bit of the 16-bit value in a is equal to 1. The bits in a are likewise numbered from left to
+ right.
+
+ Endian considerations:
+ Because elements are numbered from left to right in the result
+ vector regardless of endianness, the semantics of this built-in
+ function differ on big-endian and little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ mtvsrbm
+ vec_genbm
+
+
+
+ Supported type signatures for vec_genbm
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ unsigned long long
+
+
+
+ mtvsrbm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_gendm
+ Vector Generate Doubleword Mask
+
+ r = vec_gendm (a)
+
+
+ Purpose:
+ Create an element mask for doubleword elements from a bit mask.
+
+ Result value:
+ For each integer i from 0 to 1, do the
+ following. Counting the leftmost element of r as the 0th element, and the rightmost
+ element as the 1st element, all bits of the
+ ith element of r are set to 0 if the
+ ith bit of the 2-bit value in a is equal to 0. All bits of the
+ ith element of r are set to 1 if the
+ ith bit of the 2-bit value in a is equal to 1. The bits in a are likewise numbered from left to
+ right.
+
+ Endian considerations:
+ Because elements are numbered from left to right in the result
+ vector regardless of endianness, the semantics of this built-in
+ function differ on big-endian and little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ mtvsrdm
+ vec_gendm
+
+
+
+ Supported type signatures for vec_gendm
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ unsigned long long
+
+
+
+ mtvsrdm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_genhm
+ Vector Generate Halfword Mask
+
+ r = vec_genhm (a)
+
+
+ Purpose:
+ Create an element mask for halfword elements from a bit mask.
+
+ Result value:
+ For each integer i from 0 to 7, do the
+ following. Counting the leftmost element of r as the 0th element, and the rightmost
+ element as the 7th element, all bits of the
+ ith element of r are set to 0 if the
+ ith bit of the 8-bit value in a is equal to 0. All bits of the
+ ith element of r are set to 1 if the
+ ith bit of the 8-bit value in a is equal to 1. The bits in a are likewise numbered from left to
+ right.
+
+ Endian considerations:
+ Because elements are numbered from left to right in the result
+ vector regardless of endianness, the semantics of this built-in
+ function differ on big-endian and little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ mtvsrhm
+ vec_genhm
+
+
+
+ Supported type signatures for vec_genhm
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ unsigned long long
+
+
+
+ mtvsrhm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_genpcvm
+ Vector Generate Permute Control Vector from Mask
+
+ r = vec_genpcvm (a, b)
+
+
+ Purpose:
+ Generate a permute control vector for expanding or compressing a
+ source vector according to a specified mask.
+
+ Result value:
+ b must have a value of 0, 1, 2,
+ or 3. a contains a bit mask
+ where the high-order bit in each element is set if the permute
+ mask should specify expansion or compression of that element, as
+ explained below.
+
+
+ If b = 0, r is assigned the value of the permute
+ control vector required to enable a left-indexed permute to
+ implement an expansion of the leftmost elements of a source
+ vector into the elements of a result vector specified by the
+ element mask in a.
+
+
+ If b = 1, r is assigned the value of the permute
+ control vector required to enable a left-indexed permute to
+ implement a compression of the sparse elements in a source
+ vector specified by the element mask in a into the leftmost elements of a
+ result vector.
+
+
+ If b = 2, r is assigned the value of the permute
+ control vector required to enable a right-indexed permute to
+ implement an expansion of the rightmost elements of a source
+ vector into the elements of a result vector specified by the
+ element mask in a.
+
+
+ If b = 3, r is assigned the value of the permute
+ control vector required to enable a right-indexed permute to
+ implement a compression of the sparse elements in a source
+ vector specified by the element mask in a into the rightmost elements of a
+ result vector.
+
+ Endian considerations:
+ None.
+
+ Notes:
+ See the descriptions of xxgenpcvbm et al. in the
+ Power Instruction Set Architecture, Version 3.1B Specification
+ () for examples of how to use
+ this function in practice.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ xxgenpcvbm
+ vec_genpcvm
+
+
+ xxgenpcvhm
+ vec_genpcvm
+
+
+ xxgenpcvwm
+ vec_genpcvm
+
+
+ xxgenpcvdm
+ vec_genpcvm
+
+
+
+ Supported type signatures for vec_genpcvm
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxgenpcvbm r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ const int
+
+
+
+ xxgenpcvhm r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const int
+
+
+
+ xxgenpcvwm r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ const int
+
+
+
+ xxgenpcvdm r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_genqm
+ Vector Generate Quadword Mask
+
+ r = vec_genqm (a)
+
+
+ Purpose:
+ Create an element mask for a quadword from a bit mask.
+
+ Result value:
+ All bits of r are set to 0 if
+ the bit in a is equal to 0.
+ Otherwise all bits of r are set
+ to 1.
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ mtvsrqm
+ vec_genqm
+
+
+
+ Supported type signatures for vec_genqm
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned __int128
+
+
+ unsigned long long
+
+
+
+ mtvsrqm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_genwm
+ Vector Generate Word Mask
+
+ r = vec_genwm (a)
+
+
+ Purpose:
+ Create an element mask for word elements from a bit mask.
+
+ Result value:
+ For each integer i from 0 to 3, do the
+ following. Counting the leftmost element of r as the 0th element, and the rightmost
+ element as the 3rd element, all bits of the
+ ith element of r are set to 0 if the
+ ith bit of the 4-bit value in a is equal to 0. All bits of the
+ ith element of r are set to 1 if the
+ ith bit of the 4-bit value in a is equal to 1. The bits in a are likewise numbered from left to
+ right.
+
+ Endian considerations:
+ Because elements are numbered from left to right in the result
+ vector regardless of endianness, the semantics of this built-in
+ function differ on big-endian and little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ mtvsrwm
+ vec_genwm
+
+
+
+ Supported type signatures for vec_genwm
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ unsigned long long
+
+
+
+ mtvsrwm r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_gnb
Vector Gather Nth Bits
@@ -42560,6 +44004,554 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_stril
+ Vector String Isolate Left-Justified
+
+ r = vec_stril (a)
+
+
+ Purpose:
+ Copy a null-terminated string of elements from the input vector
+ to the output vector, replacing all elements following the first
+ zero element with zeros.
+
+ Result value:
+ Elements in a are copied, in
+ natural element order, to corresponding elements of r until the first zero element of
+ a is encountered, or until all
+ elements have been copied. If a zero element is encountered,
+ all remaining elements of r are
+ set to zero.
+
+ Endian considerations:
+ The element numbering within a register is left-to-right for
+ big-endian targets, and right-to-left for little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vstribr
+ vec_stril
+
+
+ vstribl
+ vec_stril
+
+
+ vstrihr
+ vec_stril
+
+
+ vstrihl
+ vec_stril
+
+
+
+ Supported type signatures for vec_stril
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+
+ vstribr r,a
+
+
+
+
+ vstribl r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+
+ vstribr r,a
+
+
+
+
+ vstribl r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+
+ vstrihr r,a
+
+
+
+
+ vstrihl r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+
+ vstrihr r,a
+
+
+
+
+ vstrihl r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_stril_p
+ Vector String Isolate Left-Justified (Predicate)
+
+ r = vec_stril_p (a)
+
+
+ Purpose:
+ Returns a nonzero value if and only if the input vector contains
+ at least one zero element.
+
+ Result value:
+ r contains a nonzero value if
+ and only if a contains at least
+ one nonzero value.
+
+ Endian considerations:
+ None.
+
+ Notes:
+ I suggest renaming this to vec_any_zero, and not
+ having vec_strir_p.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vstribr
+ vec_stril_p
+
+
+ vstribl
+ vec_stril_p
+
+
+ vstrihr
+ vec_stril_p
+
+
+ vstrihl
+ vec_stril_p
+
+
+ mfocrf
+ vec_stril_p
+
+
+ rlwinm
+ vec_stril_p
+
+
+
+ Supported type signatures for vec_stril_p
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+
+ vstribr. t,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+
+ vstribl. r,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+
+ vstribr. r,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+
+ vstribl. r,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+
+ vstrihr. r,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+
+ vstrihl. r,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+
+ vstrihr. r,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+
+ vstrihl. r,a
+ mfocrf u,2
+ rlwinm r,u,25,1
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_strir
+ Vector String Isolate Right-Justified
+
+ r = vec_strir (a)
+
+
+ Purpose:
+ Copy a null-terminated string of elements from the input vector
+ to the output vector, replacing all elements following the first
+ zero element with zeros. Elements appear in the reverse of
+ natural element order.
+
+ Result value:
+ Elements in a are copied, in
+ the reverse of natural element order, to corresponding elements
+ of r until the first zero
+ element of a is encountered, or
+ until all elements have been copied. If a zero element is
+ encountered, all remaining elements of r are set to zero.
+
+ Endian considerations:
+ The element numbering within a register is left-to-right for
+ big-endian targets, and right-to-left for little-endian targets.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vstribr
+ vec_strir
+
+
+ vstribl
+ vec_strir
+
+
+ vstrihr
+ vec_strir
+
+
+ vstrihl
+ vec_strir
+
+
+
+ Supported type signatures for vec_strir
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+
+ vstribl r,a
+
+
+
+
+ vstribr r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+
+ vstribl r,a
+
+
+
+
+ vstribr r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+
+ vstrihl r,a
+
+
+
+
+ vstrihr r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+
+ vstrihl r,a
+
+
+
+
+ vstrihr r,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_sub
Vector Subtract
@@ -44800,6 +46792,208 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_test_lsbb_all_ones
+ Vector Test Least-Significant Bit by Byte for All
+ Ones
+
+ r = vec_test_lsbb_all_ones (a)
+
+
+ Purpose:
+ Test whether the least-significant bit of all bytes of the input
+ operand are equal to one.
+
+ Result value:
+ r is set to 1 if the
+ least-significant bit of all bytes of a are equal to 1. Otherwise, r is set to 0.
+
+ Endian considerations:
+ None.
+
+ Notes:
+ In the example implementation, "mask" is an 8-bit mask where the
+ only set bit identifies condition register field
+ t, and "bit" identifies the first bit
+ position in condition register field t.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ xvtlsbb
+ vec_test_lsbb_all_ones
+
+
+ mfocrf
+ vec_test_lsbb_all_ones
+
+
+ rlwinm
+ vec_test_lsbb_all_ones
+
+
+
+ Supported type signatures for vec_test_lsbb_all_ones
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ int
+
+
+ vector unsigned char
+
+
+
+ xvtlsbb t,a
+ mfocrf u,mask
+ rlwinm r,u,bit,1
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_test_lsbb_all_zeros
+ Vector Test Least-Significant Bit by Byte for All
+ Zeros
+
+ r = vec_test_lsbb_all_zeros (a)
+
+
+ Purpose:
+ Test whether the least-significant bit of all bytes of the input
+ operand are equal to zero.
+
+ Result value:
+ r is set to 1 if the
+ least-significant bit of all bytes of a are equal to 0. Otherwise, r is set to 0.
+
+ Endian considerations:
+ None.
+
+ Notes:
+ In the example implementation, "mask" is an 8-bit mask where the
+ only set bit identifies condition register field
+ t, and "bit" identifies the third bit
+ position in condition register field t.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ xvtlsbb
+ vec_test_lsbb_all_zeros
+
+
+ mfocrf
+ vec_test_lsbb_all_zeros
+
+
+ rlwinm
+ vec_test_lsbb_all_zeros
+
+
+
+ Supported type signatures for vec_test_lsbb_all_zeros
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ int
+
+
+ vector unsigned char
+
+
+
+ xvtlsbb t,a
+ mfocrf u,mask
+ rlwinm r,u,bit,1
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_trunc
Vector Truncate