diff --git a/Intrinsics_Reference/ch_intro.xml b/Intrinsics_Reference/ch_intro.xml index ab385b0..4fad449 100644 --- a/Intrinsics_Reference/ch_intro.xml +++ b/Intrinsics_Reference/ch_intro.xml @@ -97,10 +97,6 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro"> the Power SIMD (single-instruction, multiple-data) instructions. - - Write an introductory paragraph about the MMA facility and the - ACC registers. -
Little-Endian Linux diff --git a/Intrinsics_Reference/ch_mma_reference.xml b/Intrinsics_Reference/ch_mma_reference.xml index d0a761f..fee36c7 100644 --- a/Intrinsics_Reference/ch_mma_reference.xml +++ b/Intrinsics_Reference/ch_mma_reference.xml @@ -28,10 +28,20 @@ Specification (see ) introduced instructions to accelerate matrix multiplication computations. These instructions operate both on the VSRs and - on new 512-bit accumulator registers (ACCs). Intrinsic + on eight new 512-bit accumulator registers (ACCs). Intrinsic functions to access these instructions are described in this chapter. + + Although the ACCs are treated as separate registers from the + VSRs, each ACC[i] may use its associated VSRs + 4i to 4i+3 as scratch space. That is, + when ACC[i] contains defined data, the contents of + VSRs 4i to 4i+3 are undefined until + either an xxmfacc instruction is used to copy the + contents of ACC[i] to the VSRs, or some other + instruction directly writes to one of these VSRs. + Review status: This chapter is not yet reviewed by anyone. diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index 9104fe3..7b4d4d9 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -10613,7 +10613,8 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> b must have a value between 1 and the number of elements of a, inclusive. + role="bold">a, inclusive, but need not be a literal + constant. Endian considerations: The element numbering within a register is left-to-right for @@ -10684,7 +10685,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vector signed char - const int + unsigned int @@ -10708,7 +10709,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vector unsigned char - const int + unsigned int @@ -10751,7 +10752,8 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> b must have a value between 1 and the number of elements of a, inclusive. + role="bold">a, inclusive, but need not be a literal + constant. Endian considerations: The element numbering within a register is left-to-right for @@ -10822,7 +10824,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vector signed char - const int + unsigned int @@ -10846,7 +10848,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vector unsigned char - const int + unsigned int