diff --git a/Intrinsics_Reference/ch_mma_reference.xml b/Intrinsics_Reference/ch_mma_reference.xml
index e94d877..fb94d63 100644
--- a/Intrinsics_Reference/ch_mma_reference.xml
+++ b/Intrinsics_Reference/ch_mma_reference.xml
@@ -90,6 +90,14 @@
stxvp
__builtin_vsx_stxvp
+
+ lxvpx
+ __builtin_vsx_lxvp
+
+
+ stxvpx
+ __builtin_vsx_stxvp
+
@@ -109,24 +117,32 @@
+
__vector_pair __builtin_vsx_lxvp (signed long a, const __vector_pair* b)
+
lxvp r,a(b)
+ or
+ lxvpx r,b,a
+
void __builtin_vsx_stxvp (__vector_pair s, signed long a, const __vector_pair* b)
+
stxvp s,a(b)
+ or
+ stxvpx s,b,a
@@ -140,7 +156,7 @@
The following builtins are used to construct
__vector_pair and __vector_quad
- objects from smaller vectors, and deconstruct them into such
+ objects from 128-bit vectors, and deconstruct them into such
vectors. The disassembly interfaces place the results into
arrays of vectors.
diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml
index eb17696..ebaffa1 100644
--- a/Intrinsics_Reference/ch_vec_reference.xml
+++ b/Intrinsics_Reference/ch_vec_reference.xml
@@ -10220,8 +10220,323 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+
+
+ vec_blendv
+ Vector Blend Variable
+
+ r = vec_blendv (a, b, c)
+
+
+ Purpose:
+ Blend two source vectors according to the sign bits of the
+ corresponding elements of a third source vector.
+
+ Result value:
+ For each element of c, if bit 0
+ of that element is equal to 0, the corresponding element of
+ r is set to the corresponding
+ element of a. Otherwise, the
+ corresponding element of r is
+ set to the corresponding element of b.
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ xxblendvb
+ vec_blendv
+
+
+ xxblendvh
+ vec_blendv
+
+
+ xxblendvw
+ vec_blendv
+
+
+ xxblendvd
+ vec_blendv
+
+
+ Supported type signatures for vec_blendv
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+
+ xxblendvb r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+
+ xxblendvb r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+
+ xxblendvh r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+
+ xxblendvh r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+
+ xxblendvw r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+
+ xxblendvw r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+
+ xxblendvd r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+
+ xxblendvd r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+
+ xxblendvw r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+
+ xxblendvd r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
vec_ceil
Vector Ceiling
@@ -19261,6 +19576,498 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_extracth
+ Vector Extract High-Order
+
+ r = vec_extracth (a, b, c)
+
+
+ Purpose:
+ Extract an element from a pair of vectors using an index in
+ reverse of natural order.
+
+ Result value:
+ Let v be a wide vector
+ consisting of a concatenated
+ with b. Let e be the element of v starting at byte position c in the reverse of natural byte order.
+ Then doubleword element 1 of r
+ is set to e, and doubleword
+ element 0 of r is set to zero.
+
+ Endian considerations:
+ The byte and element numbering within a register is
+ left-to-right for big-endian targets, and right-to-left for
+ little-endian targets.
+
+ Notes:
+ The byte index c must be in the
+ range 0 to 31. The results are undefined if the byte index does
+ not address an element boundary.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vextubvlx
+ vec_extracth
+
+
+ vextubvrx
+ vec_extracth
+
+
+ vextuhvlx
+ vec_extracth
+
+
+ vextuhvrx
+ vec_extracth
+
+
+ vextuwvlx
+ vec_extracth
+
+
+ vextuwvrx
+ vec_extracth
+
+
+ vextddvlx
+ vec_extracth
+
+
+ vextddvrx
+ vec_extracth
+
+
+ xxpermdi
+ vec_extracth
+
+
+
+ Supported type signatures for vec_extracth
+
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ unsigned int
+
+
+
+ vextdubvlx r,b,a,c
+
+
+
+
+
+ vextdubvrx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ unsigned int
+
+
+
+ vextduhvlx r,b,a,c
+
+
+
+
+
+ vextduhvrx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+
+ vextduwvlx r,b,a,c
+
+
+
+
+
+ vextduwvrx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ unsigned int
+
+
+
+ vextddvlx r,b,a,c
+
+
+
+
+
+ vextddvrx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_extractl
+ Vector Extract Low-Order
+
+ r = vec_extractl (a, b, c)
+
+
+ Purpose:
+ Extract an element from a pair of vectors using an index in
+ natural order.
+
+ Result value:
+ Let v be a wide vector
+ consisting of a concatenated
+ with b. Let e be the element of v starting at byte position c in natural byte order. Then doubleword
+ element 1 of r is set to
+ e, and doubleword element 0 of
+ r is set to zero.
+
+ Endian considerations:
+ The byte and element numbering within a register is
+ left-to-right for big-endian targets, and right-to-left for
+ little-endian targets.
+
+ Notes:
+ The byte index c must be in the
+ range 0 to 31. The results are undefined if the byte index does
+ not address an element boundary.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vextubvlx
+ vec_extractl
+
+
+ vextubvrx
+ vec_extractl
+
+
+ vextuhvlx
+ vec_extractl
+
+
+ vextuhvrx
+ vec_extractl
+
+
+ vextuwvlx
+ vec_extractl
+
+
+ vextuwvrx
+ vec_extractl
+
+
+ vextddvlx
+ vec_extractl
+
+
+ vextddvrx
+ vec_extractl
+
+
+ xxpermdi
+ vec_extractl
+
+
+
+ Supported type signatures for vec_extractl
+
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ unsigned int
+
+
+
+ vextdubvrx r,b,a,c
+
+
+
+
+
+ vextdubvlx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ unsigned int
+
+
+
+ vextduhvrx r,b,a,c
+
+
+
+
+
+ vextduhvlx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+
+ vextduwvrx r,b,a,c
+
+
+
+
+
+ vextduwvlx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ unsigned int
+
+
+
+ vextddvrx r,b,a,c
+
+
+
+
+
+ vextddvlx t,a,b,c
+ xxswapd r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_extractm
Vector Extract Mask
@@ -22352,6 +23159,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+ Notes:
+ When a is a constant, compilers
+ may generate the mtvsrbmi instruction as an
+ optimization.
+
@@ -23712,6 +24524,726 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_inserth
+ Vector Insert High-Indexed
+
+ r = vec_inserth (a, b, c)
+
+
+ Purpose:
+ Insert a source element into a source vector at a specified
+ byte position in reverse of natural byte order.
+
+ Result value:
+ When a is a scalar, let
+ e be equal to a. Otherwise, when a is a vector, let e be the rightmost element of the
+ leftmost doubleword of a in
+ register order. Then the result r is set to the value of b with e
+ inserted at byte position c,
+ counting in reverse of natural byte order. Other than the bytes
+ modified by the insert operation, bytes of r are identical to the corresponding
+ bytes of b.
+
+ Endian considerations:
+ The byte and element numbering within a register is
+ left-to-right for big-endian targets, and right-to-left for
+ little-endian targets. Note that this operation is not
+ semantically equivalent for big- and little-endian targets when
+ a is a vector, because the
+ element chosen for insertion is at the same location in the
+ vector, regardless of target endianness.
+
+ Notes:
+ The byte index c must be in the
+ range 0 to 15. The results are undefined if the byte index does
+ not address an element boundary.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vinsblx
+ vec_inserth
+
+
+ vinsbrx
+ vec_inserth
+
+
+ vinshlx
+ vec_inserth
+
+
+ vinshrx
+ vec_inserth
+
+
+ vinswlx
+ vec_inserth
+
+
+ vinswrx
+ vec_inserth
+
+
+ vinsdlx
+ vec_inserth
+
+
+ vinsdrx
+ vec_inserth
+
+
+ vinsbvlx
+ vec_inserth
+
+
+ vinsbvrx
+ vec_inserth
+
+
+ vinshvlx
+ vec_inserth
+
+
+ vinshvrx
+ vec_inserth
+
+
+ vinswvlx
+ vec_inserth
+
+
+ vinswvrx
+ vec_inserth
+
+
+
+ Supported type signatures for vec_inserth
+
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ unsigned char
+
+
+ vector unsigned char
+
+
+ unsigned int
+
+
+
+ vinsblx r/b,c,a
+
+
+
+
+
+ vinsbrx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ unsigned short
+
+
+ vector unsigned short
+
+
+ unsigned int
+
+
+
+ vinshlx r/b,c,a
+
+
+
+
+
+ vinshrx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+
+ vinswlx r/b,c,a
+
+
+
+
+
+ vinswrx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ unsigned long long
+
+
+ vector unsigned long long
+
+
+ unsigned int
+
+
+
+ vinsdlx r/b,c,a
+
+
+
+
+
+ vinsdrx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ unsigned int
+
+
+
+ vinsbvlx r/b,c,a
+
+
+
+
+
+ vinsbvrx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ unsigned int
+
+
+
+ vinshvlx r/b,c,a
+
+
+
+
+
+ vinshvrx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+
+ vinswvlx r/b,c,a
+
+
+
+
+ vinswvrx r/b,c,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_insertl
+ Vector Insert Low-Indexed
+
+ r = vec_insertl (a, b, c)
+
+
+ Purpose:
+ Insert a source element into a source vector at a specified
+ byte position in natural byte order.
+
+ Result value:
+ When a is a scalar, let
+ e be equal to a. Otherwise, when a is a vector, let e be the rightmost element of the
+ leftmost doubleword of a in
+ register order. Then the result r is set to the value of b with e
+ inserted at byte position c in
+ natural byte order. Other than the bytes modified by the insert
+ operation, bytes of r are
+ identical to the corresponding bytes of b.
+
+ Endian considerations:
+ The byte and element numbering within a register is
+ left-to-right for big-endian targets, and right-to-left for
+ little-endian targets. Note that this operation is not
+ semantically equivalent for big- and little-endian targets when
+ a is a vector, because the
+ element chosen for insertion is at the same location in the
+ vector, regardless of target endianness.
+
+ Notes:
+ The byte index c must be in the
+ range 0 to 15. The results are undefined if the byte index does
+ not address an element boundary.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vinsblx
+ vec_insertl
+
+
+ vinsbrx
+ vec_insertl
+
+
+ vinshlx
+ vec_insertl
+
+
+ vinshrx
+ vec_insertl
+
+
+ vinswlx
+ vec_insertl
+
+
+ vinswrx
+ vec_insertl
+
+
+ vinsdlx
+ vec_insertl
+
+
+ vinsdrx
+ vec_insertl
+
+
+ vinsbvlx
+ vec_insertl
+
+
+ vinsbvrx
+ vec_insertl
+
+
+ vinshvlx
+ vec_insertl
+
+
+ vinshvrx
+ vec_insertl
+
+
+ vinswvlx
+ vec_insertl
+
+
+ vinswvrx
+ vec_insertl
+
+
+
+ Supported type signatures for vec_insertl
+
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ unsigned char
+
+
+ vector unsigned char
+
+
+ unsigned int
+
+
+
+ vinsbrx r/b,c,a
+
+
+
+
+
+ vinsblx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ unsigned short
+
+
+ vector unsigned short
+
+
+ unsigned int
+
+
+
+ vinshrx r/b,c,a
+
+
+
+
+
+ vinshlx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+
+ vinswrx r/b,c,a
+
+
+
+
+
+ vinswlx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ unsigned long long
+
+
+ vector unsigned long long
+
+
+ unsigned int
+
+
+
+ vinsdrx r/b,c,a
+
+
+
+
+
+ vinsdlx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ unsigned int
+
+
+
+ vinsbvrx r/b,c,a
+
+
+
+
+
+ vinsbvlx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ unsigned int
+
+
+
+ vinshvrx r/b,c,a
+
+
+
+
+
+ vinshvlx r/b,c,a
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+
+ vinswvrx r/b,c,a
+
+
+
+
+ vinswvlx r/b,c,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_insert4b
Vector Insert Four Bytes
@@ -25416,6 +26948,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
Endian considerations:
None.
+ Notes:
+ For floating-point types, if both source elements contain signed
+ zeros, or if either source element contains a NaN, it is
+ undefined which of the two source elements is copied into the
+ corresponding result element.
+
vmaxsb
@@ -33468,6 +35006,369 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_permx
+ Vector Permute Extended
+
+ r = vec_permx (a, b, c, d)
+
+
+ Purpose:
+ Perform a partial permute of the first two arguments, which form
+ an aligned 32-byte section of an emulated vector up to 256 bytes
+ wide, using the partial permute control vector in the third
+ argument. The fourth argument (constrained to values of 0-7)
+ identifies which 32-byte section of the emulated vector is
+ contained in the first two arguments.
+
+ Result value:
+ Let s be the concatenation of
+ a and b. For each integer value
+ i from 0 to 15, do the following.
+
+
+ Let j be the contents of bits 3 through 7
+ of byte element i of c. If d is equal to the contents of bits 0
+ through 2 of byte element i of c, the contents of byte element
+ j of s
+ are placed into byte element i of
+ r. Otherwise the contents of
+ byte element i of r are set to zero.
+
+ Endian considerations:
+ This instruction operates in big-endian fashion, with elements
+ numbered in increasing order from left to right.
+
+ Notes: This built-in
+ function can be used to emulate permutes on vectors up to 256
+ bytes in length, and can also be used to perform a parallel
+ table lookup on up to 256-byte tables. Please see the
+ description of the xxpermx instruction in the Power
+ Instruction Set Architecture () for examples.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ xxpermx
+ vec_permx
+
+
+
+ Supported type signatures for vec_permx
+
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ d
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector unsigned char
+
+
+ const int
+
+
+
+ xxpermx r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_permxor
Vector Permute and Exclusive-OR
@@ -35080,6 +36981,492 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_replace_elt
+ Vector Replace Element
+
+ r = vec_replace_elt (a, b, c)
+
+
+ Purpose:
+ Replaces an element in a vector.
+
+ Result value:
+ The result value r is set to
+ the value of a. Then the
+ element of r indexed by
+ c using natural element order
+ is set to the value of b.
+
+ Endian considerations:
+ The element numbering within a register is left-to-right for big-endian
+ targets, and right-to-left for little-endian targets.
+
+ Notes:
+ The value of c must be between
+ 0 and 3 for word-length elements, and between 0 and 1 for
+ doubleword-length elements.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vinsw
+ vec_replace_elt
+
+
+ vinsd
+ vec_replace_elt
+
+
+
+ Supported type signatures for vec_replace_elt
+
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example LE Implementation
+
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ signed int
+
+
+ const int
+
+
+
+ vinsw r/a,b,12-4*c
+
+
+
+
+ vinsw r/a,b,4*c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+ const int
+
+
+
+ vinsw r/a,b,12-4*c
+
+
+
+
+ vinsw r/a,b,4*c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ signed long long
+
+
+ const int
+
+
+
+ vinsd r/a,b,8-8*c
+
+
+
+
+
+ vinsd r/a,b,8*c
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ unsigned long long
+
+
+ const int
+
+
+
+ vinsd r/a,b,8-8*c
+
+
+
+
+
+ vinsd r/a,b,8*c
+
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ float
+
+
+ const int
+
+
+
+ vinsw r/a,b,12-4*c
+
+
+
+
+ vinsw r/a,b,4*c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ double
+
+
+ const int
+
+
+
+ vinsd r/a,b,8-8*c
+
+
+
+
+ vinsd r/a,b,8*c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_replace_unaligned
+ Vector Replace Unaligned
+
+ r = vec_replace_unaligned (a, b, c)
+
+
+ Purpose:
+ Replaces some bytes of a vector with a given value, not
+ necessarily aligned where an element of that size would normally
+ be placed.
+
+ Result value:
+ The result value r is set to
+ the value of a. Then the
+ value of b is written to
+ r starting at the byte position
+ indicated by c in left-to-right
+ byte order.
+
+ Endian considerations:
+ The semantics of this built-in function differ for big-endian
+ and little-endian targets.
+
+ Notes:
+ The value of c must be between
+ 0 and 15.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vinsw
+ vec_replace_unaligned
+
+
+ vinsd
+ vec_replace_unaligned
+
+
+
+ Supported type signatures for vec_replace_unaligned
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ signed int
+
+
+ const int
+
+
+
+ vinsw r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+ const int
+
+
+
+ vinsw r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ signed long long
+
+
+ const int
+
+
+
+ vinsd r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ unsigned long long
+
+
+ const int
+
+
+
+ vinsd r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ float
+
+
+ const int
+
+
+
+ vinsw r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ double
+
+
+ const int
+
+
+
+ vinsd r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_revb
Vector Reverse Bytes
@@ -39199,6 +41586,272 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_sldb
+ Vector Shift Left Double Bit Immediate
+
+ r = vec_sldb (a, b, c)
+
+
+ Purpose:
+ Shifts a double-wide vector left by up to 7 bits and returns the
+ leftmost 128 bits of the result.
+
+ Result value:
+ Let v be the concatenation of
+ a and b, with a on the left. Let v' be v
+ shifted left by the number of bits specified by c. Then r is set to the leftmost 128 bits of
+ v'.
+
+ Endian considerations:
+ The semantics of this built-in function differ for big-endian
+ and little-endian targets.
+
+ Notes:
+ The value of c must be between
+ 0 and 7, inclusive.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vsldbi
+ vec_sldb
+
+
+
+ Supported type signatures for vec_sldb
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ const unsigned int
+
+
+
+ vsldbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_sldw
Vector Shift Left Double by Words
@@ -40931,7 +43584,214 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
- vector signed int
+ vector signed int
+
+
+ 5-bit signed literal
+
+
+
+ vspltisw r,a
+
+
+
+
+
+
+
+
+
+
+
+ vec_splat_u8
+ Vector Splat to Unsigned Byte
+
+ r = vec_splat_u8 (a)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value:
+ The 5-bit signed value of a is
+ sign-extended to a byte and the resulting value is cast to an
+ unsigned char. This value is placed in each element of
+ r. The range of the original value is
+ [-16:15].
+ Endian considerations:
+ None.
+
+
+
+ vspltisb
+ vec_splat_u8
+
+
+
+ Supported type signatures for vec_splat_u8
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned char
+
+
+ 5-bit signed literal
+
+
+
+ vspltisb r,a
+
+
+
+
+
+
+
+
+
+
+
+ vec_splat_u16
+ Vector Splat to Unsigned Halfword
+
+ r = vec_splat_u16 (a)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value:
+ The 5-bit signed value of a is
+ sign-extended to a halfword and the resulting value is cast to an
+ unsigned short. This value is placed in each element of
+ r. The range of the original value is
+ [-16:15].
+ Endian considerations:
+ None.
+
+
+
+ vspltish
+ vec_splat_u16
+
+
+
+ Supported type signatures for vec_splat_u16
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned short
+
+
+ 5-bit signed literal
+
+
+
+ vspltish r,a
+
+
+
+
+
+
+
+
+
+
+
+ vec_splat_u32
+ Vector Splat to Unsigned Word
+
+ r = vec_splat_u32 (a)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value:
+ The 5-bit signed value of a is
+ sign-extended to a word and the resulting value is cast to an
+ unsigned int. This value is placed in each element of
+ r. The range of the original value is
+ [-16:15].
+ Endian considerations:
+ None.
+
+
+
+ vspltisw
+ vec_splat_u32
+
+
+
+ Supported type signatures for vec_splat_u32
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned int
5-bit signed literal
@@ -40949,208 +43809,363 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
-
- vec_splat_u8
- Vector Splat to Unsigned Byte
+
+ vec_splati
+ Vector Splat Immediate
- r = vec_splat_u8 (a)
+ r = vec_splati (a)
Purpose:
- Returns a vector with all elements equal to the given value.
+ Copy an immediate value into every element of a vector.
+
+ Result value:
+ The result value r is a vector
+ with each element set to the value of a.
- Result value:
- The 5-bit signed value of a is
- sign-extended to a byte and the resulting value is cast to an
- unsigned char. This value is placed in each element of
- r. The range of the original value is
- [-16:15].
Endian considerations:
None.
+ Review status:
+ Not yet reviewed.
+
- vspltisb
- vec_splat_u8
+ xxspltiw
+ vec_splati
- Supported type signatures for vec_splat_u8
-
+ Supported type signatures for vec_splati
+
+
-
-
+
+
r
-
+
-
-
+
+
a
-
+
-
- Example Implementation
+
+
+ Example Implementation
+
+
+
+ Restrictions
+
+
- vector unsigned char
+ vector signed int
- 5-bit signed literal
+ const signed int
-
- vspltisb r,a
+
+ xxspltiw r,a
+
+ ISA 3.1 or later
+
+
+
+
+ vector float
+
+
+ const float
+
+
+
+ xxspltiw r,a
+
+
+
+ ISA 3.1 or later
+
-
+
-
- vec_splat_u16
- Vector Splat to Unsigned Halfword
+
+ vec_splati_ins
+ Vector Splat Immediate Insert
- r = vec_splat_u16 (a)
+ r = vec_splati_ins (a, b, c)
Purpose:
- Returns a vector with all elements equal to the given value.
+ Copy an immediate value into a specified word of each doubleword
+ of a vector, leaving the remaining words unchanged.
+
+ Result value:
+ If b has a value of 0, then the
+ even elements of r are set to
+ the value of c and the odd
+ elements of r are copied from
+ the corresponding elements of a. Otherwise, b must have a value of 1, and the odd
+ elements of r are set to the
+ value of c and the even
+ elements of r are copied from
+ the corresponding elements of a.
- Result value:
- The 5-bit signed value of a is
- sign-extended to a halfword and the resulting value is cast to an
- unsigned short. This value is placed in each element of
- r. The range of the original value is
- [-16:15].
Endian considerations:
- None.
+ Element numbering is left-to-right in a register for big-endian
+ targets, and right-to-left for little-endian targets.
+
+ Review status:
+ Not yet reviewed.
- vspltish
- vec_splat_u16
+ xxsplti32dx
+ vec_splati_ins
- Supported type signatures for vec_splat_u16
-
+ Supported type signatures for vec_splati_ins
+
+
+
+
+
-
-
+
+
r
-
+
-
-
+
+
a
-
+
-
- Example Implementation
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example LE Implementation
+
+
+
+ Example BE Implementation
+
+
+
+
+ Restrictions
+
+
- vector unsigned short
+ vector signed int
- 5-bit signed literal
+ vector signed int
+
+
+ const unsigned int
+
+
+ const signed int
-
- vspltish r,a
+
+ xxsplti32dx r/a,1-b,c
+
+
+
+
+ xxsplti32dx r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const unsigned int
+
+
+ const unsigned int
+
+
+
+ xxsplti32dx r/a,1-b,c
+
+
+
+
+ xxsplti32dx r/a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ const unsigned int
+
+
+ const float
+
+
+
+ xxsplti32dx r/a,1-b,c
+
+
+
+
+ xxsplti32dx r/a,b,c
+
+ ISA 3.1 or later
+
-
+
-
- vec_splat_u32
- Vector Splat to Unsigned Word
+
+ vec_splatid
+ Vector Splat Immediate Double
- r = vec_splat_u32 (a)
+ r = vec_splatid (a)
Purpose:
- Returns a vector with all elements equal to the given value.
+ Convert an immediate single-precision floating-point value to
+ double precision, and copy the result into every element of a vector.
+
+ Result value:
+ The result value r is a vector
+ with each element set to the value of a when converted to double precision.
- Result value:
- The 5-bit signed value of a is
- sign-extended to a word and the resulting value is cast to an
- unsigned int. This value is placed in each element of
- r. The range of the original value is
- [-16:15].
Endian considerations:
None.
+ Notes:
+ If a is a single-precision
+ denormal value, the value of r
+ is undefined.
+
+ Review status:
+ Not yet reviewed.
+
- vspltisw
- vec_splat_u32
+ xxspltidp
+ vec_splatid
- Supported type signatures for vec_splat_u32
-
+ Supported type signatures for vec_splatid
+
+
-
-
+
+
r
-
+
-
-
+
+
a
-
+
-
- Example Implementation
+
+
+ Example Implementation
+
+
+
+ Restrictions
+
+
- vector unsigned int
+ vector double
- 5-bit signed literal
+ const float
-
- vspltisw r,a
+
+ xxspltidp r,a
+
+ ISA 3.1 or later
+
-
+
@@ -42083,6 +45098,272 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_srdb
+ Vector Shift Right Double Bit Immediate
+
+ r = vec_srdb (a, b, c)
+
+
+ Purpose:
+ Shifts a double-wide vector right by up to 7 bits and returns the
+ rightmost 128 bits of the result.
+
+ Result value:
+ Let v be the concatenation of
+ a and b, with a on the left. Let v' be v
+ shifted right by the number of bits specified by c. Then r is set to the rightmost 128 bits of
+ v'.
+
+ Endian considerations:
+ The semantics of this built-in function differ for big-endian
+ and little-endian targets.
+
+ Notes:
+ The value of c must be between
+ 0 and 7, inclusive.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vsrdbi
+ vec_srdb
+
+
+
+ Supported type signatures for vec_srdb
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ const unsigned int
+
+
+
+ vsrdbi r,a,b,c
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_srl
Vector Shift Right Long
@@ -50569,6 +53850,361 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_xl_sext
+ Load VSX Vector Element and Sign Extend
+
+ r = vec_xl_sext (a, b)
+
+
+ Purpose:
+ Load a single element into a vector register and sign extend it
+ to a 128-bit integer.
+
+ Result value:
+ Let x be the addressed formed
+ by adding a and b. Then r is set to the value of the element
+ loaded from address x and
+ sign-extended to 128 bits. The type of the loaded element is
+ specified by the pointer type of argument b.
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ lxvrbx
+ vec_xl_sext
+
+
+ lxvrhx
+ vec_xl_sext
+
+
+ lxvrwx
+ vec_xl_sext
+
+
+ lxvrdx
+ vec_xl_sext
+
+
+ vextsb2d
+ vec_xl_sext
+
+
+ vextsh2d
+ vec_xl_sext
+
+
+ vextsw2d
+ vec_xl_sext
+
+
+ vextsd2q
+ vec_xl_sext
+
+
+
+ Supported type signatures for vec_xl_sext
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed char *
+
+
+
+ lxvrbx t,b,a
+ vextsb2d u,t
+ vextsd2q r,u
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed short *
+
+
+
+ lxvrhx t,b,a
+ vextsh2d u,t
+ vextsd2q r,u
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed int *
+
+
+
+ lxvrwx t,b,a
+ vextsw2d u,t
+ vextsd2q r,u
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed long long *
+
+
+
+ lxvrdx t,b,a
+ vextsd2q r,t
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xl_zext
+ Load VSX Vector Element and Zero Extend
+
+ r = vec_xl_zext (a, b)
+
+
+ Purpose:
+ Load a single element into a vector register and zero-extend it
+ to a 128-bit unsigned integer.
+
+ Result value:
+ Let x be the addressed formed
+ by adding a and b. Then r is set to the value of the element
+ loaded from address x and
+ zero-extended to 128 bits. The type of the loaded element is
+ specified by the pointer type of argument b.
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ lxvrbx
+ vec_xl_zext
+
+
+ lxvrhx
+ vec_xl_zext
+
+
+ lxvrwx
+ vec_xl_zext
+
+
+ lxvrdx
+ vec_xl_zext
+
+
+
+ Supported type signatures for vec_xl_zext
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned char *
+
+
+
+ lxvrbx r,b,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned short *
+
+
+
+ lxvrhx r,b,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned int *
+
+
+
+ lxvrwx r,b,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned long long *
+
+
+
+ lxvrdx r,b,a
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_xor
Vector Exclusive OR
@@ -51895,6 +55531,244 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+
+
+ vec_xst_trunc
+ Truncate and Store from VSX Vector
+
+ vec_xst_trunc (a, b, c)
+
+
+ Purpose:
+ Truncate the value in a vector register and store it.
+
+ Operation:
+ The rightmost element of a
+ (using the element type specified by the pointer type of
+ c) is stored to the address
+ formed by adding b and
+ c.
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ stxvrbx
+ vec_xst_trunc
+
+
+ stxvrhx
+ vec_xst_trunc
+
+
+ stxvrwx
+ vec_xst_trunc
+
+
+ stxvrdx
+ vec_xst_trunc
+
+
+
+ Supported type signatures for vec_xst_trunc
+
+
+
+
+
+
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed char *
+
+
+
+ stxvrbx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned char *
+
+
+
+ stxvrbx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed short *
+
+
+
+ stxvrhx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned short *
+
+
+
+ stxvrhx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed int *
+
+
+
+ stxvrwx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned int *
+
+
+
+ stxvrwx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector signed __int128
+
+
+ signed long
+
+
+ signed long long *
+
+
+
+ stxvrdx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long
+
+
+ unsigned long long *
+
+
+
+ stxvrdx a,c,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+