diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml
index 7caee0a..262d9fa 100644
--- a/Intrinsics_Reference/ch_vec_reference.xml
+++ b/Intrinsics_Reference/ch_vec_reference.xml
@@ -6070,6 +6070,16920 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics">
+
+
+
+ vec_extract_exp
+ Vector ... Spelled Out Name TBD
+
+ r = vec_extract_exp (ARG1)
+
+
+ Purpose:
+ Extracts an exponent from a floating-point number.
+
+ Result value: Each element of the returned integer vector is extracted from the exponent field of the corresponding floating-point vector element.
+The extracted exponents of ARG1 are returned as
+ right-justified unsigned integers containing biased exponents, in
+ accordance with the exponent representation specified by IEEE
+ 754, without further processing.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_extract_exp
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_extract_fp32_from_shorth
+ Vector ... Spelled Out Name TBD
+
+ r = vec_extract_fp32_from_shorth (ARG1)
+
+
+ Purpose:
+ Extracts four single-precision floating-point numbers from the high elements of a vector of eight 16-bit elements, interpreting each element as a 16-bit floating-point number in IEEE format.
+
+ Result value: The first four elements are interpreted as 16-bit floating-point numbers in IEEE format, and extended to single-precision format, returning a vector with four single-precision IEEE numbers.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_extract_fp32_from_shorth
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector float
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_extract_fp32_from_shortl
+ Vector ... Spelled Out Name TBD
+
+ r = vec_extract_fp32_from_shortl (ARG1)
+
+
+ Purpose:
+
+
+ Result value: The last four elements are interpreted as 16-bit floating-point numbers in IEEE format, and extended to single-precision format, returning a vector with four single-precision IEEE numbers.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_extract_fp32_from_shortl
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector float
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_extract_sig
+ Vector ... Spelled Out Name TBD
+
+ r = vec_extract_sig (ARG1)
+
+
+ Purpose:
+ Extracts a significand (mantissa) from a floating-point number.
+
+ Result value: Each element of the returned integer vector is extracted from the significand (mantissa) field of the corresponding floating-point vector element.
+The significand is from the corresponding floating-point
+ number in accordance with the IEEE format. The returned result
+ includes the implicit leading digit. The value of that digit is
+ not encoded in the IEEE format, but is implied by the
+ exponent.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_extract_sig
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_extract4b
+ Vector ... Spelled Out Name TBD
+
+ r = vec_extract4b (ARG1, ARG2)
+
+
+ Purpose:
+ Extracts a word from a vector at a byte position.
+
+ Result value: The first doubleword element of the result contains the zero-extended extracted word from ARG1. The second doubleword is set to 0. ARG2 specifies the least-significant byte number (0–12) of the word to be extracted.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_extract4b
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_first_match_index
+ Vector ... Spelled Out Name TBD
+
+ r = vec_first_match_index (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a comparison of equality on each of the corresponding elements of ARG1 and ARG2, and returns the first position of equality.
+
+ Result value: Returns the element index of the position of the first character match. If no match, returns the number of characters as an element count in the vector argument.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_first_match_index
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ unsigned int
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_first_match_or_eos_index
+ Vector ... Spelled Out Name TBD
+
+ r = vec_first_match_or_eos_index (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a comparison of equality on each of the corresponding elements of ARG1 and ARG2. Returns the first position of equality, or the zero string terminator.
+
+ Result value: Returns the element index of the position of either the first character match or an end-of-string (EOS) terminator. If no match or terminator, returns the number of characters as an element count in the vector argument.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_first_match_or_eos_index
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ unsigned int
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_first_mismatch_index
+ Vector ... Spelled Out Name TBD
+
+ r = vec_first_mismatch_index (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a comparison of inequality on each of the corresponding elements of ARG1 and ARG2, and returns the first position of inequality.
+
+ Result value: Returns the element index of the position of the first character mismatch. If no mismatch, returns the number of characters as an element count in the vector argument.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_first_mismatch_index
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ unsigned int
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_first_mismatch_or_eos_index
+ Vector ... Spelled Out Name TBD
+
+ r = vec_first_mismatch_or_eos_index (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a comparison of inequality on each of the corresponding elements of ARG1 and ARG2. Returns the first position of inequality, or the zero string terminator.
+
+ Result value: Returns the element index of the position of either the first character mismatch or an end-of-string (EOS) terminator. If no mismatch or terminator, returns the number of characters as an element count in the vector argument.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_first_mismatch_or_eos_index
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ unsigned int
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_float
+ Vector ... Spelled Out Name TBD
+
+ r = vec_float (ARG1)
+
+
+ Purpose:
+ Converts a vector of integers to a vector of single-precision floating-point numbers.
+
+ Result value: Target elements are obtained by converting the respective source elements to single-precision floating-point numbers.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_float
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector float
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_float2
+ Vector ... Spelled Out Name TBD
+
+ r = vec_float2 (ARG1, ARG2)
+
+
+ Purpose:
+ Converts an input vector to a vector of single-precision numbers.
+
+ Result value: Target elements are obtained by converting the source elements to single-precision numbers as follows:
+
+
+ Target elements 0 and 1 from source 0
+
+
+ Target elements 2 and 3 from source 1
+
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_float2
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector float
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_floate
+ Vector ... Spelled Out Name TBD
+
+ r = vec_floate (ARG2)
+
+
+ Purpose:
+ Converts an input vector to a vector of single-precision numbers.
+
+ Result value: The even-numbered target elements are obtained by converting the source elements to single-precision numbers, using the current floating-point rounding mode.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_floate
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector float
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_floath
+ Vector ... Spelled Out Name TBD
+
+ r = vec_floath (ARG2)
+
+
+ Purpose:
+ Converts a vector to a vector of single-precision floating-point numbers.
+
+ Result value: Target elements 0 through 3 are set to the converted values of source elements 0 through 3, respectively.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_floath
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector float
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_floatl
+ Vector ... Spelled Out Name TBD
+
+ r = vec_floatl (ARG2)
+
+
+ Purpose:
+ Converts a vector to a vector of single-precision floating-point numbers.
+
+ Result value: Target elements 0 through 3 are set to the converted values of source elements 4 through 7, respectively.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_floatl
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector float
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_floato
+ Vector ... Spelled Out Name TBD
+
+ r = vec_floato (ARG2)
+
+
+ Purpose:
+ Converts an input vector to a vector of single-precision numbers.
+
+ Result value: The odd-numbered target elements are obtained by converting the source elements to single-precision numbers, using the current floating-point rounding mode.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_floato
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector float
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_floor
+ Vector ... Spelled Out Name TBD
+
+ r = vec_floor (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the largest representable floating-point integral values less than or equal to the values of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the largest representable floating-point integral value less than or equal to the value of the corresponding element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_floor
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_gb
+ Vector ... Spelled Out Name TBD
+
+ r = vec_gb (ARG1)
+
+
+ Purpose:
+ Performs a gather-bits operation on the input.
+
+ Result value: Within each doubleword, let x(i) (0 ≤ i < 8) denote the byte elements of the corresponding input doubleword element, with x(7) the most-significant byte. For each pair of i and j (0 ≤ i < 8, 0 ≤ j < 8), the j-th bit of the i-th byte element of the result is set to the value of the i-th bit of the j-th byte element of the input.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_gb
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_insert
+ Vector ... Spelled Out Name TBD
+
+ r = vec_insert (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a copy of vector ARG2 with element ARG3 replaced by the value of ARG1.
+
+ Result value: A copy of vector ARG2 with element ARG3 replaced by the value of ARG1. This function uses modular arithmetic on ARG3 to determine the element number. For example, if ARG3 is out of range, the compiler uses ARG3 modulo the number of elements in the vector to determine the element position.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_insert
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector signed char
+
+
+ signed char
+
+
+ vector signed char
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ unsigned char
+
+
+ vector unsigned char
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ signed int
+
+
+ vector signed int
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+ vector unsigned int
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ signed long long
+
+
+ vector signed long long
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ unsigned long long
+
+
+ vector unsigned long long
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ signed short
+
+
+ vector signed short
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ unsigned short
+
+
+ vector unsigned short
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ double
+
+
+ vector double
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ float
+
+
+ vector float
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ _Float16
+
+
+ vector _Float16
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_insert_exp
+ Vector ... Spelled Out Name TBD
+
+ r = vec_insert_exp (ARG1, ARG2)
+
+
+ Purpose:
+ Inserts an exponent into a floating-point number.
+
+ Result value: Each element of the returned floating-point vector is generated by combining the exponent specified by the corresponding element of ARG2 with the sign and significand of the corresponding element of ARG1.
+The inserted exponent of ARG2 is treated as a
+ right-justified unsigned integer containing a biased exponent, in
+ accordance with the exponent representation specified by IEEE
+ 754. It is combined with the sign and significand of ARG1 without
+ further processing.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_insert_exp
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector double
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector float
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_insert4b
+ Vector ... Spelled Out Name TBD
+
+ r = vec_insert4b (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Inserts a word into a vector at a byte position.
+
+ Result value: Let W be the first doubleword element of ARG1, truncated to 32 bits. The result vector is formed by inserting W into ARG2 at the byte position (0–12) specified by ARG3.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_insert4b
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector signed int
+
+
+ vector unsigned char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_loge
+ Vector ... Spelled Out Name TBD
+
+ r = vec_loge (ARG1)
+
+
+ Purpose:
+ Returns a vector containing estimates of the base-2 logarithms of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the estimated value of the base-2 logarithm of the corresponding element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_loge
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_madd
+ Vector ... Spelled Out Name TBD
+
+ r = vec_madd (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a fused multiply-add operation for each corresponding set of elements of the given vectors.
+
+ Result value: The value of each element of the result is the product of the values of the corresponding elements of ARG1 and ARG2, added to the value of the corresponding element of ARG3.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_madd
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector unsigned short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_madds
+ Vector ... Spelled Out Name TBD
+
+ r = vec_madds (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a saturated multiply-high-and-add operation for each corresponding set of elements of the given vectors.
+
+ Result value: For each element of the result, the value is produced in the following way: The values of the corresponding elements of ARG1 and ARG2 are multiplied. The value of the 17 most-significant bits of this product is then added, using 16-bit-saturated addition, to the value of the corresponding element of ARG3.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_madds
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_max
+ Vector ... Spelled Out Name TBD
+
+ r = vec_max (ARG1, ARG2)
+
+
+ Purpose:
+
+
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_max
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_mergee
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mergee (ARG1, ARG2)
+
+
+ Purpose:
+ Merges the even-numbered values from the two vectors.
+
+ Result value: The even-numbered elements of ARG1 are stored into the even-numbered elements of the result. The even-numbered elements of ARG2 are stored in the odd-numbered elements of the result.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mergee
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_mergeh
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mergeh (ARG1, ARG2)
+
+
+ Purpose:
+ Merges the most-significant halves of two vectors.
+
+ Result value: Assume that the elements of each vector are numbered beginning with 0. The even-numbered elements of the result are taken, in order, from the elements in the most-significant 8 bytes of ARG1. The odd-numbered elements of the result are taken, in order, from the elements in the most-significant 8 bytes of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mergeh
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_mergel
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mergel (ARG1, ARG2)
+
+
+ Purpose:
+ Merges the least-significant halves of two vectors.
+
+ Result value: Assume that the elements of each vector are numbered beginning with 0. The even-numbered elements of the result are taken, in order, from the elements in the least-significant 8 bytes of ARG1. The odd-numbered elements of the result are taken, in order, from the elements in the least-significant 8 bytes of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mergel
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_mergeo
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mergeo (ARG1, ARG2)
+
+
+ Purpose:
+ Merges the odd-numbered halves of two vectors.
+
+ Result value: The odd-numbered elements of ARG1 are stored in the even-numbered elements of the result.
+The odd-numbered elements of ARG2 are stored in the
+ odd-numbered elements of the result.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mergeo
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_min
+ Vector ... Spelled Out Name TBD
+
+ r = vec_min (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the minimum value from each set of corresponding elements of the given vectors.
+
+ Result value: The value of each element of the result is the minimum of the values of the corresponding elements of ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_min
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_mradds
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mradds (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a saturated multiply-high-round-and-add operation for each corresponding set of elements of the given vectors.
+
+ Result value: For each element of the result, the value is produced in the following way: The values of the corresponding elements of ARG1 and ARG2 are multiplied and rounded such that the 15 least-significant bits are 0. The value of the 17 most-significant bits of this rounded product is then added, using 16-bit-saturated addition, to the value of the corresponding element of ARG3.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mradds
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_msub
+ Vector ... Spelled Out Name TBD
+
+ r = vec_msub (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a multiply-subtract operation using the given vectors.
+
+ Result value: This function multiplies each element in ARG1 by the corresponding element in ARG2 and then subtracts the corresponding element in ARG3 from the result.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_msub
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_msum
+ Vector ... Spelled Out Name TBD
+
+ r = vec_msum (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a multiply-sum operation using the given vectors.
+
+ Result value: Assume that the elements of each vector are numbered beginning with 0. If ARG1 is a vector signed char or a vector unsigned char vector, then let m be 4. Otherwise, let m be 2. For each element n of the result vector, the value is obtained in the following way: For p = mn to mn + m – 1, multiply element p of ARG1 by element p of ARG2. Add the sum of these products to element n of ARG3. All additions are performed using 32-bit modular arithmetic.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_msum
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_msums
+ Vector ... Spelled Out Name TBD
+
+ r = vec_msums (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a saturated multiply-sum operation using the given vectors.
+
+ Result value: Assume that the elements of each vector are numbered beginning with 0. For each element n of the result vector, the value is obtained in the following way: For p = 2n to 2n+1, multiply element p of ARG1 by element p of ARG2. Add the sum of these products to element n of ARG3. All additions are performed using 32-bit saturated arithmetic.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_msums
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_mul
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mul (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a multiply operation using the given vectors.
+
+ Result value: This function multiplies corresponding elements in the given vectors and then assigns the result to corresponding elements in the result vector.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mul
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_mule
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mule (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the results of multiplying every second set of the corresponding elements of the given vectors, beginning with the first element.
+
+ Result value: Assume that the elements of each vector are numbered beginning with 0. For each element n of the result vector, the value is the product of the value of element 2n of ARG1 and the value of element 2n of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mule
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_mulo
+ Vector ... Spelled Out Name TBD
+
+ r = vec_mulo (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the results of multiplying every second set of corresponding elements of the given vectors, beginning with the second element.
+
+ Result value: Assume that the elements of each vector are numbered beginning with 0. For each element n of the result vector, the value is the product of the value of element 2n+1 of ARG1 and the value of element 2n+1 of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_mulo
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_nabs
+ Vector ... Spelled Out Name TBD
+
+ r = vec_nabs (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the negated absolute values of the contents of the given vector.
+
+ Result value: The value of each element of the result is the negated absolute value of the corresponding element of ARG1. For integer vectors, the arithmetic is modular.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_nabs
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_nand
+ Vector ... Spelled Out Name TBD
+
+ r = vec_nand (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a bitwise NAND of the given vectors.
+
+ Result value: The result is the bitwise NAND of ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_nand
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_nearbyint
+ Vector ... Spelled Out Name TBD
+
+ r = vec_nearbyint (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the floating-point integral values nearest to the values of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the nearest representable floating-point integral value to the value of the corresponding element of ARG1. When an input element value is exactly between two integer values, the result value with the largest absolute value is selected.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_nearbyint
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_neg
+ Vector ... Spelled Out Name TBD
+
+ r = vec_neg (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the negated values of the contents of the given vector.
+
+ Result value: The value of each element of the result is the negated value of the corresponding element of ARG1. For integer vectors, the arithmetic is modular.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_neg
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_nmadd
+ Vector ... Spelled Out Name TBD
+
+ r = vec_nmadd (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a negative multiply-add operation on the given vectors.
+
+ Result value: The value of each element of the result is the product of the corresponding elements of ARG1 and ARG2, added to the corresponding elements of ARG3, then multiplied by –1.0.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_nmadd
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_nmsub
+ Vector ... Spelled Out Name TBD
+
+ r = vec_nmsub (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a negative multiply-subtract operation on the given vectors.
+
+ Result value: The value of each element of the result is the product of the corresponding elements of ARG1 and ARG2, subtracted from the corresponding element of ARG3, and then multiplied by –1.0.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_nmsub
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_nor
+ Vector ... Spelled Out Name TBD
+
+ r = vec_nor (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a bitwise NOR of the given vectors.
+
+ Result value: The result is the bitwise NOR of ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_nor
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_or
+ Vector ... Spelled Out Name TBD
+
+ r = vec_or (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a bitwise OR of the given vectors.
+
+ Result value: The result is the bitwise OR of ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_or
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_orc
+ Vector ... Spelled Out Name TBD
+
+ r = vec_orc (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a bitwise OR of the first vector with the negated second vector.
+
+ Result value: The result is the bitwise OR of ARG1 and the bitwise negation of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_orc
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_pack
+ Vector ... Spelled Out Name TBD
+
+ r = vec_pack (ARG1, ARG2)
+
+
+ Purpose:
+ Packs information from each element of two vectors into the result vector.
+
+ Result value: For integer types, the value of each element of the result vector is taken from the low-order half of the corresponding element of the result of concatenating ARG1 and ARG2.
+For floating-point types, the value of each element of the
+ result vector is the corresponding element of the result of
+ concatenating ARG1 and ARG2, rounded to the result type.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_pack
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_pack_to_short_fp32
+ Vector ... Spelled Out Name TBD
+
+ r = vec_pack_to_short_fp32 (ARG1, ARG2)
+
+
+ Purpose:
+ Packs eight single-precision 32-bit floating-point numbers into a vector of eight 16-bit floating-point numbers.
+
+ Result value: The value is a vector consisting of eight 16-bit elements, each representing a 16-bit floating-point number that was created by converting the corresponding single-precision value to half-precision.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_pack_to_short_fp32
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_packpx
+ Vector ... Spelled Out Name TBD
+
+ r = vec_packpx (ARG1, ARG2)
+
+
+ Purpose:
+ Packs information from each element of two vectors into the result vector.
+
+ Result value: The value of each element of the result vector is taken from the corresponding element of the result of concatenating ARG1 and ARG2 as follows:
+
+
+ The least-significant bit of the high-order byte is
+ stored into the first bit of the result element.
+
+
+ The least-significant 5 bits of each of the remaining
+ bytes are stored into the remaining portion of the result
+ element.
+
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_packpx
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector pixel
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_packs
+ Vector ... Spelled Out Name TBD
+
+ r = vec_packs (ARG1, ARG2)
+
+
+ Purpose:
+ Packs information from each element of two vectors into the result vector, using saturated values.
+
+ Result value: The value of each element of the result vector is the saturated value of the corresponding element of the result of concatenating ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_packs
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_packsu
+ Vector ... Spelled Out Name TBD
+
+ r = vec_packsu (ARG1, ARG2)
+
+
+ Purpose:
+ Packs information from each element of two vectors into the result vector, using unsigned saturated values.
+
+ Result value: The value of each element of the result vector is the saturated value of the corresponding element of the result of concatenating ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_packsu
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_parity_lsbb
+ Vector ... Spelled Out Name TBD
+
+ r = vec_parity_lsbb (ARG1)
+
+
+ Purpose:
+ Compute parity on the least-significant bit of each byte.
+
+ Result value: Returns a vector with each element containing the parity of the low-order bit of each of the bytes in that element.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_parity_lsbb
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ vector signed __int128
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_perm
+ Vector ... Spelled Out Name TBD
+
+ r = vec_perm (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector that contains some elements of two vectors, in the order specified by a third vector.
+
+ Result value: Each byte of the result is selected by using the least-significant 5 bits of the corresponding byte of ARG3 as an index into the concatenated bytes of ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_perm
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_permxor
+ Vector ... Spelled Out Name TBD
+
+ r = vec_permxor (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Applies a permute and exclusive-OR operation on two vectors of byte elements.
+
+ Result value: For each i (0 ≤ i < 16), let index1 be bits 0–3 and index2 be bits 4–7 of byte element i of mask ARG3.
+Byte element i of the result is set to the exclusive-OR of
+ byte elements index1 of ARG1 and index2 of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_permxor
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_popcnt
+ Vector ... Spelled Out Name TBD
+
+ r = vec_popcnt (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the number of bits set in each element of the input vector.
+
+ Result value: The value of each element of the result is the number of bits set in the corresponding input element.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_popcnt
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_re
+ Vector ... Spelled Out Name TBD
+
+ r = vec_re (ARG1)
+
+
+ Purpose:
+ Returns a vector containing estimates of the reciprocals of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the estimated value of the reciprocal of the corresponding element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_re
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_recipdiv
+ Vector ... Spelled Out Name TBD
+
+ r = vec_recipdiv (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing approximations of the division of the corresponding elements of ARG1 by the corresponding elements of ARG2. This implementation provides an implementation-dependent precision, which is commonly within 2 ulps for most of the numeric range expressible by the input operands. This built-in function does not correspond to a single IEEE operation and does not provide the overflow, underflow, and NaN propagation characteristics specified for IEEE division. (Precision may be a function of both the specified target processor model during compilation and the actual processor on which a program is executed.)
+
+ Result value: Each element of the result vector contains a refined approximation of the division of the corresponding element of ARG1 by the corresponding element of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_recipdiv
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_revb
+ Vector ... Spelled Out Name TBD
+
+ r = vec_revb (ARG1)
+
+
+ Purpose:
+ Reverse the bytes of each vector element of a vector.
+
+ Result value: Returns a vector where each vector element contains the corresponding byte-reversed vector element of the input vector.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_revb
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_reve
+ Vector ... Spelled Out Name TBD
+
+ r = vec_reve (ARG1)
+
+
+ Purpose:
+ Reverse the elements of a vector.
+
+ Result value: Returns a vector with the elements of the input vector in reversed order.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_reve
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_rint
+ Vector ... Spelled Out Name TBD
+
+ r = vec_rint (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the floating-point integral values nearest to the values of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the nearest representable floating-point integral value to the value of the corresponding element of ARG1. When an input element value is exactly between two integer values, the result value is selected based on the rounding mode specified by the Floating-Point Rounding Control field (RN) of the FPSCR register.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_rint
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_rl
+ Vector ... Spelled Out Name TBD
+
+ r = vec_rl (ARG1, ARG2)
+
+
+ Purpose:
+ Rotates each element of a vector left by a given number of bits.
+
+ Result value: Each element of the result is obtained by rotating the corresponding element of ARG1 left by the number of bits specified by the corresponding element of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_rl
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_rlmi
+ Vector ... Spelled Out Name TBD
+
+ r = vec_rlmi (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Rotates each element of a vector left and inserts each element under a mask.
+
+ Result value: The result is obtained by rotating each element of vector ARG1 left and inserting it under mask into ARG2. ARG3 bits 11:15 contain the mask beginning, bits 19:23 contain the mask end, and bits 27:31 contain the shift count.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_rlmi
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_rlnm
+ Vector ... Spelled Out Name TBD
+
+ r = vec_rlnm (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Rotates each element of a vector left; then intersects (AND) it with a mask.
+
+ Result value: Each element of vector ARG1 is rotated left; then intersected (AND) with a mask specified by ARG2 and ARG3.
+ARG2 contains the shift count for each element in the
+ low-order byte, with other bytes zero. ARG3 contains the mask
+ begin and mask end for each element, with the mask end in the
+ low-order byte, the mask begin in the next higher byte, and
+ other bytes zero.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_rlnm
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_round
+ Vector ... Spelled Out Name TBD
+
+ r = vec_round (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the rounded values of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the value of the corresponding element of ARG1, rounded to the nearest representable floating-point integer, using IEEE round-to-nearest rounding.
+
+ This function might not follow the strict
+ operation definition of the resolution of a tie during a
+ round if the -qstrict=nooperationprecision compiler option is
+ specified to the XLC compiler.
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_round
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_rsqrt
+ Vector ... Spelled Out Name TBD
+
+ r = vec_rsqrt (ARG1)
+
+
+ Purpose:
+ Returns a vector containing a refined approximation of the reciprocal square roots of the corresponding elements of the given vector. This function provides an implementation-dependent greater precision than VEC_RSQRTE.
+
+ Result value: Each element of the result contains a refined approximation of the reciprocal square root of the corresponding element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_rsqrt
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_rsqrte
+ Vector ... Spelled Out Name TBD
+
+ r = vec_rsqrte (ARG1)
+
+
+ Purpose:
+ Returns a vector containing estimates of the reciprocal square roots of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the estimated value of the reciprocal square root of the corresponding element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_rsqrte
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sel
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sel (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the value of either ARG1 or ARG2 depending on the value of ARG3.
+
+ Result value: Each bit of the result vector has the value of the corresponding bit of ARG1 if the corresponding bit of ARG3 is 0. Otherwise, each bit of the result vector has the value of the corresponding bit of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sel
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_signed
+ Vector ... Spelled Out Name TBD
+
+ r = vec_signed (ARG1)
+
+
+ Purpose:
+ Converts a vector of floating-point numbers to a vector of signed integers.
+
+ Result value: Target elements are obtained by truncating the respective source elements to signed integers.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_signed
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_signed2
+ Vector ... Spelled Out Name TBD
+
+ r = vec_signed2 (ARG1, ARG2)
+
+
+ Purpose:
+ Converts a vector of floating-point numbers to vector of signed integers.
+
+ Result value: Target elements are obtained by truncating the source elements to the signed integers as follows:
+
+
+ Target elements 0 and 1 from source 0
+
+
+ Target elements 2 and 3 from source 1
+
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_signed2
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_signede
+ Vector ... Spelled Out Name TBD
+
+ r = vec_signede (ARG1)
+
+
+ Purpose:
+ Converts an input vector to a vector of signed integers.
+
+ Result value: The even target elements are obtained by truncating the source elements to signed integers as follows:
+Target elements 0 and 2 contain the converted values of the
+ input vector.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_signede
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_signedo
+ Vector ... Spelled Out Name TBD
+
+ r = vec_signedo (ARG1)
+
+
+ Purpose:
+ Converts an input vector to a vector of signed integers.
+
+ Result value: The odd target elements are obtained by truncating the source elements to signed integers as follows:
+Target elements 1 and 3 contain the converted values of the
+ input vector.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_signedo
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sl
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sl (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a left shift for each element of a vector.
+
+ Result value: Each element of the result vector is the result of left shifting the corresponding element of ARG1 by the number of bits specified by the value of the corresponding element of ARG2, modulo the number of bits in the element. The bits that are shifted out are replaced by zeros.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sl
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sld
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sld (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Left shifts a double vector (that is, two concatenated vectors) by a given number of bytes. For vec_sld being performed on the vector bool and floating-point types, the result is undefined, when the specified shift count is not a multiple of the element size.
+
+ Result value: The result is the most-significant 16 bytes obtained by concatenating ARG1 and ARG2 and shifting left by the number of bytes specified by ARG3, which should be in the range 0–15.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sld
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sldw
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sldw (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector obtained by shifting left the concatenated input vectors by the number of specified words.
+
+ Result value: The value of each element is set to the value of an input element of the concatenated vectors ARG1 and ARG2, with the word offset to its right
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sldw
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sll
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sll (ARG1, ARG2)
+
+
+ Purpose:
+ Left shifts a vector by a given number of bits.
+
+ Result value: The result is the contents of ARG1, shifted left by the number of bits specified by the three least-significant bits of ARG2. The bits that are shifted out are replaced by zeros. The shift count must have been replicated into all bytes of the shift count specification.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sll
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_slo
+ Vector ... Spelled Out Name TBD
+
+ r = vec_slo (ARG1, ARG2)
+
+
+ Purpose:
+ Left shifts a vector by a given number of bytes (octets).
+
+ Result value: The result is the contents of ARG1, shifted left by the number of bytes specified by the most-significant nibble of the least-significant byte
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_slo
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_slv
+ Vector ... Spelled Out Name TBD
+
+ r = vec_slv (ARG1, ARG2)
+
+
+ Purpose:
+ Left-shifts a vector by a varying number of bits by element.
+
+ Result value: For each integer 0
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_slv
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_splat
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splat (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector that has all of its elements set to a given value.
+
+ Result value: The value of each element of the result is the value of the element of ARG1 specified by ARG2, which should be an element number less than the number of elements supported for the respective ARG1 type.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splat
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ vector _Float16
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_splat_s8
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splat_s8 (ARG1)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value: The bit pattern of ARG1 is interpreted as a signed value. Each element of the result is given this value.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splat_s8
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_splat_s16
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splat_s16 (ARG1)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value: Each element of the result has the value of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splat_s16
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_splat_s32
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splat_s32 (ARG1)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value: Each element of the result has the value of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splat_s32
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_splat_u8
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splat_u8 (ARG1)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value: The bit pattern of ARG1 is interpreted as an unsigned value. Each element of the result is given this value.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splat_u8
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned char
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_splat_u16
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splat_u16 (ARG1)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value: The bit pattern of ARG1 is interpreted as an unsigned value. Each element of the result is given this value.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splat_u16
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned short
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_splat_u32
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splat_u32 (ARG1)
+
+
+ Purpose:
+ Returns a vector with all elements equal to the given value.
+
+ Result value: The bit pattern of ARG1 is interpreted as an unsigned value. Each element of the result is given this value.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splat_u32
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned int
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_splats
+ Vector ... Spelled Out Name TBD
+
+ r = vec_splats (ARG1)
+
+
+ Purpose:
+ Returns a vector with the value of each element set to ARG1.
+
+ Result value: Each element of the result is set to the value of the scalar input parameter.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_splats
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector signed char
+
+
+ signed char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed __int128
+
+
+ signed __int128
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned __int128
+
+
+ unsigned __int128
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ signed long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_sqrt
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sqrt (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the square root of each element in the given vector.
+
+ Result value: Each element of the result vector is the square root of the corresponding element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sqrt
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sr
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sr (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a logical right shift for each element of a vector.
+
+ Result value: Each element of the result vector is the result of logically right shifting the corresponding element of ARG1 by the number of bits specified by the value of the corresponding element of ARG2, modulo the number of bits in the element. The bits that are shifted out are replaced by zeros.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sr
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sra
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sra (ARG1, ARG2)
+
+
+ Purpose:
+ Performs an algebraic right shift for each element of a vector.
+
+ Result value: Each element of the result vector is the result of algebraically right shifting the corresponding element of ARG1 by the number of bits specified by the value of the corresponding element of ARG2, modulo the number of bits in the element. The bits that are shifted out are replaced by copies of the most-significant bit of the element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sra
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_srl
+ Vector ... Spelled Out Name TBD
+
+ r = vec_srl (ARG1, ARG2)
+
+
+ Purpose:
+ Right shifts a vector by a given number of bits.
+
+ Result value: The result is the contents of ARG1, shifted right by the number of bits specified by the 3 least-significant bits of ARG2. The bits that are shifted out are replaced by zeros. The shift count must have been replicated into all bytes of the shift count specification.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_srl
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sro
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sro (ARG1, ARG2)
+
+
+ Purpose:
+ Right shifts a vector by a given number of bytes (octets).
+
+ Result value: The result is the contents of ARG1, shifted right by the number of bytes specified by bits 121–124 of ARG2. The bits that are shifted out are replaced by zeros.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sro
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector pixel
+
+
+ vector pixel
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_srv
+ Vector ... Spelled Out Name TBD
+
+ r = vec_srv (ARG1, ARG2)
+
+
+ Purpose:
+ Right-shifts a vector by a varying number of bits by element.
+
+ Result value: For each integer 1
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_srv
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_sub
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sub (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the result of subtracting each element of ARG2 from the corresponding element of ARG1. This function emulates the operation on long long vectors.
+
+ Result value: The value of each element of the result is the result of subtracting the value of the corresponding element of ARG2 from the value of the corresponding element of ARG1. The arithmetic is modular for integer vectors.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sub
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_subc
+ Vector ... Spelled Out Name TBD
+
+ r = vec_subc (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the carry produced by subtracting each set of corresponding elements of the given vectors.
+
+ Result value: The value of each element of the result is the value of the carry produced by subtracting the value of the corresponding element of ARG2 from the value of the corresponding element of ARG1. The value is 0 if a borrow occurred, or 1 if no borrow occurred.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_subc
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sube
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sube (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the result of first elementwise subtracting vector ARG2 from vector ARG1, and then elementwise adding vector ARG3 to the difference. ARG3 is a carry vector, with each element having a value of 0 or 1.
+
+ Result value: The value of each element of the result is produced by subtracting the corresponding element of ARG2 from the corresponding element of ARG1, and then adding the carry specified in the corresponding element of ARG3 (1 if there is a carry, 0 otherwise).
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sube
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_subec
+ Vector ... Spelled Out Name TBD
+
+ r = vec_subec (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Returns a vector containing the carries produced by first elementwise subtracting vector ARG2 from vector ARG1, and then elementwise adding vector ARG3 to the difference. ARG3 is a carry vector, with each element having a value of 0 or 1.
+
+ Result value: The value of each element of the result is the carry produced by subtracting the corresponding element of ARG2 from the corresponding element of ARG1, and then adding the carry specified in the corresponding element of ARG3 (1 if there is a carry, 0 otherwise).
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_subec
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ vector signed __int128
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_subs
+ Vector ... Spelled Out Name TBD
+
+ r = vec_subs (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the saturated differences of each set of corresponding elements of the given vectors.
+
+ Result value: The value of each element of the result is the saturated result of subtracting the value of the corresponding element of ARG2 from the value of the corresponding element of ARG1.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_subs
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sum2s
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sum2s (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a sum-across-doublewords vector operation on the given vectors.
+
+ Result value: The first and third element of the result are 0. The second element of the result contains the saturated sum of the first and second elements of ARG1 and the second element of ARG2. The fourth element of the result contains the saturated sum of the third and fourth elements of ARG1 and the fourth element of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sum2s
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sum4s
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sum4s (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a sum-across-words vector operation on the given vectors.
+
+ Result value: Assume that the elements of each vector are numbered beginning with 0. If ARG1 is a vector signed char vector or a vector unsigned char vector, then let m be 4. Otherwise, let m be 2. For each element n of the result vector, the value is obtained by adding elements mn through mn + m – 1 of ARG1 and element n of ARG2 using saturated addition.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sum4s
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed char
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed short
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned char
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_sums
+ Vector ... Spelled Out Name TBD
+
+ r = vec_sums (ARG1, ARG2)
+
+
+ Purpose:
+ Returns a vector containing the results of performing a sum across vector operation on the given vectors.
+
+ Result value: The first three elements of the result are 0. The fourth element is the saturated sum of all the elements of ARG1 and the fourth element of ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_sums
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_test_data_class
+ Vector ... Spelled Out Name TBD
+
+ r = vec_test_data_class (ARG1, ARG2)
+
+
+ Purpose:
+ Determines the data class for each floating-point element.
+
+ Result value: Each element is set to all ones if the corresponding element of ARG1 matches one of the possible data types selected by ARG2. If not, each element is set to all zeros. ARG2 can select one of the data types defined in
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_test_data_class
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool int
+
+
+ vector float
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector bool long long
+
+
+ vector double
+
+
+ const int
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_trunc
+ Vector ... Spelled Out Name TBD
+
+ r = vec_trunc (ARG1)
+
+
+ Purpose:
+ Returns a vector containing the truncated values of the corresponding elements of the given vector.
+
+ Result value: Each element of the result contains the value of the corresponding element of ARG1, truncated to an integral value.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_trunc
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_unpackh
+ Vector ... Spelled Out Name TBD
+
+ r = vec_unpackh (ARG1)
+
+
+ Purpose:
+ Unpacks the most-significant (“high”) half of a vector into a vector with larger elements.
+
+ Result value: If ARG1 is an integer vector, the value of each element of the result is the value of the corresponding element of the most-significant half of ARG1.
+If ARG1 is a floating-point vector, the value of each
+ element of the result is the value of the corresponding element
+ of the most-significant half of ARG1, widened to the result
+ precision.
+If ARG1 is a pixel vector, the value of each element of the
+ result is taken from the corresponding element of the
+ most-significant half of ARG1 as follows:
+
+
+ All bits in the first byte of the element of the result
+ are set to the value of the first bit of the element of
+ ARG1.
+
+
+ The least-significant 5 bits of the second byte of the
+ element of the result are set to the value of the next 5 bits
+ in the element of ARG1.
+
+
+ The least-significant 5 bits of the third byte of the
+ element of the result are set to the value of the next 5 bits
+ in the element of ARG1.
+
+
+ The least-significant 5 bits of the fourth byte of the
+ element of the result are set to the value of the next 5 bits
+ in the element of ARG1.
+
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_unpackh
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector pixel
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_unpackl
+ Vector ... Spelled Out Name TBD
+
+ r = vec_unpackl (ARG1)
+
+
+ Purpose:
+ Unpacks the least-significant (“low”) half of a vector into a vector with larger elements.
+
+ Result value: If ARG1 is an integer vector, the value of each element of the result is the value of the corresponding element of the least-significant half of ARG1.
+If ARG1 is a floating-point vector, the value of each
+ element of the result is the value of the corresponding element
+ of the least-significant half of ARG, widened to the result
+ precision.
+If ARG1 is a pixel vector, the value of each element of the
+ result is taken from the corresponding element of the
+ least-significant half of ARG1 as follows:
+
+
+ All bits in the first byte of the element of the result
+ are set to the value of the first bit of the element of
+ ARG1.
+
+
+ The least-significant 5 bits of the second byte of the
+ element of the result are set to the value of the next 5 bits
+ in the element of ARG1.
+
+
+ The least-significant 5 bits of the third byte of the
+ element of the result are set to the value of the next 5 bits
+ in the element of ARG1.
+
+
+ The least-significant 5 bits of the fourth byte of the
+ element of the result are set to the value of the next 5 bits
+ in the element of ARG1.
+
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_unpackl
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector bool int
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector pixel
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool long long
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector bool short
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ vector _Float16
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_unsigned
+ Vector ... Spelled Out Name TBD
+
+ r = vec_unsigned (ARG1)
+
+
+ Purpose:
+ Converts a vector of double-precision numbers to a vector of unsigned integers.
+
+ Result value: Target elements are obtained by truncating the respective source elements to unsigned integers.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_unsigned
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_unsigned2
+ Vector ... Spelled Out Name TBD
+
+ r = vec_unsigned2 (ARG1, ARG2)
+
+
+ Purpose:
+ Converts a vector of double-precision numbers to a vector of unsigned integers.
+
+ Result value: Target elements are obtained by truncating the source elements to the unsigned integers as follows:
+
+
+ Target elements 0 and 1 from source 0
+
+
+ Target elements 2 and 3 from source 1
+
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_unsigned2
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_unsignede
+ Vector ... Spelled Out Name TBD
+
+ r = vec_unsignede (ARG1)
+
+
+ Purpose:
+ Converts an input vector to a vector of unsigned integers.
+
+ Result value: The even target elements are obtained by truncating the source elements to unsigned integers as follows:
+Target elements 0 and 2 contain the converted values of the
+ input vector.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_unsignede
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_unsignedo
+ Vector ... Spelled Out Name TBD
+
+ r = vec_unsignedo (ARG1)
+
+
+ Purpose:
+ Converts an input vector to a vector of unsigned integers.
+
+ Result value: The odd target elements are obtained by truncating the source elements to unsigned integers as follows:
+Target elements 1 and 3 contain the converted values of the
+ input vector.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_unsignedo
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector unsigned int
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_xl
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xl (ARG1, ARG2)
+
+
+ Purpose:
+ Loads a 16-byte vector from the memory address specified by the displacement and the pointer.
+
+ Result value: This function adds the displacement and the pointer R-value to obtain the address for the load operation.
+
+ For languages that support built-in
+ methods for pointer dereferencing, such as the C/C++ pointer
+ dereference * and array access [ ] operators, use of the
+ native operators is encouraged and use of the vec_xl
+ intrinsic is discouraged.
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xl
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector signed char
+
+
+ signed long long
+
+
+ signed char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ signed long long
+
+
+ unsigned char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ signed long long
+
+
+ signed int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ signed long long
+
+
+ unsigned int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed __int128
+
+
+ signed long long
+
+
+ signed __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long long
+
+
+ unsigned __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed signed long long
+
+
+ signed long long
+
+
+ signed long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ signed long long
+
+
+ unsigned long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ signed long long
+
+
+ signed short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ signed long long
+
+
+ unsigned short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ signed long long
+
+
+ double *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ signed long long
+
+
+ float *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ signed long long
+
+
+ _Float16 *
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xl_be
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xl_be (ARG1, ARG2)
+
+
+ Purpose:
+ In little-endian environments, loads the elements of the 16-byte vector ARG1 starting with the highest-numbered element at the memory address specified by the displacement ARG1 and the pointer ARG2. In big-endian environments, this operator performs the same operation as VEC_XL.
+
+ Result value: In little-endian mode, loads the elements of the vector in sequential order, with the highest-numbered element loaded from the lowest data address and the lowest-numbered element of the vector at the highest address. All elements are loaded in little-endian data format.
+This function adds the displacement and the pointer R-value
+ to obtain the address for the load operation. It does not
+ truncate the affected address to a multiple of 16 bytes.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xl_be
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector signed char
+
+
+ signed long long
+
+
+ signed char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ signed long long
+
+
+ unsigned char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed int
+
+
+ signed long long
+
+
+ signed int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned int
+
+
+ signed long long
+
+
+ unsigned int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed __int128
+
+
+ signed long long
+
+
+ signed __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned __int128
+
+
+ signed long long
+
+
+ unsigned __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed long long
+
+
+ signed long long
+
+
+ signed long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ signed long long
+
+
+ unsigned long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector signed short
+
+
+ signed long long
+
+
+ signed short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector unsigned short
+
+
+ signed long long
+
+
+ unsigned short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector double
+
+
+ signed long long
+
+
+ double *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector float
+
+
+ signed long long
+
+
+ float *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ vector _Float16
+
+
+ signed long long
+
+
+ _Float16 *
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xl_len
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xl_len (ARG1, ARG2)
+
+
+ Purpose:
+ Loads a vector of a specified byte length.
+
+ Result value: Loads the number of bytes specified by ARG2 from the address specified in ARG1. Initializes elements in order from the byte stream (as defined by the endianness of the operating environment). Any bytes of elements that cannot be initialized from the number of loaded bytes have a zero value.
+At least 0 and at most 16 bytes will be loaded. The length
+ is specified by the least-significant byte of ARG2, as min (mod
+ (ARG2, 256), 16). The behavior is undefined if the length
+ argument is outside of the range 0–255, or if it is not a
+ multiple of the vector element size.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xl_len
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector signed char
+
+
+ signed char *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned char
+
+
+ unsigned char *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector signed int
+
+
+ signed int *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned int
+
+
+ unsigned int *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector signed __int128
+
+
+ signed __int128 *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ unsigned __int128 *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector signed long long
+
+
+ signed long long *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned long long
+
+
+ unsigned long long *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector signed short
+
+
+ signed short *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector unsigned short
+
+
+ unsigned short *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector double
+
+
+ double *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector float
+
+
+ float *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ vector _Float16
+
+
+ _Float16 *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xl_len_r
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xl_len_r (ARG1, ARG2)
+
+
+ Purpose:
+
+
+ Result value: Loads the number of bytes specified by ARG2 from the address specified in ARG1, right justified with the first byte to the left and the last to the right. Initializes elements in order from the byte stream (as defined by the endianness of the operating environment). Any bytes of elements that cannot be initialized from the number of loaded bytes have a zero value.
+At least 0 and at most 16 bytes will be loaded. The length
+ is specified by the least-significant byte of ARG2, as min (mod
+ (ARG2, 256), 16). The behavior is undefined if the length
+ argument is outside of the range 0–255, or if it is not a
+ multiple of the vector element size.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xl_len_r
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ vector unsigned char
+
+
+ unsigned char *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xor
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xor (ARG1, ARG2)
+
+
+ Purpose:
+ Performs a bitwise XOR of the given vectors.
+
+ Result value: The result is the bitwise XOR of ARG1 and ARG2.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xor
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+ Example Implementation
+
+
+
+
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ vector bool char
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ vector signed char
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ vector bool int
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ vector signed int
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ vector bool long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ vector signed long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ sample implementation TBD
+
+
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ vector bool short
+
+
+ sample implementation TBD
+
+
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ vector signed short
+
+
+ sample implementation TBD
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ sample implementation TBD
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+ sample implementation TBD
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+
+
+
+ vec_xst
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xst (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+
+
+ Result value: Stores the provided vector in memory.
+
+ For languages that support built-in
+ methods for pointer dereferencing, such as the C/C++ pointer
+ dereference * and array access [ ] operators, use of the
+ native operators is encouraged and use of the vec_xl
+ intrinsic is discouraged.
+
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xst
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ void
+
+
+ vector signed char
+
+
+ signed long long
+
+
+ signed char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned char
+
+
+ signed long long
+
+
+ unsigned char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed int
+
+
+ signed long long
+
+
+ signed int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned int
+
+
+ signed long long
+
+
+ unsigned int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed __int128
+
+
+ signed long long
+
+
+ signed __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned __int128
+
+
+ signed long long
+
+
+ unsigned __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed long long
+
+
+ signed long long
+
+
+ signed long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned long long
+
+
+ signed long long
+
+
+ unsigned long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed short
+
+
+ signed long long
+
+
+ signed short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned short
+
+
+ signed long long
+
+
+ unsigned short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector double
+
+
+ signed long long
+
+
+ double *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector float
+
+
+ signed long long
+
+
+ float *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector _Float16
+
+
+ signed long long
+
+
+ _Float16 *
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xst_be
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xst_be (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ In little-endian environments, stores the elements of the 16-byte vector ARG1 starting with the highest-numbered element at the memory address specified by the displacement ARG1 and the pointer ARG2. In big-endian environments, this operator performs the same operation as VEC_XST.
+
+ Result value: In little-endian mode, stores the elements of the vector in sequential order, with the highest-numbered element stored at the lowest data address and the lowest-numbered element of the vector at the highest address. All elements are stored in little-endian data format.
+This function adds the displacement and the pointer R-value
+ to obtain the address for the store operation. It does not
+ truncate the affected address to a multiple of 16 bytes.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xst_be
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ void
+
+
+ vector signed char
+
+
+ signed long long
+
+
+ signed char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned char
+
+
+ signed long long
+
+
+ unsigned char *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed int
+
+
+ signed long long
+
+
+ signed int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned int
+
+
+ signed long long
+
+
+ unsigned int *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed __int128
+
+
+ signed long long
+
+
+ signed __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned __int128
+
+
+ signed long long
+
+
+ unsigned __int128 *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed long long
+
+
+ signed long long
+
+
+ signed long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned long long
+
+
+ signed long long
+
+
+ unsigned long long *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector signed short
+
+
+ signed long long
+
+
+ signed short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector unsigned short
+
+
+ signed long long
+
+
+ unsigned short *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector double
+
+
+ signed long long
+
+
+ double *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector float
+
+
+ signed long long
+
+
+ float *
+
+
+ sample implementation TBD
+
+
+
+
+
+
+
+ void
+
+
+ vector _Float16
+
+
+ signed long long
+
+
+ _Float16 *
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xst_len
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xst_len (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Stores a vector of a specified byte length.
+
+ Result value: Stores the number of bytes specified by ARG3 of the vector ARG1 to the address specified in ARG2. The bytes are obtained starting from the lowest-numbered byte of the lowest-numbered element (as defined by the endianness of the operating environment). All bytes of an element are accessed before proceeding to the next higher element.
+At least 0 and at most 16 bytes will be stored. The length
+ is specified by the least-significant byte of ARG3, as min (mod
+ (ARG3, 256), 16). The behavior is undefined if the length
+ argument is outside of the range 0–255, or if it is not a
+ multiple of the vector element size.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xst_len
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ void
+
+
+ vector signed char
+
+
+ signed char *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector unsigned char
+
+
+ unsigned char *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector signed int
+
+
+ signed int *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector unsigned int
+
+
+ unsigned int *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector signed __int128
+
+
+ signed __int128 *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector unsigned __int128
+
+
+ unsigned __int128 *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector signed long long
+
+
+ signed long long *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector unsigned long long
+
+
+ unsigned long long *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector signed short
+
+
+ signed short *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector unsigned short
+
+
+ unsigned short *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector double
+
+
+ double *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector float
+
+
+ float *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+ void
+
+
+ vector _Float16
+
+
+ _Float16 *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+
+
+
+
+ vec_xst_len_r
+ Vector ... Spelled Out Name TBD
+
+ r = vec_xst_len_r (ARG1, ARG2, ARG3)
+
+
+ Purpose:
+ Stores a right-justified vector of a specified byte length.
+
+ Result value: Stores the number of bytes specified by ARG3 of the right-justified vector ARG1 to the address specified by ARG2.
+At least 0 and at most 16 bytes will be stored. The length
+ is specified by the least-significant byte of ARG3, as min (mod
+ (ARG2, 256), 16). The behavior is undefined if the length
+ argument is outside of the range 0–255, or if it is not a
+ multiple of the vector element size.
+ Endian considerations:
+ None.
+
+
+
+ Supported type signatures for vec_xst_len_r
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ ARG1
+
+
+
+
+ ARG2
+
+
+
+
+ ARG3
+
+
+
+ Example Implementation
+
+
+ Restrictions
+
+
+
+
+
+
+ void
+
+
+ vector unsigned char
+
+
+ unsigned char *
+
+
+ size_t
+
+
+ sample implementation TBD
+
+
+ ISA 3.0 or later
+
+
+
+
+
+
+