From dedea3224e9c96d52247695cb51121b2e52c4c45 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Mon, 5 Oct 2020 13:44:49 -0500 Subject: [PATCH] Changes for RFC 2602, Vector Integer Multiply-Divide-Modulo Signed-off-by: Bill Schmidt --- Intrinsics_Reference/ch_vec_reference.xml | 717 +++++++++++++++++++++- 1 file changed, 700 insertions(+), 17 deletions(-) diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index 94d2aec..cbc0b89 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -12730,6 +12730,21 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> Endian considerations: None. + + Notes: + For integer division, when any element of b is zero, the corresponding element of + r is undefined. For signed + integer division, when an element of a is the negative number with maximum + cardinality and the corresponding element of b is negative one, the corresponding + element of r is undefined. + + + Review status: + Unreviewed. + xxspltd @@ -12759,39 +12774,114 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xvdivdp vec_div + + vdivsw + vec_div + + + vdivuw + vec_div + + + vdivsd + vec_div + + + vdivud + vec_div + Supported type signatures for vec_div - + + + - + r - + a - + b - + - Example Implementation + Example ISA 2.07 and 3.0 + Implementation + + + + + Example ISA 3.1 + Implementation + + + + + Restrictions + + + vector signed int + + + vector signed int + + + vector signed int + + + Not required + + + + vdivsw r,a,b + + + + ISA 3.1 or later + + + + + vector unsigned int + + + vector unsigned int + + + vector unsigned int + + + Not required + + + + vdivuw r,a,b + + + + ISA 3.1 or later + + vector signed long long @@ -12817,6 +12907,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xxmrghd r,z,y + + + vdivsd r,a,b + + + + + @@ -12843,6 +12941,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xxmrghd r,z,y + + + vdivud r,a,b + + + + + @@ -12859,6 +12965,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xvdivsp r,a,b + + + xvdivsp r,a,b + + + + + @@ -12875,6 +12989,192 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xvdivdp r,a,b + + + xvdivdp r,a,b + + + + + + + + +
+ + + + + + vec_dive + Vector Divide Extended + + r = vec_dive (a, b) + + + Purpose: + Divides the left-shifted elements in one vector by the + corresponding elements in another vector and places the + quotients in the result vector. + + Result value: + The value of each element of r is + obtained by shifting the corresponding element of a left by 32 bits, and then dividing that + value by the corresponding element of b. + + Endian considerations: + None. + + + Notes: + When any element of b is + zero, the corresponding element of r is undefined. If any quotient cannot + be represented in the element type of r, the corresponding element of + r is undefined. + + + Review status: + Unreviewed. + + + + vdivesw + vec_dive + + + vdiveuw + vec_dive + + + vdivesd + vec_dive + + + vdiveud + vec_dive + + + + Supported type signatures for vec_dive + + + + + + + + + + + r + + + + + a + + + + + b + + + + + Example Implementation + + + + + Restrictions + + + + + + + + vector signed int + + + vector signed int + + + vector signed int + + + + + vdivesw r,a,b + + + + + ISA 3.1 or later + + + + + vector unsigned int + + + vector unsigned int + + + vector unsigned int + + + + vdiveuw r,a,b + + + + ISA 3.1 or later + + + + + vector signed long long + + + vector signed long long + + + vector signed long long + + + + + vdivesd r,a,b + + + + + ISA 3.1 or later + + + + + vector unsigned long long + + + vector unsigned long long + + + vector unsigned long long + + + + vdiveud r,a,b + + + + ISA 3.1 or later + @@ -22306,6 +22606,187 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+ + + + vec_mod + Vector Modulo + + r = vec_mod (a, b) + + + Purpose: + Produces the remainders from dividing the elements of one vector + by the elements of another vector, and places them in the result + vector. + + Result value: + The value of each element of r is + obtained by dividing the corresponding element of a by the corresponding element of b and determining the unique signed or + unsigned integer remainder from the division. + + Endian considerations: + None. + + + Notes: + When any element of b is + zero, the corresponding element of r is undefined. For signed arithmetic, + when any element of a is the + negative number with maximum cardinality, and the + corresponding element of b is + negative one, the corresponding element of r is undefined. + + + Review status: + Unreviewed. + + + + vmodsw + vec_mod + + + vmoduw + vec_mod + + + vmodsd + vec_mod + + + vmodud + vec_mod + + + + Supported type signatures for vec_mod + + + + + + + + + + + r + + + + + a + + + + + b + + + + + Example Implementation + + + + + Restrictions + + + + + + + + vector signed int + + + vector signed int + + + vector signed int + + + + + vmodsw r,a,b + + + + + ISA 3.1 or later + + + + + vector unsigned int + + + vector unsigned int + + + vector unsigned int + + + + vmoduw r,a,b + + + + ISA 3.1 or later + + + + + vector signed long long + + + vector signed long long + + + vector signed long long + + + + + vmodsd r,a,b + + + + + ISA 3.1 or later + + + + + vector unsigned long long + + + vector unsigned long long + + + vector unsigned long long + + + + vmodud r,a,b + + + + ISA 3.1 or later + + + + +
+ + + @@ -23018,13 +23499,20 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> - There are currently no vector instructions to support vector long - long multiplication, so the compiler must perform two scalar - multiplies on the vector elements for this case. + Prior to ISA 3.1, + there are currently no vector + instructions to support vector long long multiplication, + so the compiler must perform two scalar multiplies on the + vector elements for this case. - + + Review status: + Unreviewed. + + vmulesb vec_mul @@ -23061,14 +23549,19 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xvmulsp vec_mul + + vmulld + vec_mul + Supported type signatures for vec_mul - + + @@ -23089,6 +23582,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> Example Implementation + + Restrictions + @@ -23110,6 +23606,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vperm r,t,u,v + + + @@ -23129,6 +23628,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vperm r,t,u,v + + + @@ -23146,6 +23648,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vmladduhm r,a,b,t + + + @@ -23163,6 +23668,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vmladduhm r,a,b,t + + + @@ -23179,6 +23687,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vmuluwm r,a,b + + + @@ -23195,6 +23706,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vmuluwm r,a,b + + + @@ -23206,11 +23720,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vector signed long long - - - [scalarized] + + + vmulld r,a,b + + ISA 3.1 or later + @@ -23222,11 +23739,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> vector unsigned long long - - - [scalarized] + + + vmulld r,a,b + + ISA 3.1 or later + @@ -23243,6 +23763,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xvmulsp r,a,b + + + @@ -23259,6 +23782,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> xvmuldp r,a,b + + + @@ -23504,6 +24030,163 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref"> + + vec_mulh + Vector Multiply High + + r = vec_mulh (a, b) + + + Purpose: + Multiplies the elements of the source vectors and places the + high half of each result in the target vector. + + Result value: Each element + of r is the high half of the + product of the corresponding elements of a and b. + Endian considerations: + None. + + Review status: + Unreviewed. + + + + vmulhsw + vec_mulh + + + vmulhuw + vec_mulh + + + vmulhsd + vec_mulh + + + vmulhud + vec_mulh + + +
+ Supported type signatures for vec_mulh + + + + + + + + + + + r + + + + + a + + + + + b + + + + Example Implementation + + + Restrictions + + + + + + + vector signed int + + + vector signed int + + + vector signed int + + + + vmulhsw r,a,b + + + + ISA 3.1 or later + + + + + vector unsigned int + + + vector unsigned int + + + vector unsigned int + + + + vmulhuw r,a,b + + + + ISA 3.1 or later + + + + + vector signed long long + + + vector signed long long + + + vector signed long long + + + + vmulhsd r,a,b + + + + ISA 3.1 or later + + + + + vector unsigned long long + + + vector unsigned long long + + + vector unsigned long long + + + + vmulhud r,a,b + + + + ISA 3.1 or later + + + + +
+ + + + vec_mulo Vector Multiply Odd