From ed5148441c95447615b7171c5266b601cf9bd354 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Thu, 21 Jun 2018 22:00:49 -0500 Subject: [PATCH] Updates through vec_sube. Signed-off-by: Bill Schmidt --- Intrinsics_Reference/ch_vec_reference.xml | 456 ++++++++++++++++------ 1 file changed, 330 insertions(+), 126 deletions(-) diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index 368e8ab..c1d553e 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -19471,7 +19471,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_slo Vector Shift Left by Octets - r = vec_slo (ARG1, ARG2) + r = vec_slo (a, b) Purpose: @@ -19484,7 +19484,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> role="bold">b. Endian considerations: This intrinsic is not endian-neutral, so uses of - vec_sll in big-endian code must be rewritten for little-endian targets. + vec_slo in big-endian code must be rewritten for little-endian targets. The shift count is in element 15 of b for big-endian, but in element 0 of b for little-endian. @@ -21121,15 +21121,21 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sr - Vector ... Spelled Out Name TBD + Vector Shift Right - r = vec_sr (ARG1, ARG2) + r = vec_sr (a, b) Purpose: Performs a logical right shift for each element of a vector. - Result value: Each element of the result vector is the result of logically right shifting the corresponding element of ARG1 by the number of bits specified by the value of the corresponding element of ARG2, modulo the number of bits in the element. The bits that are shifted out are replaced by zeros. + Result value: Each element of + r is the result of logically + right-shifting the corresponding element of a by the number of bits specified by the + corresponding element of b, modulo the + number of bits in the element. Zeros are shifted in from the + left. Endian considerations: None. @@ -21150,12 +21156,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -21175,7 +21181,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsrb r,a,b + @@ -21189,7 +21197,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsrb r,a,b + @@ -21203,7 +21213,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vsrw r,a,b + @@ -21217,7 +21229,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vsrw r,a,b + @@ -21231,7 +21245,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vsrd r,a,b + @@ -21245,7 +21261,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vsrd r,a,b + @@ -21259,7 +21277,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vsrh r,a,b + @@ -21273,7 +21293,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vsrh r,a,b + @@ -21285,15 +21307,21 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sra - Vector ... Spelled Out Name TBD + Vector Shift Right Algebraic - r = vec_sra (ARG1, ARG2) + r = vec_sra (a, b) Purpose: Performs an algebraic right shift for each element of a vector. - Result value: Each element of the result vector is the result of algebraically right shifting the corresponding element of ARG1 by the number of bits specified by the value of the corresponding element of ARG2, modulo the number of bits in the element. The bits that are shifted out are replaced by copies of the most-significant bit of the element of ARG1. + Result value: Each element of + r is the result of algebraically + right-shifting the corresponding element of a by the number of bits specified by the + corresponding element of b, modulo the + number of bits in the element. Copies of the sign bit are shifted in + from the left. Endian considerations: None. @@ -21314,12 +21342,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -21339,7 +21367,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsrab r,a,b + @@ -21353,7 +21383,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsrab r,a,b + @@ -21367,7 +21399,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vsraw r,a,b + @@ -21381,7 +21415,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vsraw r,a,b + @@ -21395,7 +21431,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vsrad r,a,b + @@ -21409,7 +21447,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vsrad r,a,b + @@ -21423,7 +21463,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vsrah r,a,b + @@ -21437,7 +21479,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vsrah r,a,b + @@ -21449,17 +21493,24 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_srl - Vector ... Spelled Out Name TBD + Vector Shift Right Long - r = vec_srl (ARG1, ARG2) + r = vec_srl (a, b) Purpose: Right shifts a vector by a given number of bits. - Result value: The result is the contents of ARG1, shifted right by the number of bits specified by the 3 least-significant bits of ARG2. The bits that are shifted out are replaced by zeros. The shift count must have been replicated into all bytes of the shift count specification. + Result value: Vector r contains the contents of a, shifted right by the number of bits specified + by the 3 least-significant bits of b. + Zeros are supplied on the left. The shift count must have been + replicated into all bytes of b; if not, + the value of r is undefined. Endian considerations: - None. + This intrinsic is not endian-neutral, so uses of + vec_srl in big-endian code must be rewritten for little-endian targets. @@ -21478,12 +21529,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -21503,7 +21554,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21517,7 +21570,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21531,7 +21586,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21545,7 +21602,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21559,7 +21618,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21573,7 +21634,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21587,7 +21650,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21601,7 +21666,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21615,7 +21682,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsr r,a,b + @@ -21627,17 +21696,26 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sro - Vector ... Spelled Out Name TBD + Vector Shift Right by Octets - r = vec_sro (ARG1, ARG2) + r = vec_sro (a, b) Purpose: Right shifts a vector by a given number of bytes (octets). - Result value: The result is the contents of ARG1, shifted right by the number of bytes specified by bits 121–124 of ARG2. The bits that are shifted out are replaced by zeros. + Result value: Vector + r receives the contents of + a, shifted right by the number of bytes + specified by bits 1–4 of the least-significant byte of + b. + Zeros are supplied from the left. Endian considerations: - None. + This intrinsic is not endian-neutral, so uses of + vec_sro in big-endian code must be rewritten for little-endian targets. + The shift count is in element 15 of b + for big-endian, but in element 0 of b + for little-endian.
@@ -21656,12 +21734,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -21681,7 +21759,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21695,7 +21775,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21709,7 +21791,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21723,7 +21807,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21737,7 +21823,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21751,7 +21839,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21765,7 +21855,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21779,7 +21871,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21793,7 +21887,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21807,7 +21903,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21821,7 +21919,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21835,7 +21935,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21849,7 +21951,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21863,7 +21967,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21877,7 +21983,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21891,7 +21999,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21905,7 +22015,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21919,7 +22031,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21933,7 +22047,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsro r,a,b + @@ -21947,7 +22063,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsro r,a,b + @@ -21959,17 +22077,29 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_srv - Vector ... Spelled Out Name TBD + Vector Shift Right Variable - r = vec_srv (ARG1, ARG2) + r = vec_srv (a, b) Purpose: Right-shifts a vector by a varying number of bits by element. - Result value: For each integer 1 + Result value: Let v be a 17-byte vector formed from a zero byte + in element 0 and the elements of a + in bytes [1:16]. Then each byte element i of + r is determined as follows. The + start bit sb is obtained from bits 5:7 of + byte element i of a. Then the contents of bits + (8-sb):(15-sb) of the + halfword in byte elements i:i+1 + of v are placed into byte element + i of r. Endian considerations: - None. + All bit and byte element numbers are specified in big-endian order. + This intrinsic is not endian-neutral.
@@ -21982,25 +22112,25 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b Example Implementation - + Restrictions @@ -22017,7 +22147,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsrv r,a,b + ISA 3.0 or later @@ -22032,15 +22164,22 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sub - Vector ... Spelled Out Name TBD + Vector Subtract - r = vec_sub (ARG1, ARG2) + r = vec_sub (a, b) Purpose: - Returns a vector containing the result of subtracting each element of ARG2 from the corresponding element of ARG1. This function emulates the operation on long long vectors. + Returns a vector containing the result of subtracting each element of + one source vector from the corresponding element of another source + vector. - Result value: The value of each element of the result is the result of subtracting the value of the corresponding element of ARG2 from the value of the corresponding element of ARG1. The arithmetic is modular for integer vectors. + Result value: The value of each + element of r is the result of + subtracting the value of the corresponding element of b from the value of the corresponding element of + a. The arithmetic is modular for + integer vectors. Endian considerations: None. @@ -22061,12 +22200,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a - ARG2 + b @@ -22086,7 +22225,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed char - sample implementation TBD + + vsububm r,a,b + @@ -22100,7 +22241,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + vsububm r,a,b + @@ -22114,7 +22257,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vsubuwm r,a,b + @@ -22128,7 +22273,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vsubuwm r,a,b + @@ -22142,7 +22289,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed __int128 - sample implementation TBD + + vsubuqm r,a,b + @@ -22156,7 +22305,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned __int128 - sample implementation TBD + + vsubuqm r,a,b + @@ -22170,7 +22321,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed long long - sample implementation TBD + + vsubudm r,a,b + @@ -22184,7 +22337,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vsubudm r,a,b + @@ -22198,7 +22353,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed short - sample implementation TBD + + vsubuhm r,a,b + @@ -22212,7 +22369,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + vsubuhm r,a,b + @@ -22226,7 +22385,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xvsubdp r,a,b + @@ -22240,7 +22401,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xvsubsp r,a,b + @@ -22252,15 +22415,21 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_subc - Vector ... Spelled Out Name TBD + Vector Subtract Carryout - r = vec_subc (ARG1, ARG2) + r = vec_subc (a, b) Purpose: - Returns a vector containing the carry produced by subtracting each set of corresponding elements of the given vectors. + Returns a vector containing the carry produced by subtracting each set + of corresponding elements of the given vectors. - Result value: The value of each element of the result is the value of the carry produced by subtracting the value of the corresponding element of ARG2 from the value of the corresponding element of ARG1. The value is 0 if a borrow occurred, or 1 if no borrow occurred. + Result value: The value of each + element of r is the complement of the + carry produced by subtracting the value of the corresponding element of + b from the value of the corresponding + element of a. The value is 0 if a + borrow occurred, or 1 if no borrow occurred. Endian considerations: None. @@ -22274,19 +22443,19 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b @@ -22306,7 +22475,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vsubcuw r,a,b + @@ -22320,7 +22491,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vsubcuw r,a,b + @@ -22334,7 +22507,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed __int128 - sample implementation TBD + + vsubcuq r,a,b + @@ -22348,7 +22523,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned __int128 - sample implementation TBD + + vsubcuq r,a,b + @@ -22360,18 +22537,31 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sube - Vector ... Spelled Out Name TBD + Vector Subtract Extended - r = vec_sube (ARG1, ARG2, ARG3) + r = vec_sube (a, b, c) Purpose: - Returns a vector containing the result of first elementwise subtracting vector ARG2 from vector ARG1, and then elementwise adding vector ARG3 to the difference. ARG3 is a carry vector, with each element having a value of 0 or 1. + Returns a vector containing the result of first elementwise subtracting + one vector from another vector, and then elementwise adding a third + carry vector. Elements of the carry vector have a value of 0 or 1. + + Result value: Let c' be a vector for which each element is 0 if + the rightmost bit of the corresponding element of c is 0, and 1 otherwise. Then the value of each + element of r is produced by subtracting + the corresponding element of b from the + corresponding element of a, and then + adding the corresponding element of c'. - Result value: The value of each element of the result is produced by subtracting the corresponding element of ARG2 from the corresponding element of ARG1, and then adding the carry specified in the corresponding element of ARG3 (1 if there is a carry, 0 otherwise). Endian considerations: None. + Notes: + Investigate apparent inconsistency here. +
Supported type signatures for vec_sube @@ -22383,24 +22573,24 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c @@ -22423,7 +22613,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed int - sample implementation TBD + + vspltisw t,1 + vsubuwm u,a,b + xxland v,c,t + vsubuwm r,u,v + @@ -22440,7 +22635,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vspltisw t,1 + vsubuwm u,a,b + xxland v,c,t + vsubuwm r,u,v + @@ -22457,7 +22657,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector signed __int128 - sample implementation TBD + + vsubeuqm r,a,b,c + @@ -22474,7 +22676,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned __int128 - sample implementation TBD + + vsubeuqm r,a,b,c +