From ef1925c3b8945fd03135d031f8ce22148a9a9d5d Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Sun, 17 Jun 2018 17:17:18 -0500 Subject: [PATCH] Updates through vec_signed2. Signed-off-by: Bill Schmidt --- Intrinsics_Reference/ch_vec_reference.xml | 448 +++++++++++++++------- 1 file changed, 308 insertions(+), 140 deletions(-) diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml index 9a65c32..a52633a 100644 --- a/Intrinsics_Reference/ch_vec_reference.xml +++ b/Intrinsics_Reference/ch_vec_reference.xml @@ -12726,7 +12726,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_nearbyint Vector Nearby Integer - r = vec_nearbyint (ARG1) + r = vec_nearbyint (a) Purpose: @@ -15955,7 +15955,8 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> Notes: The example implementation for vector double assumes that a register z - initially contains the double-precision floating-point value 1.0. + initially contains the double-precision floating-point value 1.0 + in each doubleword. Supported type signatures for vec_recipdiv @@ -16951,17 +16952,26 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_rlmi - Vector ... Spelled Out Name TBD + Vector Rotate Left then Mask Insert - r = vec_rlmi (ARG1, ARG2, ARG3) + r = vec_rlmi (a, b, c) Purpose: - Rotates each element of a vector left and inserts each element under a mask. + Rotates each element of a vector left and inserts each element under + a mask. - Result value: The result is obtained by rotating each element of vector ARG1 left and inserting it under mask into ARG2. ARG3 bits 11:15 contain the mask beginning, bits 19:23 contain the mask end, and bits 27:31 contain the shift count. + Result value: Each element of + r is obtained by rotating the + corresponding element of vector b left + and inserting it under mask into the corresponding element of + a. Bits 11:15 of the corresponding + element of c contain the mask + beginning, bits 19:23 contain the mask end, and bits 27:31 contain the + shift count. Endian considerations: - None. + The referenced bit numbers within the elements of c are in left-to-right order.
@@ -16975,30 +16985,30 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c Example Implementation - + Restrictions @@ -17018,7 +17028,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vrlwmi r/a,b,c + ISA 3.0 or later @@ -17038,7 +17050,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + vrldmi r/a,b,c + ISA 3.0 or later @@ -17053,20 +17067,24 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_rlnm - Vector ... Spelled Out Name TBD + Vector Rotate Left then AND with Mask - r = vec_rlnm (ARG1, ARG2, ARG3) + r = vec_rlnm (a, b, c) Purpose: - Rotates each element of a vector left; then intersects (AND) it with a mask. - - Result value: Each element of vector ARG1 is rotated left; then intersected (AND) with a mask specified by ARG2 and ARG3. -ARG2 contains the shift count for each element in the - low-order byte, with other bytes zero. ARG3 contains the mask - begin and mask end for each element, with the mask end in the - low-order byte, the mask begin in the next higher byte, and - other bytes zero. + Rotates each element of a vector left, then logically ANDs it with a + mask. + + Result value: Each element of + a is rotated left, then logically ANDed + with a mask specified by b and + c. + b contains the shift count for + each element in the low-order byte, with other bytes zero. + c contains the mask begin and mask end + for each element, with the mask end in the low-order byte, the mask + begin in the next higher byte, and other bytes zero. Endian considerations: None. @@ -17082,30 +17100,30 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c Example Implementation - + Restrictions @@ -17125,7 +17143,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + vspltisw t,8 + vslw u,b,t + xxlor v,u,c + vrlwnm r,a,v + ISA 3.0 or later @@ -17145,7 +17168,13 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxspltib t,8 + vextsb2d u,t + vsld v,b,u + xxlor w,v,c + vrldnm r,a,w + ISA 3.0 or later @@ -17160,21 +17189,24 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_round - Vector ... Spelled Out Name TBD + Vector Round - r = vec_round (ARG1) + r = vec_round (a) Purpose: - Returns a vector containing the rounded values of the corresponding elements of the given vector. - - Result value: Each element of the result contains the value of the corresponding element of ARG1, rounded to the nearest representable floating-point integer, using IEEE round-to-nearest rounding. - - This function might not follow the strict - operation definition of the resolution of a tie during a - round if the -qstrict=nooperationprecision compiler option is - specified to the XLC compiler. - + Returns a vector containing the rounded values of the corresponding + elements of the given vector. + + Result value: Each element of + r contains the value of the + corresponding element of a, rounded + to the nearest representable floating-point integer, using IEEE + round-to-nearest rounding. + Notes: This function might not + follow the strict operation definition of the resolution of a tie during + a round if the -qstrict=nooperationprecision compiler option is + specified to the XLC compiler. Endian considerations: None. @@ -17194,7 +17226,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -17211,7 +17243,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xvrdpi r,a + @@ -17222,7 +17256,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + vrfin r,a + @@ -17234,18 +17270,27 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_rsqrt - Vector ... Spelled Out Name TBD + Vector Reciprocal Square Root - r = vec_rsqrt (ARG1) + r = vec_rsqrt (a) Purpose: - Returns a vector containing a refined approximation of the reciprocal square roots of the corresponding elements of the given vector. This function provides an implementation-dependent greater precision than VEC_RSQRTE. - - Result value: Each element of the result contains a refined approximation of the reciprocal square root of the corresponding element of ARG1. + Returns a vector containing a refined approximation of the reciprocal + square roots of the corresponding elements of the given vector. This + function provides an implementation-dependent greater precision than + vec_rsqrte. + Result value: Each element of + r contains a refined approximation of + the reciprocal square root of the corresponding element of + a. Endian considerations: None. + Notes: The example implementations + assume that a register h initially + contains the floating-point value 0.5 in each element (single- or + double-precision as appropriate).
Supported type signatures for vec_rsqrt @@ -17262,7 +17307,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -17279,7 +17324,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xvrsqrtedp t,a + xvmuldp u,t,a + xvmuldp v,t,h + xxlor w,h,h + xvnmsubadp w,u,v + xvmaddadp v,v,w + xvmaddadp u,u,w + xvnmsubmdp u,v,h + xvmaddadp v,v,u + xvadddp r,v,v + @@ -17290,7 +17346,13 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xvrsqrtesp t,a + xvmulsp u,t,a + xvmulsp v,t,h + xvnmsubmsp v,u,h + xvmaddmsp r/v,t,t + @@ -17302,15 +17364,19 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_rsqrte - Vector ... Spelled Out Name TBD + Vector Reciprocal Square Root Estimate - r = vec_rsqrte (ARG1) + r = vec_rsqrte (a) Purpose: - Returns a vector containing estimates of the reciprocal square roots of the corresponding elements of the given vector. + Returns a vector containing estimates of the reciprocal square roots of + the corresponding elements of the given vector. - Result value: Each element of the result contains the estimated value of the reciprocal square root of the corresponding element of ARG1. + Result value: Each element of + r contains the estimated value of the + reciprocal square root of the corresponding element of a. Endian considerations: None. @@ -17330,7 +17396,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -17347,7 +17413,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xvrsqrtedp r,a + @@ -17358,7 +17426,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xvrsqrtesp r,a + @@ -17370,18 +17440,28 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_sel - Vector ... Spelled Out Name TBD + Vector Select - r = vec_sel (ARG1, ARG2, ARG3) + r = vec_sel (a, b, c) Purpose: - Returns a vector containing the value of either ARG1 or ARG2 depending on the value of ARG3. - - Result value: Each bit of the result vector has the value of the corresponding bit of ARG1 if the corresponding bit of ARG3 is 0. Otherwise, each bit of the result vector has the value of the corresponding bit of ARG2. + Returns a vector containing the value of either a or b + depending on the value of c. + + Result value: Each bit of + r has the value of the corresponding + bit of a if the corresponding bit of + c is 0. Otherwise, the bit of + r has the value of the corresponding + bit of b. Endian considerations: None. + Notes: + No Power compilers yet support the vector _Float16 type, so those + interfaces are currently deferred.
Supported type signatures for vec_sel @@ -17394,30 +17474,30 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - + r - + - ARG1 + a - + - ARG2 + b - + - ARG3 + c Example Implementation - + Restrictions @@ -17437,7 +17517,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxsel r,a,b,c + @@ -17457,7 +17539,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxsel r,a,b,c + @@ -17477,7 +17561,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxsel r,a,b,c + @@ -17497,7 +17583,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxsel r,a,b,c + @@ -17517,7 +17605,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool char - sample implementation TBD + + xxsel r,a,b,c + @@ -17537,7 +17627,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned char - sample implementation TBD + + xxsel r,a,b,c + @@ -17557,7 +17649,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxsel r,a,b,c + @@ -17577,7 +17671,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxsel r,a,b,c + @@ -17597,7 +17693,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxsel r,a,b,c + @@ -17617,7 +17715,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxsel r,a,b,c + @@ -17637,7 +17737,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxsel r,a,b,c + @@ -17657,7 +17759,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxsel r,a,b,c + @@ -17677,7 +17781,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17697,7 +17803,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17717,7 +17825,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17737,7 +17847,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17757,7 +17869,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17777,7 +17891,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17797,7 +17913,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxsel r,a,b,c + @@ -17817,7 +17935,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxsel r,a,b,c + @@ -17837,7 +17957,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxsel r,a,b,c + @@ -17857,7 +17979,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxsel r,a,b,c + @@ -17877,7 +18001,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxsel r,a,b,c + @@ -17897,7 +18023,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxsel r,a,b,c + @@ -17917,7 +18045,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17937,7 +18067,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned long long - sample implementation TBD + + xxsel r,a,b,c + @@ -17957,7 +18089,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool int - sample implementation TBD + + xxsel r,a,b,c + @@ -17977,7 +18111,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned int - sample implementation TBD + + xxsel r,a,b,c + @@ -17997,10 +18133,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector bool short - sample implementation TBD + + xxsel r,a,b,c + - ISA 3.0 or later + Deferred @@ -18017,10 +18155,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector unsigned short - sample implementation TBD + + xxsel r,a,b,c + - ISA 3.0 or later + Deferred @@ -18032,15 +18172,19 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_signed - Vector ... Spelled Out Name TBD + Vector Convert Floating-Point to Signed Integer - r = vec_signed (ARG1) + r = vec_signed (a) Purpose: - Converts a vector of floating-point numbers to a vector of signed integers. + Converts a vector of floating-point numbers to a vector of signed + integers. - Result value: Target elements are obtained by truncating the respective source elements to signed integers. + Result value: Each element of + r is obtained by truncating the + corresponding element of a to a signed + integer. Endian considerations: None. @@ -18060,7 +18204,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> - ARG1 + a @@ -18077,7 +18221,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector float - sample implementation TBD + + xvcvspsxws r,a + @@ -18088,7 +18234,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xvcvdpsxds r,a + @@ -18100,53 +18248,58 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vec_signed2 - Vector ... Spelled Out Name TBD + Vector Convert Double-Precision to Signed Word - r = vec_signed2 (ARG1, ARG2) + r = vec_signed2 (a, b) Purpose: - Converts a vector of floating-point numbers to vector of signed integers. + Converts two vectors of double-precision floating-point numbers to a + vector of signed 32-bit integers. - Result value: Target elements are obtained by truncating the source elements to the signed integers as follows: - - - Target elements 0 and 1 from source 0 - - - Target elements 2 and 3 from source 1 - - + Result value: Let v be the concatenation of a and b. Each + element of r is obtained by truncating + the corresponding element of v to a + signed 32-bit integer. Endian considerations: - None. + The element numbering within a register is left-to-right for big-endian + targets, and right-to-left for little-endian targets.
Supported type signatures for vec_signed2 - + + - + r - + - ARG1 + a - + - ARG2 + b - - Example Implementation + + Example LE + Implementation + + + Example BE + Implementation @@ -18162,7 +18315,22 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_vec_intrinsics"> vector double - sample implementation TBD + + xxpermdi t,b,a,3 + xxpermdi u,b,a,0 + xvcvdpsxws v,t + xvcvdpsxws w,u + vmrgow r,w,v + + + + + xxpermdi t,a,b,0 + xxpermdi u,a,b,3 + xvcvdpsxws v,t + xvcvdpsxws w,u + vmrgew r,v,w +