diff --git a/Intrinsics_Reference/ch_vec_reference.xml b/Intrinsics_Reference/ch_vec_reference.xml
index fde93a9..ad8d9bb 100644
--- a/Intrinsics_Reference/ch_vec_reference.xml
+++ b/Intrinsics_Reference/ch_vec_reference.xml
@@ -10264,8 +10264,165 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+
+
+ vec_cfuge
+ Vector Centrifuge
+
+ r = vec_cfuge (a, b)
+
+
+ Purpose:
+ For each element in an input vector, separates its bits to the
+ right and left within a target vector element, according to the
+ mask in the corresponding element of a second input vector.
+
+ Result value:
+ For each element of a, the bits
+ whose corresponding bits in the mask in the corresponding
+ element of b equal 1 are placed
+ in the rightmost bits in the corresponding element of r, maintaining their original relative
+ order. The other bits of the element of a are placed in the leftmost bits in the
+ corresponding element of r,
+ maintaining their original relative order.
+
+ An example for doubleword inputs follows:
+
+
+
+
+
+
+
+
+
+
+
+ Element 0
+
+
+ Element 1
+
+
+
+
+
+
+ a
+
+
+ 0x0123456789abcdef
+
+
+ 0x0123456789abcdef
+
+
+
+
+ b
+
+
+ 0x0f0f0f0f0f0f0f0f
+
+
+ 0xffff0000ffff0000
+
+
+
+
+ r
+
+
+ 0x02468ace13579bdf
+
+
+ 0x4567cdef012389ab
+
+
+
+
+
+
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vcfuged
+ vec_cfuge
+
+
+
+ Supported type signatures for vec_cfuge
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+
+ vcfuged r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
vec_cipher_be
Vector AES Cipher Big-Endian
@@ -13822,6 +13979,159 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+
+ vec_cntlzm
+ Vector Count Leading Zeros Under Mask
+
+ r = vec_cntlzm (a, b)
+
+
+ Purpose:
+ For each element, returns the number of leading consecutive zero
+ bits in the first argument that correspond to one bits in the
+ second argument.
+
+ Result value:
+ Each element of r is set to the
+ number of consecutive zero bits, starting on the left, in the
+ corresponding element of a that
+ correspond to one bits in the corresponding element of b.
+
+ An example for doubleword inputs follows:
+
+
+
+
+
+
+
+
+
+
+
+ Element 0
+
+
+ Element 1
+
+
+
+
+
+
+ a
+
+
+ 0x0123456789abcdef
+
+
+ 0x0123456789abcdef
+
+
+
+
+ b
+
+
+ 0xaaaaaaaaaaaaaaaa
+
+
+ 0xcccccccccccccccc
+
+
+
+
+ r
+
+
+ 5
+
+
+ 9
+
+
+
+
+
+
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vclzdm
+ vec_cntlzm
+
+
+
+ Supported type signatures for vec_cntlzm
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+
+ vclzdm r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
vec_cnttz
@@ -14529,39 +14839,97 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
-
- vec_cpsgn
- Vector Copy Sign
+
+ vec_cnttzm
+ Vector Count Trailing Zeros Under Mask
- r = vec_cpsgn (a, b)
+ r = vec_cnttzm (a, b)
Purpose:
- Returns a vector by copying the sign of the elements in one
- vector to the sign of the corresponding elements of another
- vector.
+ For each element, returns the number of trailing consecutive
+ zero bits in the first argument that correspond to one bits in
+ the second argument.
Result value:
- The value of each element of r is set
- to the corresponding element of b
- with its sign replaced by the sign from the corresponding element of
- a.
+ Each element of r is set to the
+ number of consecutive zero bits, starting on the right, in the
+ corresponding element of a that
+ correspond to one bits in the corresponding element of b.
+ An example for doubleword inputs follows:
+
+
+
+
+
+
+
+
+
+
+
+ Element 0
+
+
+ Element 1
+
+
+
+
+
+
+ a
+
+
+ 0xfedcba9876543210
+
+
+ 0xfedcba9876543210
+
+
+
+
+ b
+
+
+ 0xaaaaaaaaaaaaaaaa
+
+
+ 0xcccccccccccccccc
+
+
+
+
+ r
+
+
+ 4
+
+
+ 8
+
+
+
+
+
+
+
Endian considerations:
None.
+ Review status:
+ Not yet reviewed.
+
- xvcpsgnsp
- vec_cpsgn
-
-
- xvcpsgndp
- vec_cpsgn
+ vctzdm
+ vec_cnttzm
- Supported type signatures for vec_cpsgn
+ Supported type signatures for vec_cnttzm
@@ -14600,40 +14968,21 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
- vector float
-
-
- vector float
-
-
- vector float
-
-
-
- xvcpsgnsp r,b,a
-
-
-
-
-
-
-
-
- vector double
+ vector unsigned long long
- vector double
+ vector unsigned long long
- vector double
+ vector unsigned long long
- xvcpsgndp r,b,a
+ vctzdm r,a,b
-
+ ISA 3.1 or later
@@ -14643,46 +14992,160 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
-
- vec_ctf
- Vector Convert to Floating-Point
+
+ vec_cpsgn
+ Vector Copy Sign
- r = vec_ctf (a, b)
+ r = vec_cpsgn (a, b)
Purpose:
- Converts an integer vector into a floating-point vector.
+ Returns a vector by copying the sign of the elements in one
+ vector to the sign of the corresponding elements of another
+ vector.
Result value:
- The value of each element of r is the
- closest floating-point approximation of the value of the
- corresponding element of a divided
- by 2 to the power of b, which must
- be in the range 0–31.
+ The value of each element of r is set
+ to the corresponding element of b
+ with its sign replaced by the sign from the corresponding element of
+ a.
Endian considerations:
None.
- Notes:
- The example implementations below assume b is zero, so that the scaling code
- is omitted. Scaling is accomplished by multiplying each
- element of r by 2 to the
- power of –b.
-
- vcfsx
- vec_ctf
+ xvcpsgnsp
+ vec_cpsgn
- vcfux
- vec_ctf
+ xvcpsgndp
+ vec_cpsgn
- Supported type signatures for vec_ctf
-
+ Supported type signatures for vec_cpsgn
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector float
+
+
+ vector float
+
+
+ vector float
+
+
+
+ xvcpsgnsp r,b,a
+
+
+
+
+
+
+
+
+ vector double
+
+
+ vector double
+
+
+ vector double
+
+
+
+ xvcpsgndp r,b,a
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ vec_ctf
+ Vector Convert to Floating-Point
+
+ r = vec_ctf (a, b)
+
+
+ Purpose:
+ Converts an integer vector into a floating-point vector.
+
+ Result value:
+ The value of each element of r is the
+ closest floating-point approximation of the value of the
+ corresponding element of a divided
+ by 2 to the power of b, which must
+ be in the range 0–31.
+
+ Endian considerations:
+ None.
+
+ Notes:
+ The example implementations below assume b is zero, so that the scaling code
+ is omitted. Scaling is accomplished by multiplying each
+ element of r by 2 to the
+ power of –b.
+
+
+
+ vcfsx
+ vec_ctf
+
+
+ vcfux
+ vec_ctf
+
+
+
+ Supported type signatures for vec_ctf
+
@@ -20842,6 +21305,112 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_gnb
+ Vector Gather Nth Bits
+
+ r = vec_gnb (a, b)
+
+
+ Purpose:
+ Copies every Nth bit of the input vector into the leftmost
+ positions of the target value.
+
+ Result value:
+ Let N be the constant value of b. Starting with bit 0, the contents of
+ every Nth bit of a are
+ concatenated and placed in the leftmost bits of r. The remaining bits of r are set to 0.
+
+
+ b must have a value between 2
+ and 7, inclusive.
+
+ As an example, if a has a
+ value of 0x0123456789abcdef0123456789abcdef and b has a value of 4, then r will have a value of
+ 0x00ff00ff00000000.
+
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vgnb
+ vec_gnb
+
+
+
+ Supported type signatures for vec_gnb
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ unsigned long long
+
+
+ vector unsigned __int128
+
+
+ const unsigned int
+
+
+
+ vgnb r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_insert
Vector Insert
@@ -30411,6 +30980,167 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_pdep
+ Vector Parallel Bit Deposit
+
+ r = vec_pdep (a, b)
+
+
+ Purpose:
+ Copies some bits from each element of one argument into
+ positions of the result specified by a mask in a second argument.
+
+ Result value:
+ The rightmost bit of each element of a is copied into the bit position of the
+ corresponding element of r in
+ which the rightmost 1-bit appears in the corresponding element
+ of b. The next-rightmost bit
+ of each element of a is copied
+ into the bit position of the corresponding element of r in which the next-rightmost 1-bit
+ appears in the corresponding element of b; and so forth until the element of
+ b contains no more 1-bits. All
+ bits of the element of r that
+ correspond to 0-bits in the corresponding element of
+ b are set to zero.
+
+ An example for doubleword inputs follows:
+
+
+
+
+
+
+
+
+
+
+
+ Element 0
+
+
+ Element 1
+
+
+
+
+
+
+ a
+
+
+ 0xfedcba9876543210
+
+
+ 0xfedcba9876543210
+
+
+
+
+ b
+
+
+ 0x8888888888888888
+
+
+ 0xcccccccccccccccc
+
+
+
+
+ r
+
+
+ 0x0088 0080 0008 0000
+
+
+ 0x4c 48 44 40 0c 08 04 00
+
+
+
+
+
+
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vpdepd
+ vec_pdep
+
+
+
+ Supported type signatures for vec_pdep
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+
+ vpdepd r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_perm
Vector Permute
@@ -31566,6 +32296,169 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_pext
+ Vector Parallel Bit Extract
+
+ r = vec_pext (a, b)
+
+
+ Purpose:
+ Copies some bits from each element of one argument as specified
+ by a mask in a second argument into the rightmost bits of the
+ result elements.
+
+ Result value:
+ The bit of each element of a,
+ for which the corresponding bit of that element of b is the rightmost bit containing a 1, is
+ copied into the rightmost bit position of the corresponding
+ element of r.
+ The bit of each element of a,
+ for which the corresponding bit of that element of b is the next-rightmost bit containing a
+ 1, is copied into the next-rightmost bit position of the
+ corresponding element of r; and
+ so forth until the element of b
+ contains no more 1-bits. All bits in each element of r that weren't copied from the
+ corresponding element of a are
+ set to zero.
+
+ An example for doubleword inputs follows:
+
+
+
+
+
+
+
+
+
+
+
+ Element 0
+
+
+ Element 1
+
+
+
+
+
+
+ a
+
+
+ 0x0088 0080 0008 0000
+
+
+ 0x4c 48 44 40 0c 08 04 00
+
+
+
+
+ b
+
+
+ 0x8888888888888888
+
+
+ 0xcccccccccccccccc
+
+
+
+
+ r
+
+
+ 0x0000000000003210
+
+
+ 0x0000000076543210
+
+
+
+
+
+
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ vpextd
+ vec_pext
+
+
+
+ Supported type signatures for vec_pext
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+
+ vpextd r,a,b
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_pmsum_be
Vector Polynomial Multiply-Sum Big-Endian
@@ -43537,6 +44430,235 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
+
+ vec_ternary_logic
+ Vector Ternary Logic
+
+ r = vec_ternary_logic (a, b, c, d)
+
+
+ Purpose:
+ Perform one of 256 logical operations on three input vectors to
+ produce the output vector.
+
+ Result value:
+ For each integer value i from 0 to 127, do
+ the following. Let j be the value of the
+ concatenation of the contents of bit i of
+ a, b, and c. The value of bit
+ j of the 8-bit value in d is placed into bit
+ i of r.
+
+
+ d must have a value between 0
+ and 255, inclusive.
+
+
+ The effect of this operation is to perform one of 256 logical
+ functions on the input arguments to produce the result. The
+ full set of logical functions is documented with the
+ xxeval
instruction in the Power Instruction Set
+ Architecture, Version 3.1B Specification (see ).
+
+
+ Endian considerations:
+ None.
+
+ Review status:
+ Not yet reviewed.
+
+
+
+ xxeval
+ vec_ternary_logic
+
+
+
+ Supported type signatures for vec_ternary_logic
+
+
+
+
+
+
+
+
+
+
+
+
+ r
+
+
+
+
+ a
+
+
+
+
+ b
+
+
+
+
+ c
+
+
+
+
+ d
+
+
+
+
+ Example Implementation
+
+
+
+
+ Restrictions
+
+
+
+
+
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ vector unsigned char
+
+
+ const unsigned int
+
+
+
+ xxeval r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ vector unsigned short
+
+
+ const unsigned int
+
+
+
+ xxeval r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ vector unsigned int
+
+
+ const unsigned int
+
+
+
+ xxeval r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ vector unsigned long long
+
+
+ const unsigned int
+
+
+
+ xxeval r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ vector unsigned __int128
+
+
+ const unsigned int
+
+
+
+ xxeval r,a,b,c,d
+
+
+
+ ISA 3.1 or later
+
+
+
+
+
+
+
+
+
vec_test_data_class
Vector Test Data Class