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27 Commits
v2 ... master

Author SHA1 Message Date
Bill Schmidt 64ee3d30c4 More updates, and prepare for external draft submission. 3 years ago
Bill Schmidt 03b142e07a Address a few review comments from Will Schmidt. 3 years ago
Bill Schmidt 49e3ac00e5 Various updates 3 years ago
Bill Schmidt c8feea2569 Many more P10 updates 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 16a91014e0 Fix up cross-reference to Fortran data types table. 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 06943c54cc Add missing MMA instructions 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 446b6227cf Fix issue #74 problems with vec_cpsgn 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt d61bb0f96a Fix issue #75 with vec_round 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 81e159f662 Comply with latest branding guidelines 
Also includes a few fixes for comments from Paul Clarke.

Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 321ac9e713 Incorporate changes following Paul Clarke's admirable review 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt ae4cd5ccc6 Publish the PVIPR Errara; corrections to PVIPR 2.0 draft 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt c5fee541fb Add vec_stri[lr]_p 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt c51f95c61b Miscellaneous updates 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt f766c63456 Update endian-sensitive builtins table 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt dd66bbd6c0 Introduce "build" interfaces for MMA 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt b1151856bb Fix issue #66 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt bce1abd913 Fix issue #72 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt c62808ced9 Address issue #70 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 469f5267c5 Cleanups; also address issue #64. 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt f821556104 Add MMA chapter 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt a1b4a3c084 Finish first draft of V3.1 builtins added to chapter 4. 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt fd3dfb21e2 Document built-ins for RFC 2613. 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 98c2d19534 Completed draft work for RFC 2608 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 2fb400dd56 Partial implementation of RFC 2608, not yet reviewed 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 5f420b5f84 Partial implementation of RFC 2608, not yet reviewed 
Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
 3 years ago
Bill Schmidt 8c875503ea Merge branch 'v2' 
The v2 branch was used to work on PVIPR v2.0 while PVIPR v1.0 was
still under review.  Since PVIPR 1.0 has now been published, and a
separate document will be used for v1.0 errata, merge v2 into mainline
and use mainline for further updates.
 3 years ago
Toshaan Bharvani a74d7d2571 change the contact to the generic tsc chair email 
Signed-off-by: Toshaan Bharvani <toshaan@vantosh.com>
 3 years ago
9 changed files with 13985 additions and 973 deletions
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7
Intrinsics_Reference/bk_main.xml
Unescape Escape View File

@ -54,7 +54,7 @@
<holder>OpenPOWER Foundation</holder>
</copyright>
<!-- TODO: Set the correct document releaseinfo -->
<releaseinfo>Revision 2.0.0</releaseinfo>
<releaseinfo>Revision 2.0.0_prd</releaseinfo>
<productname>OpenPOWER</productname>
<pubdate/>

@ -88,11 +88,11 @@
<revhistory>
<!-- TODO: Set the initial version information and clear any old information out -->
<revision>
<date>2020-10-05</date>
<date>2021-09-08</date>
<revdescription>
<itemizedlist spacing="compact">
<listitem>
<para>Version 2.0_pre pre-review draft</para>
<para>Version 2.0.0_prd public review draft</para>
</listitem>
</itemizedlist>
</revdescription>
@ -121,6 +121,7 @@
<xi:include href="ch_techniques.xml"/>
<xi:include href="ch_vec_reference.xml"/>
<!-- xi:include href="ch_scal_reference.xml"/ -->
<xi:include href="ch_mma_reference.xml"/>
<xi:include href="ch_isa_intrin_xref.xml"/>
<!-- xi:include href="app_a.xml"/ -->


298
Intrinsics_Reference/ch_biendian.xml
Unescape Escape View File

@ -151,8 +151,8 @@ vector unsigned __int128 x = { (((unsigned __int128)0x1020304050607080) &lt;&lt;
it.
</para>
<para>
For the Fortran language, <xref
linkend="VIPR.biendian.fortran-types" /> gives a correspondence
For the Fortran language, <phrase revisionflag="changed"><xref
linkend="VIPR.biendian.fortrantypes" /></phrase> gives a correspondence
between Fortran and C/C++ language types.
</para>
<para>
@ -787,10 +787,6 @@ a[3] = c;</programlisting>
thus are not "endian-sensitive." A complete list of
endian-sensitive built-in functions can be found in <xref
linkend="VIPR.biendian.sensitive" />.
</para>
<para revisionflag="added">
Be sure to update this table for any new endian-sensitive
built-ins added for P10.
</para>
<table frame="all" pgwide="1" xml:id="VIPR.biendian.sensitive">
<title>Endian-Sensitive Built-In Functions</title>
@ -804,10 +800,16 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_bperm" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mergeh" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_inserth"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_signedo" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_signextll"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
@ -815,10 +817,16 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_cipher_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mergel" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_insertl"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_sld" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_signextq"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
@ -826,7 +834,38 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_cipherlast_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mergeo" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_mergee" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sld" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_clr_first"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_mergeh" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_sldb" xrefstyle="select:title
nopage"/></code>
</para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_clr_last"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_mergel" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sldw" xrefstyle="select:title nopage"/></code></para>
@ -837,7 +876,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doublee" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mfvscr" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_mergeo" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sll" xrefstyle="select:title nopage"/></code></para>
@ -848,7 +887,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doubleh" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mule" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_mfvscr" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_slo" xrefstyle="select:title nopage"/></code></para>
@ -859,7 +898,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doublel" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mulo" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_mule" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_slv" xrefstyle="select:title nopage"/></code></para>
@ -870,7 +909,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doubleo" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_ncipher_be" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_mulo" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_splat" xrefstyle="select:title nopage"/></code></para>
@ -881,10 +920,13 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_ncipherlast_be" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_ncipher_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_srl" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_splati_ins"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
@ -892,10 +934,13 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract_fp32_from_shorth" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_pack" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_ncipherlast_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sro" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_srdb" xrefstyle="select:title
nopage"/></code>
</para>
</entry>
</row>
<row>
@ -903,10 +948,10 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract_fp32_from_shortl" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_pack_to_short_fp32" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_pack" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_srv" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_srl" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
@ -914,122 +959,234 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract4b" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_packpx" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_pack_to_short_fp32" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sum2s" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_sro" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_first_match_index" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_extracth"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_packs" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_packpx" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sums" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_srv" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_first_match_or_eos_index" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_extractl"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_packsu" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_packs" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unpackh" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_stril"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_first_mismatch_index" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_first_match_index" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_perm" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_packsu" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unpackl" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_stril_p"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_first_mismatch_or_eos_index" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_first_match_or_eos_index" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_permxor" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_perm" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unsigned2" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_strir"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_float2" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_first_mismatch_index" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_pmsum_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unsignede" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_permx"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_strir_p"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_floate" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_reve" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_first_mismatch_or_eos_index" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unsignedo" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_permxor" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sum2s" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_floato" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sbox_be" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_float2" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_xl" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
<para><code><xref linkend="vec_pmsum_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_sums" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_insert" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_floate" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_shasigma_be" xrefstyle="select:title nopage"/></code></para>
<para revisionflag="added">
<code><xref linkend="vec_replace_elt"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_xl_be" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_unpackh"
xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_insert4b" xrefstyle="select:title nopage"/></code></para>
</entry>
<row>
<entry>
<para><code><xref linkend="vec_floato" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_replace_unaligned"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_signed2" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_unpackl" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_genbm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_reve" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_xst" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
<para><code><xref linkend="vec_unsigned2" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_gendm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_sbox_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mergee" xrefstyle="select:title nopage"/></code></para>
<para><code><xref linkend="vec_unsignede" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_genhm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_shasigma_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unsignedo" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_genpcvm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_signed2" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_xl" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_genwm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_signede" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
</entry>
<entry>
<para><code><xref linkend="vec_xl_be" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_insert" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_signedo" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_xst" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_insert4b" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_signexti"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_xst_be" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
</entry>
</row>
</tbody>
</tgroup>
</table>
@ -1183,13 +1340,14 @@ a[3] = c;</programlisting>
introduced serious compiler complexity without much utility.
Thus this support (previously controlled by switches
<code>-maltivec=be</code> and/or <code>-qaltivec=be</code>) is
now deprecated. Current versions of the GCC and Clang
open-source compilers do not implement this support.
now deprecated. Current versions of the <phrase
revisionflag="changed">GCC, Clang, and Open XL</phrase>
compilers do not implement this support.
</para>
</section>
</section>

<section>
<section revisionflag="deleted">
<title>Language-Specific Vector Support for Other
Languages</title>
<section>

79
Intrinsics_Reference/ch_intro.xml
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@ -23,13 +23,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
<section>
<title>A Brief History</title>
<para>
The history of vector programming on Power processors begins
The history of vector programming on <phrase
revisionflag="changed"><trademark
class="registered">Power</trademark></phrase> processors begins
with the AIM (Apple, IBM, Motorola) alliance in the 1990s. The
AIM partners developed the Power Vector Media Extension (VMX) to
accelerate multimedia applications, particularly image
processing. VMX is the name still used by IBM for this
instruction set. Freescale (formerly Motorola) used the
trademark "AltiVec," while Apple at one time called it "Velocity
trademark <phrase revisionflag="changed"><trademark
class="trade">AltiVec</trademark>,</phrase> while Apple at one
time called it "Velocity
Engine." While VMX remains the most official name, the term
AltiVec is still in common use today. Freescale's AltiVec
Technology Programming Interface Manual (the "AltiVec PIM") is
@ -68,11 +72,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
also included AltiVec support, and was used in the Apple
PowerMac G5. IBM initially omitted support for VMX from its
server-class computers, but added support for it in the POWER6
server family.
<phrase revisionflag="added">processor-based</phrase> server
family.
</para>
<para>
IBM extended VMX by introducing the Vector-Scalar Extension
(VSX) for the POWER7 family of processors. VSX adds sixty-four
(VSX) for the <phrase revisionflag="changed"><trademark
class="registered">POWER7</trademark></phrase> family of
processors. VSX adds sixty-four
128-bit vector-scalar registers (VSRs); however, to optimize the amount
of per-process register state, the registers overlap with the
VRs and the scalar floating-point registers (FPRs) (see <xref
@ -80,13 +87,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
the data types representable by the VRs, and can also be treated
as containing two 64-bit integers or two 64-bit double-precision
floating-point values. However, ISA support for two 64-bit
integers in VSRs was limited until Version 2.07 (POWER8) of the
integers in VSRs was limited until Version 2.07 (<phrase
revisionflag="changed"><trademark
class="registered">POWER8</trademark></phrase>) of the
Power ISA, and only the VRs are supported for these
instructions.
</para>
<para>
Both the VMX and VSX instruction sets have been expanded for the
POWER8 and POWER9 processor families. Starting with POWER8,
<phrase revisionflag="changed">POWER8, <trademark
class="registered">POWER9</trademark>, and <trademark
class="registered">Power10</trademark></phrase> processor
families. Starting with POWER8,
a VSR can now contain a single 128-bit integer; and starting
with POWER9, a VSR can contain a single 128-bit IEEE floating-point
value. Again, the ISA currently only supports 128-bit
@ -97,17 +109,16 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
the Power SIMD (single-instruction, multiple-data)
instructions.
</para>
<para revisionflag="added">
Write an introductory paragraph about the MMA facility and the
ACC registers.
</para>
<section>
<title>Little-Endian Linux</title>
<para>
The Power architecture has supported operation in either
big-endian (BE) or little-endian (LE) mode from the
beginning. However, IBM's Power servers were only shipped
with big-endian operating systems (AIX, Linux, i5/OS) prior to
with big-endian operating systems (<phrase
revisionflag="changed"><trademark
class="registered">AIX</trademark>, IBM i, <trademark
class="registered">Linux</trademark></phrase>) prior to
the introduction of POWER8. With POWER8, IBM began
supporting little-endian Linux distributions for the first
time, and introduced a new application binary interface (the
@ -139,7 +150,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
<section xml:id="VIPR.intro.unified">
<title>The Unified Vector Register Set</title>
<para>
In OpenPOWER-compliant processors, floating-point and vector
In <phrase revisionflag="changed"><trademark
class="trade">OpenPOWER</trademark>-compliant</phrase>
processors, floating-point and vector
operations are implemented using a unified vector-scalar model.
As shown in <xref linkend="FPR-VSR" /> and <xref
linkend="VR-VSR" />, there are 64 vector-scalar registers; each
@ -205,11 +218,15 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
</listitem>
<listitem>
<para>
<emphasis role="underline">The XL compilers</emphasis>. For
XL compilers provided with the Linux Community Edition, you
can provide feedback to the XL compiler team via email
<emphasis role="underline">The XL <phrase
revisionflag="added">and Open XL</phrase>
compilers</emphasis>. For XL <phrase
revisionflag="added">and Open XL</phrase> compilers provided
with the Linux Community Edition, you can provide feedback
to the XL compiler team via email
(<email>compinfo@cn.ibm.com</email>); for other editions of
XL compilers, please open a <link
XL <phrase revisionflag="added">and Open XL</phrase>
compilers, please open a <link
xlink:href="https://www.ibm.com/mysupport/s/">Case</link>.
</para>
</listitem>
@ -291,7 +308,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
</listitem>
<listitem revisionflag="added">
<para>
<emphasis>POWER10 Processor User's Manual.</emphasis>
<emphasis>Power10 Processor User's Manual.</emphasis>
<emphasis>
<link
xlink:href="https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k">Not
@ -339,9 +356,37 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
</emphasis>
</para>
</listitem>
<listitem revisionflag="added">
<para>
<emphasis>The GNU C Library Project.</emphasis>
<emphasis>
<link xlink:href="https://www.gnu.org/software/libc">https://www.gnu.org/software/libc</link>
</emphasis>
</para>
</listitem>
<listitem revisionflag="added">
<para>
<emphasis>Matrix-Multiply Assist Best Practices Guide.</emphasis>
<emphasis>
<link xlink:href="http://www.redbooks.ibm.com/redpapers/pdfs/redp5612.pdf">https://www.redbooks.ibm.com/redpapers/pdfs/redp5612.pdf</link>
</emphasis>
</para>
</listitem>
</itemizedlist>
</section>

<section xml:id="VIPR.intro.marks" revisionflag="added">
<title>Trademarks</title>
<para>
AIX, POWER7, POWER8, POWER9, and Power10 are trademarks or
registered trademarks of International Business Machines
Corporation. Linux is a registered trademark of Linus
Torvalds. Intel is a registered trademark of Intel Corporation
or its subsidiaries. AltiVec is a trademark of Freescale
Semiconductor, Inc.
</para>
</section>

<section xml:id="VIPR.intro.conf">
<title>Conformance to this Specification</title>
<orderedlist>

1364
Intrinsics_Reference/ch_mma_reference.xml
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36
Intrinsics_Reference/ch_techniques.xml
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@ -113,9 +113,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
references. (<code>restrict</code> can be used only in C
when compiling for the C99 standard or later.
<code>__restrict__</code> is a language extension, available
in GCC, Clang, and the XL compilers, that can be used
without restriction for both C and C++. See your compiler's
user manual for details.)
in GCC, Clang, and the XL <phrase revisionflag="added">and
Open XL</phrase> compilers, that can be used without
restriction for both C and C++. See your compiler's user
manual for details.)
</para>
<para>
Suppose you have a function that takes two pointer
@ -142,8 +143,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
</para>
<para>
This reference provides intrinsics that are guaranteed to be
portable across compliant compilers. In particular, both the
GCC and Clang compilers for Power implement the intrinsics in
portable across compliant compilers. In particular, the <phrase
revisionflag="changed">GCC, Clang, and Open XL</phrase>
compilers for Power implement the intrinsics in
this manual. The compilers may each implement many more
intrinsics, but the ones in this manual are the only ones
guaranteed to be portable. So if you are using an interface not
@ -204,10 +206,15 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
responsible for following the calling conventions established by
the ABI (see <xref linkend="VIPR.intro.links" />). Again, it is
best to look at examples. One place to find well-written
<code>.S</code> files is in the GLIBC project. You can also
<code>.S</code> files is in the <phrase
revisionflag="changed">GNU C Library project (see <xref
linkend="VIPR.intro.links" />).</phrase> You can also
study the assembly output from your favorite compiler, which can
be obtained with the <code>-S</code> or similar option, or by
using the <emphasis role="bold">objdump</emphasis> utility.
using the <emphasis role="bold">objdump</emphasis> utility:
</para>
<para revisionflag="added">
<programlisting> objdump -dr &lt;binary or object file&gt;</programlisting>
</para>
</section>

@ -219,9 +226,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
<section>
<title>x86 Vector Portability Headers</title>
<para>
Recent versions of the GCC and Clang open-source compilers
Recent versions of the <phrase revisionflag="changed">GCC,
Clang, and Open XL</phrase> compilers
for Power provide "drop-in" portability headers for portions
of the Intel Architecture Instruction Set Extensions (see <xref
of the <phrase revisionflag="changed"><trademark
class="registered">Intel</trademark></phrase> Architecture
Instruction Set Extensions (see <xref
linkend="VIPR.intro.links" />). These headers mirror the APIs
of Intel headers having the same names. As of this writing,
support is provided for the MMX and SSE layers, up through
@ -243,14 +253,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
<para>
Access to the portability APIs occurs automatically when
including one of the corresponding Intel header files, such as
<code>&lt;mmintrin.h&gt;</code>.
<code>&lt;mmintrin.h&gt;</code>. <phrase
revisionflag="added">To enable the portability headers, you
must compile with
<code>-DNO_WARN_X86_INTRINSICS</code>.</phrase>
</para>
</section>
<section xml:id="VIPR.techniques.pveclib">
<title>The Power Vector Library (pveclib)</title>
<para>The Power Vector Library, also known as
<code>pveclib</code>, is a separate project available from
github (see <xref linkend="VIPR.intro.links" />). The
<phrase revisionflag="changed">GitHub</phrase> (see <xref
linkend="VIPR.intro.links" />). The
<code>pveclib</code> project builds on top of the intrinsics
described in this manual to provide higher-level vector
interfaces that are highly portable. The goals of the project

13159
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3
README.md
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@ -37,8 +37,7 @@ This can be accomplished with the following steps:
The project which controls the look and feel of the document is the
[Docs-Maven-Plugin project](https://github.com/OpenPOWERFoundation/Docs-Maven-Plugin), an
OpenPOWER Foundation private project on GitHub. To obtain access to the Maven Plugin project,
contact Jeff Scheel \([scheel@us.ibm.com](mailto://scheel@us.ibm.com)\) or
Jeff Brown \([jeffdb@us.ibm.com](mailto://jeffdb@us.ibm.com)\).
contact TSC Chair of the OpenPOWER Foundation \([tsc-chair@openpowerfoundation.org](mailto://tsc-chair@openpowerfoundation.org)\) or

## License
This project is licensed under the Apache V2 license. More information

4
pvipr-errata-1.0/bk_main.xml
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@ -82,11 +82,11 @@
<revhistory>
<!-- TODO: Set the initial version information and clear any old information out -->
<revision>
<date>2021-04-07</date>
<date>2021-06-09</date>
<revdescription>
<itemizedlist spacing="compact">
<listitem>
<para>Initial draft</para>
<para>Revision 1.0</para>
</listitem>
</itemizedlist>
</revdescription>

8
pvipr-errata-1.0/pom.xml
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@ -112,9 +112,9 @@
other Foundation members or the public

The appropriate starting security for a new document is "workgroupConfidential". -->
<security>workgroupConfidential</security>
<!-- security>workgroupConfidential</security -->
<!-- security>foundationConfidential</security -->
<!-- security>public</security -->
<security>public</security>

<!-- TODO: Set the appropriate work flow status for the document. For documents
which are not "published" this will affect the document title page
@ -129,9 +129,9 @@
review = this document is presently being reviewed

The appropriate starting security for a new document is "draft". -->
<documentStatus>draft</documentStatus>
<!-- documentStatus>draft</documentStatus -->
<!-- documentStatus>review</documentStatus -->
<!-- documentStatus>published</documentStatus -->
<documentStatus>published</documentStatus>
</configuration>
</execution>
</executions>

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