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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2017 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<section xmlns="http://docbook.org/ns/docbook"
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xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink"
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version="5.0"
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xml:id="sec_handling_avx">
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<title>Dealing with AVX and AVX512</title>
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<para>AVX is a bit easier for PowerISA and the ELF V2 ABI. First we have
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lots (64) of vector registers and a superscalar vector pipeline (can execute
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two or more independent 128-bit vector operations concurrently). Second the ELF
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V2 ABI was designed to pass and return larger aggregates in vector
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registers:</para>
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<itemizedlist>
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<listitem>
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<para>Up to 12 qualified vector arguments can be passed in
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v2–v13.</para>
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</listitem>
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<listitem>
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<para>A qualified vector argument corresponds to:
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<itemizedlist spacing="compact">
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<listitem>
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<para>A vector data type</para>
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</listitem>
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<listitem>
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<para>A member of a homogeneous aggregate of multiple like data types
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passed in up to eight vector registers.</para>
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</listitem>
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<listitem>
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<para>Homogeneous floating-point or vector aggregate return values
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that consist of up to eight registers with up to eight elements will
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be returned in floating-point or vector registers that correspond to
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the parameter registers that would be used if the return value type
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were the first input parameter to a function.</para>
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</listitem>
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</itemizedlist>
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</para>
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</listitem>
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</itemizedlist>
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<para>So the ABI allows for passing up to three structures each
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representing 512-bit vectors and returning such (512-bit) structures all in VMX
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registers. This can be extended further by spilling parameters (beyond 12 X
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128-bit vectors) to the parameter save area, but we should not need that, as
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most intrinsics only use 2 or 3 operands.. Vector registers not needed for
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parameter passing, along with an additional 8 volatile vector registers, are
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available for scratch and local variables. All can be used by the application
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without requiring register spill to the save area. So most intrinsic operations
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on 256- or 512-bit vectors can be held within existing PowerISA vector
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registers. </para>
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<para>For larger functions that might use multiple AVX 256 or 512-bit
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intrinsics and, as a result, push beyond the 20 volatile vector registers, the
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compiler will just allocate non-volatile vector registers by allocating a stack
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frame and spilling non-volatile vector registers to the save area (as needed in
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the function prologue). This frees up to 64 vectors (32 x 256-bit or 16 x
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512-bit structs) for code optimization. </para>
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<para>Based on the specifics of our ISA and ABI we will not not use
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<literal>__vector_size__</literal> (32) or (64) in the PowerPC implementation of
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<literal>__m256</literal> and <literal>__m512</literal>
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types. Instead we will typedef structs of 2 or 4 vector (<literal>__m128</literal>) fields. This
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allows efficient handling of these larger data types without requiring new GCC
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language extensions. </para>
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<para>In the end we should use the same type names and definitions as the
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GCC X86 intrinsic headers where possible. Where that is not possible we can
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define new typedefs that provide the best mapping to the underlying PowerISA
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hardware.</para>
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</section>
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