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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2017 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<section xmlns="http://docbook.org/ns/docbook"
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xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink"
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version="5.0"
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xml:id="sec_other_intrinsic_examples">
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<title>Examples implemented using other intrinsics</title>
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<para>Some intrinsic implementations are defined in terms of other
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intrinsics. For example.
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<programlisting><![CDATA[/* Create a vector with element [0] as F and the rest zero. */
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extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_set_sd (double __F)
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{
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return __extension__ (__m128d){ __F, 0.0 };
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}
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/* Create a vector with element [0] as *P and the rest zero. */
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extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_load_sd (double const *__P)
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{
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return _mm_set_sd (*__P);
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}]]></programlisting></para>
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<para>This notion of using part (one fourth or half) of the SSE XMM
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register and leaving the rest unchanged (or forced to zero) is specific to SSE
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scalar operations and can generate some complicated (sub-optimal) PowerISA
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code. In this case <emphasis role="bold"><literal>_mm_load_sd</literal></emphasis>
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passes the dereferenced double value to
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<emphasis role="bold"><literal>_mm_set_sd</literal></emphasis> which
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uses C vector initializer notation to combine (merge) that
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double scalar value with a scalar 0.0 constant into a vector double.</para>
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<para>While code like this should work as-is for PPC64LE, you should look
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at the generated code and assess if it is reasonable. In this case the code
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is not awful (a load double splat, vector xor to generate 0.0s, then a
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<literal>xxmrghd</literal>
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to combine __F and 0.0). Other examples may generate sub-optimal code and
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justify a rewrite to PowerISA scalar or vector code (<link
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xlink:href="https://gcc.gnu.org/onlinedocs/gcc-6.3.0/gcc/PowerPC-AltiVec_002fVSX-Built-
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in-Functions.html#PowerPC-AltiVec_002fVSX-Built-in-Functions">
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<emphasis role="italic">GCC PowerPC AltiVec Built-in Functions</emphasis></link>
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or inline assembler). </para>
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<note><para>Try using the existing C code if you can, but check on what the
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compiler generates. If the generated code is horrendous, it may be worth the
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effort to write a PowerISA specific equivalent. For codes making extensive use
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of MMX or SSE scalar intrinsics you will be better off rewriting to use
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standard C scalar types and letting the GCC compiler handle the details
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(see <xref linkend="sec_prefered_methods"/>).</para></note>
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</section>
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