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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2017 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<section xmlns="http://docbook.org/ns/docbook"
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xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink"
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version="5.0"
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xml:id="sec_handling_mmx">
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<title>Dealing with MMX</title>
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<para>MMX is actually the harder case. The <literal>__m64</literal>
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type supports SIMD vector
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int types (char, short, int, long). The Intel API defines
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<literal>__m64</literal> as:
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<programlisting><![CDATA[typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));]]></programlisting></para>
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<para>Which is problematic for the PowerPC target (not really supported in
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GCC) and we would prefer to use a native PowerISA type that can be passed in a
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single register. The PowerISA Rotate Under Mask instructions can easily
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extract and insert integer fields of a General Purpose Register (GPR). This
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implies that MMX integer types can be handled as an internal union of arrays for
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the supported element types. So a 64-bit unsigned long long is the best type
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for parameter passing and return values, especially for the 64-bit (_si64)
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operations as these normally generate a single PowerISA instruction.
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So for the PowerPC implementation we will define
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<literal>__m64</literal> as:
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<programlisting><![CDATA[typedef __attribute__ ((__aligned__ (8))) unsigned long long __m64;]]></programlisting></para>
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<para>The SSE extensions include some copy / convert operations for
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<literal>_m128</literal> to /
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from <literal>_m64</literal> and this includes some int to / from float conversions. However in
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these cases the float operands always reside in SSE (XMM) registers (which
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match the PowerISA vector registers) and the MMX registers only contain integer
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values. POWER8 (PowerISA-2.07) has direct move instructions between GPRs and
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VSRs. So these transfers are normally a single instruction and any conversions
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can be handled in the vector unit.</para>
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<para>When transferring a <literal>__m64</literal> value to a vector register we should also
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execute a xxsplatd instruction to insure there is valid data in all four
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float element lanes before doing floating point operations. This avoids causing
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extraneous floating point exceptions that might be generated by uninitialized
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parts of the vector. The top two lanes will have the floating point results
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that are in position for direct transfer to a GPR or stored via Store Float
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Double (stfd). These operation are internal to the intrinsic implementation and
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there is no requirement to keep temporary vectors in correct Little Endian
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form.</para>
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<para>Also for the smaller element sizes and higher element counts (MMX
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<literal>_pi8</literal> and <literal>_p16</literal> types)
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the number of Rotate Under Mask instructions required to
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disassemble the 64-bit <literal>__m64</literal>
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into elements, perform the element calculations,
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and reassemble the elements in a single <literal>__m64</literal>
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value can get larger. In this
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case we can generate shorter instruction sequences by transfering (via direct
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move instruction) the GPR <literal>__m64</literal> value to the
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a vector register, performance the
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SIMD operation there, then transfer the <literal>__m64</literal>
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result back to a GPR.</para>
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</section>
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