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<?xml version="1.0" encoding="UTF-8"?> |
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<!-- |
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Copyright (c) 2017 OpenPOWER Foundation |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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http://www.apache.org/licenses/LICENSE-2.0 |
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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--> |
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<section xmlns="http://docbook.org/ns/docbook" |
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xmlns:xi="http://www.w3.org/2001/XInclude" |
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xmlns:xlink="http://www.w3.org/1999/xlink" |
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version="5.0" |
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xml:id="sec_floatingpoint_exceptions"> |
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<title>Floating Point Exceptions</title> |
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<para>Nominally both ISAs support the IEEE-754 specifications, but there are |
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some subtle differences. Both architectures define a status and control register |
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to record exceptions and enable / disable floating point exceptions for program |
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interrupt or default action. Intel has a MXCSR and PowerISA has a FPSCR which |
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basically do the same thing but with different bit layout. </para> |
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<para>Intel provides <literal>_mm_setcsr</literal> / <literal>_mm_getcsr</literal> |
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intrinsic functions to allow direct access to the MXCSR. |
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This might have been useful in the early days before the OS run-times were |
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updated to manage the MXCSR via the POSIX APIs. Today this would be |
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highly discouraged with a strong preference to use the POSIX APIs |
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(<literal>feclearexceptflag</literal>, |
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<literal>fegetexceptflag</literal>, |
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<literal>fesetexceptflag</literal>, ...) instead.</para> |
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<para>If we implement <literal>_mm_setcsr</literal> / |
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<literal>_mm_getcs</literal> at all, we should simply |
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redirect the implementation to use the POSIX APIs from |
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<literal><fenv.h></literal>. But it |
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might be simpler just to replace these intrinsics with macros that generate |
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#error.</para> |
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<para>The Intel MXCSR does have some non- (POSIX/IEEE754) standard quirks: |
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The Flush-To-Zero and Denormals-Are-Zeros flags. This simplifies the hardware |
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response to what should be a rare condition (underflows where the result can |
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not be represented in the exponent range and precision of the format) by simply |
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returning a signed 0.0 value. The intrinsic header implementation does provide |
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constant masks for <literal>_MM_DENORMALS_ZERO_ON</literal> |
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(<literal><pmmintrin.h></literal>) and |
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<literal>_MM_FLUSH_ZERO_ON</literal> (<literal><xmmintrin.h></literal>), |
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so technically it is available to users |
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of the Intel Intrinsics API.</para> |
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<para>The VMX Vector facility provides a separate Vector Status and Control |
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register (VSCR) with a Non-Java Mode control bit. This control combines the |
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flush-to-zero semantics for floating point underflow and denormal values. But |
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this control only applies to VMX vector float instructions and does not apply |
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to VSX scalar floating Point or vector double instructions. The FPSCR does |
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define a Floating-Point non-IEEE mode which is optional in the architecture. |
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This would apply to Scalar and VSX floating-point operations if it were |
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implemented. This was largely intended for embedded processors and is not |
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implemented in the POWER processor line.</para> |
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<para>As the flush-to-zero is primarily a performance enhancement and is |
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clearly outside the IEEE-754 standard, it may be best to simply ignore this |
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option for the intrinsic port.</para> |
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</section> |
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