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+© IBM Corp. 2020
+Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
+repository except in compliance with the License as modified.
+You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+
+Modified Terms:
+
+   1)	For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
+   the work of authorship in physical form.
+
+   2)	Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
+   from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
+   under the terms and conditions of the EULA.  
+
+Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
+"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
+governing permissions and limitations under the License.
+
+Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
+ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
+ISA) here: https://openpowerfoundation.org. 
+
+Brief explanation of modifications:
+
+Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
+it unambiguously permits a user to make and use the physical chip.  
+
+Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
+and not under this license.  To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
+licensed consistent with the terms of the Power ISA EULA.  By ensuring that rights available via the Power ISA EULA are received
+under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
+licenses for the specific Power ISA Core are granted under this modified Apache license.  
+
--- a/README.md
+++ b/README.md
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+![](https://github.com/openpower-cores/a2i/workflows/VUnit%20Tests/badge.svg)
+
+# A2I
+
+## The Project
+Release of the A2I POWER processor core RTL and associated FPGA implementation (used ADM-PCIE-9V3 FPGA)
+
+See [Project Info](rel/readme.md) for details.
+
+## The Core
+The [A2I core](rel/doc/A2_BGQ.pdf) was created as a high-frequency four-threaded design, optimized for throughput and targeted for 3+ GHz in 45nm technology.
+
+It is a 27 FO4 implementation, with an in-order pipeline supporting 1-4 threads.  It fully supports Power ISA 2.06 using Book III-E.  The core was also designed to support pluggable implementations of MMU and AXU logic macros.  This includes elimination of the MMU and using ERAT-only mode for translation/protection.
+
+## The History
+
+The [A2I platform](rel/doc/a2_1.png) was developed following IBM's game core designs.  It was designed to balance performance and power and provide high streaming throughput.  It supported chip, sim, and FPGA implementations through the use of a configurable latch/array library.
+
+A2I was developed as the "wire-speed processor" for a high-throughput edge-of-network (PowerEN) [SoC design](rel/doc/w_2.png).  This [chip](rel/doc/w_1.png) included four L2's with four A2I per L2, connected through an interconnect called PBus.  The units outside the core included multiple accelerators attached to the PBus.  External interfaces included DDR3, PCI Gen2, and Ethernet.  The chip was built and performed at ~2.3GHz (the core was throttled for power savings), but was not released.
+
+The A2I core was then selected as the general purpose processor for [BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers](https://www.ibm.com/ibm/history/ibm100/us/en/icons/bluegene).  In this [design](rel/doc/HC23.18.121.BlueGene-IBM_BQC_HC23_20110818.pdf), eighteen A2I cores were included on one chip, along with cache and memory controllers, and internal networking components.  The design ran at 1.6 GHz, to meet power/performance goals, and included a special-purpose AXU (high-bandwidth FPU).  Multiple BlueGene/Q installations have been ranked in the top 10 of the TOP500 list for many years
+([#1,#3,#7,#8 in 2012](https://www.top500.org/lists/2012/06/)), and
+[three](https://www.top500.org/lists/top500/2020/06/)
+are still ranked in the TOP500 as of June 2020.
+
+## The Future
+
+There may be uses for this core where a full feature-set is needed, and its limitations can be overcome by the intended environment.  Specifically, single-thread performance is limited by the in-order implementation, requiring a well-behaved application set to enable efficient use of the pipeline to cover pipeline dependencies, branch misprediction, etc.
+
+The design of the A2L2 interface (core-to-L2/nest) is straightforward, and offers multiple configurable options for data interfacing.  There is also some configurability for handling certain Power-specific features (core vs. L2).
+
+The ability to add an AXU that is tightly-coupled to the core enables many possibilities for special-purpose designs, like an open distributed Web 3.0 hardware/software system integrating streaming encryption, blockchain, semantic query, etc.
+
+### Technology Scaling
+
+A comparison of the design in original technology and scaled to 7nm (fixed-point, no MMU):
+
+|      |Freq     |Pwr    |Freq Sort|Pwr Sort|Area     |Vdd    |
+|-----:|---------|-------|---------|--------|---------|-------|
+|45nm  |2.30 GHz |0.88 W |         |        |2.90 mm<sup>2</sup> |0.97 V |
+| 7nm  |3.90 GHz |0.44 W |4.17 GHz |0.47 W  |0.17 mm<sup>2</sup> |1.1  V |
+| 7nm  |3.75 GHz |0.35 W |4.03 GHz |0.37 W  |0.17 mm<sup>2</sup> |1.0  V |
+| 7nm  |3.55 GHz |0.27 W |3.87 GHz |0.29 W  |0.17 mm<sup>2</sup> |0.9  V |
+| 7nm  |3.07 GHz |0.18 W |3.60 GHz |0.21 W  |0.17 mm<sup>2</sup> |0.8  V |
+| 7nm  |2.40 GHz |0.08 W |3.00 GHz |0.14 W  |0.17 mm<sup>2</sup> |0.7  V |
+
+These estimates are based on a semicustom design in representative foundry processes (IBM 45nm/Samsung 7nm).
+
+### Compliancy
+
+The A2I core is compliant to Power ISA 2.06 and will need updates to be compliant with either version 3.0c or 3.1.  Power ISA 3.0c and 3.1 are the two Power ISA versions contributed to OpenPOWER Foundation by IBM.  Changes will include:
+
+* radix translation
+* op updates, to eliminate noncompliant ones and add missing ones required for a given compliancy level
+* various 'mode' and other changes to meet the open specification targeted compliancy level
+
+## Miscellaneous
+
+1. PVR = Ver 48/Rev 2
--- a/a2i.core
+++ b/a2i.core
@ -0,0 +1,325 @@
+CAPI=2:
+
+name : ::a2i:0
+description : A2I POWER processor core
+
+filesets:
+  ibm:
+    files:
+      - rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl
+      - rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl
+      - rel/src/vhdl/ibm/std_ulogic_function_support.vhdl
+      - rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl
+      - rel/src/vhdl/ibm/std_ulogic_support.vhdl
+    file_type : vhdlSource-2008
+    logical_name : ibm
+
+  support:
+    files:
+      - rel/src/vhdl/support/power_logic_pkg.vhdl
+    file_type : vhdlSource-2008
+    logical_name : support
+
+  clib:
+    files:
+      - rel/src/vhdl/clib/c_scom_addr_decode.vhdl
+      - rel/src/vhdl/clib/c_prism_csa32.vhdl
+      - rel/src/vhdl/clib/c_event_mux.vhdl
+      - rel/src/vhdl/clib/c_debug_mux8.vhdl
+      - rel/src/vhdl/clib/c_prism_bthmx.vhdl
+      - rel/src/vhdl/clib/c_debug_mux4.vhdl
+      - rel/src/vhdl/clib/c_prism_csa42.vhdl
+      - rel/src/vhdl/clib/c_debug_mux32.vhdl
+      - rel/src/vhdl/clib/c_debug_mux16.vhdl
+    file_type : vhdlSource-2008
+    logical_name : clib
+
+  tri:
+    files:
+      - rel/src/vhdl/tri/tri_cam_16x143_1r1w1c.vhdl
+      - rel/src/vhdl/tri/tri_slat_scan.vhdl
+      - rel/src/vhdl/tri/tri_plat.vhdl
+      - rel/src/vhdl/tri/tri_64x36_4w_1r1w.vhdl
+      - rel/src/vhdl/tri/ramb16_s9_s9.vhdl
+      - rel/src/vhdl/tri/tri_lcbcntl_mac.vhdl
+      - rel/src/vhdl/tri/tri_144x78_2r2w_eco.vhdl
+      - rel/src/vhdl/tri/tri_psro_soft.vhdl
+      - rel/src/vhdl/tri/tri_cam_32x143_1r1w1c.vhdl
+      - rel/src/vhdl/tri/tri_nand2_nlats.vhdl
+      - rel/src/vhdl/tri/tri_rlmlatch_p.vhdl
+      - rel/src/vhdl/tri/tri_inv_nlats.vhdl
+      - rel/src/vhdl/tri/tri_64x42_4w_1r1w.vhdl
+      - rel/src/vhdl/tri/tri_regk.vhdl
+      - rel/src/vhdl/tri/tri_inv_nlats_wlcb.vhdl
+      - rel/src/vhdl/tri/tri_32x35_8w_1r1w.vhdl
+      - rel/src/vhdl/tri/tri_direct_err_rpt.vhdl
+      - rel/src/vhdl/tri/ramb16_s18_s18.vhdl
+      - rel/src/vhdl/tri/tri_aoi22_nlats_wlcb.vhdl
+      - rel/src/vhdl/tri/tri_nlat_scan.vhdl
+      - rel/src/vhdl/tri/tri_144x78_2r2w.vhdl
+      - rel/src/vhdl/tri/tri_128x16_1r1w_1.vhdl
+      - rel/src/vhdl/tri/tri_256x162_4w_0.vhdl
+      - rel/src/vhdl/tri/tri_lcbcntl_array_mac.vhdl
+      - rel/src/vhdl/tri/tri_caa_prism_abist.vhdl
+      - rel/src/vhdl/tri/ramb16_s36_s36.vhdl
+      - rel/src/vhdl/tri/tri_cam_16x143_1r1w1c_matchline.vhdl
+      - rel/src/vhdl/tri/tri_lcbnd.vhdl
+      - rel/src/vhdl/tri/tri_cam_parerr_mac.vhdl
+      - rel/src/vhdl/tri/tri_nor2_nlats.vhdl
+      - rel/src/vhdl/tri/tri_bht.vhdl
+      - rel/src/vhdl/tri/tri_128x168_1w_0.vhdl
+      - rel/src/vhdl/tri/tri_regs.vhdl
+      - rel/src/vhdl/tri/tri_oai22_nlats.vhdl
+      - rel/src/vhdl/tri/tri_nlat.vhdl
+      - rel/src/vhdl/tri/tri_latches_pkg.vhdl
+      - rel/src/vhdl/tri/tri_lcbor.vhdl
+      - rel/src/vhdl/tri/tri_aoi22_nlats.vhdl
+      - rel/src/vhdl/tri/tri_512x288_9.vhdl
+      - rel/src/vhdl/tri/tri_lcbs.vhdl
+      - rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl
+      - rel/src/vhdl/tri/tri_serial_scom2.vhdl
+      - rel/src/vhdl/tri/tri_err_rpt.vhdl
+      - rel/src/vhdl/tri/tri_cam_32x143_1r1w1c_matchline.vhdl
+      - rel/src/vhdl/tri/tri_64x72_1r1w.vhdl
+      - rel/src/vhdl/tri/tri_rlmreg_p.vhdl
+      - rel/src/vhdl/tri/tri_boltreg_p.vhdl
+    file_type : vhdlSource-2008
+    logical_name : tri
+
+  rtl:
+    files:
+      - rel/src/vhdl/work/xuq_fxu_a.vhdl
+      - rel/src/vhdl/work/xuq_cpl_spr_cspr.vhdl
+      - rel/src/vhdl/work/a2x_axi_reg.vhdl
+      - rel/src/vhdl/work/fuq_nrm_sh.vhdl
+      - rel/src/vhdl/work/xuq_debug_mux32.vhdl
+      - rel/src/vhdl/work/xuq_agen_loca.vhdl
+      - rel/src/vhdl/work/a2x_axi_reg_S00.vhdl
+      - rel/src/vhdl/work/xuq_dec_sspr.vhdl
+      - rel/src/vhdl/work/xuq_spr_dacen.vhdl
+      - rel/src/vhdl/work/iuq_fxu_issue.vhdl
+      - rel/src/vhdl/work/fuq_add_glbc.vhdl
+      - rel/src/vhdl/work/xuq_lsu_cmd.vhdl
+      - rel/src/vhdl/work/xuq_add_glbglbci.vhdl
+      - rel/src/vhdl/work/fuq_tblexp.vhdl
+      - rel/src/vhdl/work/xuq_add_glbloc.vhdl
+      - rel/src/vhdl/work/xuq_agen_csmuxe.vhdl
+      - rel/src/vhdl/work/a2x_axi.vhdl
+      - rel/src/vhdl/work/xuq_alu_mult_boothdcd.vhdl
+      - rel/src/vhdl/work/fuq_dcd.vhdl
+      - rel/src/vhdl/work/xuq_lsu_debug.vhdl
+      - rel/src/vhdl/work/pcq_clks.vhdl
+      - rel/src/vhdl/work/fuq_loc8inc_lsb.vhdl
+      - rel/src/vhdl/work/xuq_alu_mult_core.vhdl
+      - rel/src/vhdl/work/iuq_ic_insmux.vhdl
+      - rel/src/vhdl/work/pcq_psro_soft.vhdl
+      - rel/src/vhdl/work/xuq_lsu_fgen.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dir_val32.vhdl
+      - rel/src/vhdl/work/xuq_agen_lo.vhdl
+      - rel/src/vhdl/work/fuq_add.vhdl
+      - rel/src/vhdl/work/fuq_loc8inc.vhdl
+      - rel/src/vhdl/work/iuq_rp.vhdl
+      - rel/src/vhdl/work/fuq_tblsqo.vhdl
+      - rel/src/vhdl/work/xuq_fxu_b.vhdl
+      - rel/src/vhdl/work/iuq_spr.vhdl
+      - rel/src/vhdl/work/fuq_byp.vhdl
+      - rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl
+      - rel/src/vhdl/work/fuq_gst_loa.vhdl
+      - rel/src/vhdl/work/xuq_alu_mask.vhdl
+      - rel/src/vhdl/work/iuq_dbg.vhdl
+      - rel/src/vhdl/work/iuq_ic_dir_cmp.vhdl
+      - rel/src/vhdl/work/xuq_spr.vhdl
+      - rel/src/vhdl/work/iuq_misc.vhdl
+      - rel/src/vhdl/work/xuq_alu_caor.vhdl
+      - rel/src/vhdl/work/pcq_regs.vhdl
+      - rel/src/vhdl/work/iuq_ram.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dir.vhdl
+      - rel/src/vhdl/work/xuq_alu_or3232.vhdl
+      - rel/src/vhdl/work/a2l2_axi.vhdl
+      - rel/src/vhdl/work/xuq_byp_xer.vhdl
+      - rel/src/vhdl/work/fuq_tblmul.vhdl
+      - rel/src/vhdl/work/xuq_fxu_gpr.vhdl
+      - rel/src/vhdl/work/fuq_hc16pp_lsb.vhdl
+      - rel/src/vhdl/work/xuq_cpl.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dir_tag_arr.vhdl
+      - rel/src/vhdl/work/pcq_clks_ctrl.vhdl
+      - rel/src/vhdl/work/xuq_ctrl_spr.vhdl
+      - rel/src/vhdl/work/mmq_tlb_cmp.vhdl
+      - rel/src/vhdl/work/fuq_mad.vhdl
+      - rel/src/vhdl/work/fuq_fmt.vhdl
+      - rel/src/vhdl/work/iuq.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dir_lru32.vhdl
+      - rel/src/vhdl/work/xuq_spr_dvccmp.vhdl
+      - rel/src/vhdl/work/iuq_uc.vhdl
+      - rel/src/vhdl/work/xuq_lsu_data.vhdl
+      - rel/src/vhdl/work/fuq_dcd_uc_hooks.vhdl
+      - rel/src/vhdl/work/fuq_alg.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dir_val16.vhdl
+      - rel/src/vhdl/work/xuq_agen_csmux.vhdl
+      - rel/src/vhdl/work/fuq_sa3.vhdl
+      - rel/src/vhdl/work/fuq_nrm_or16.vhdl
+      - rel/src/vhdl/work/xuq_alu_add.vhdl
+      - rel/src/vhdl/work/fuq_fpr.vhdl
+      - rel/src/vhdl/work/xuq_ctrl.vhdl
+      - rel/src/vhdl/work/xuq_agen_glbloc.vhdl
+      - rel/src/vhdl/work/fuq_alg_sh16.vhdl
+      - rel/src/vhdl/work/fuq_add_all1.vhdl
+      - rel/src/vhdl/work/fuq_lza_clz.vhdl
+      - rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl
+      - rel/src/vhdl/work/xuq_alu_mult.vhdl
+      - rel/src/vhdl/work/xuq_debug.vhdl
+      - rel/src/vhdl/work/a2x_dbug.vhdl
+      - rel/src/vhdl/work/xuq_lsu_derat.vhdl
+      - rel/src/vhdl/work/pcq_spr.vhdl
+      - rel/src/vhdl/work/iuq_axu_fu_dep_cmp.vhdl
+      - rel/src/vhdl/work/pcq_abist.vhdl
+      - rel/src/vhdl/work/iuq_ic_dir.vhdl
+      - rel/src/vhdl/work/xuq_alu_div.vhdl
+      - rel/src/vhdl/work/xuq_dec_b.vhdl
+      - rel/src/vhdl/work/fuq_mul_62.vhdl
+      - rel/src/vhdl/work/xuq_eccchk.vhdl
+      - rel/src/vhdl/work/iuq_slice.vhdl
+      - rel/src/vhdl/work/fuq_sto.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dir_lru16.vhdl
+      - rel/src/vhdl/work/mmq_htw.vhdl
+      - rel/src/vhdl/work/fuq_mul_bthmux.vhdl
+      - rel/src/vhdl/work/fuq_perv.vhdl
+      - rel/src/vhdl/work/pcq_ctrl.vhdl
+      - rel/src/vhdl/work/xuq_perf.vhdl
+      - rel/src/vhdl/work/xuq_lsu_l2cmdq.vhdl
+      - rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl
+      - rel/src/vhdl/work/fuq_tblmul_bthdcd.vhdl
+      - rel/src/vhdl/work/xuq_byp_cr.vhdl
+      - rel/src/vhdl/work/xuq_agen_glbglb.vhdl
+      - rel/src/vhdl/work/iuq_pkg.vhdl
+      - rel/src/vhdl/work/xuq_agen_locae.vhdl
+      - rel/src/vhdl/work/fuq.vhdl
+      - rel/src/vhdl/work/fuq_eie.vhdl
+      - rel/src/vhdl/work/xuq_cpl_pri.vhdl
+      - rel/src/vhdl/work/fuq_gst.vhdl
+      - rel/src/vhdl/work/xuq_lsu_data_rot32_lu.vhdl
+      - rel/src/vhdl/work/fuq_tblsqe.vhdl
+      - rel/src/vhdl/work/iuq_ic_select.vhdl
+      - rel/src/vhdl/work/fuq_tbllut.vhdl
+      - rel/src/vhdl/work/iuq_axu_fu_dec.vhdl
+      - rel/src/vhdl/work/xuq_lsu_data_ld.vhdl
+      - rel/src/vhdl/work/fuq_gst_add11.vhdl
+      - rel/src/vhdl/work/fuq_scr.vhdl
+      - rel/src/vhdl/work/mmq_dbg.vhdl
+      - rel/src/vhdl/work/xuq_fxu_spr_tspr.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dc_cntrl.vhdl
+      - rel/src/vhdl/work/xuq_dec_a.vhdl
+      - rel/src/vhdl/work/pcq_dbg.vhdl
+      - rel/src/vhdl/work/iuq_bp.vhdl
+      - rel/src/vhdl/work/mmq_tlb_matchline.vhdl
+      - rel/src/vhdl/work/pcq.vhdl
+      - rel/src/vhdl/work/xuq_alu_mult_csa22.vhdl
+      - rel/src/vhdl/work/iuq_fxu_dep.vhdl
+      - rel/src/vhdl/work/iuq_ic_miss.vhdl
+      - rel/src/vhdl/work/acq_soft.vhdl
+      - rel/src/vhdl/work/iuq_uc_control.vhdl
+      - rel/src/vhdl/work/fuq_tblmul_bthrow.vhdl
+      - rel/src/vhdl/work/iuq_fxu_dep_cmp.vhdl
+      - rel/src/vhdl/work/iuq_ifetch.vhdl
+      - rel/src/vhdl/work/xuq.vhdl
+      - rel/src/vhdl/work/fuq_cr2.vhdl
+      - rel/src/vhdl/work/iuq_axu_fu_dep.vhdl
+      - rel/src/vhdl/work/iuq_perf.vhdl
+      - rel/src/vhdl/work/xuq_byp.vhdl
+      - rel/src/vhdl/work/mmq_inval.vhdl
+      - rel/src/vhdl/work/fuq_gst_inc19.vhdl
+      - rel/src/vhdl/work/iuq_ic_dir_cmp30.vhdl
+      - rel/src/vhdl/work/xuq_fxua_data.vhdl
+      - rel/src/vhdl/work/fuq_csa22_h2.vhdl
+      - rel/src/vhdl/work/fuq_lze.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dc.vhdl
+      - rel/src/vhdl/work/mmq_perf.vhdl
+      - rel/src/vhdl/work/xuq_spr_tspr.vhdl
+      - rel/src/vhdl/work/fuq_lza.vhdl
+      - rel/src/vhdl/work/fuq_tblres.vhdl
+      - rel/src/vhdl/work/a2x_axi_intr.vhdl
+      - rel/src/vhdl/work/xuq_pkg.vhdl
+      - rel/src/vhdl/work/pcq_regs_fir.vhdl
+      - rel/src/vhdl/work/xuq_alu_rol64.vhdl
+      - rel/src/vhdl/work/fuq_alg_or16.vhdl
+      - rel/src/vhdl/work/iuq_uc_rom.vhdl
+      - rel/src/vhdl/work/mmq_tlb_lrat.vhdl
+      - rel/src/vhdl/work/fuq_mul.vhdl
+      - rel/src/vhdl/work/iuq_fxu_decode.vhdl
+      - rel/src/vhdl/work/bxq.vhdl
+      - rel/src/vhdl/work/iuq_ib_buff.vhdl
+      - rel/src/vhdl/work/a2x_pkg.vhdl
+      - rel/src/vhdl/work/xuq_fxu_spr.vhdl
+      - rel/src/vhdl/work/fuq_eov.vhdl
+      - rel/src/vhdl/work/mmq_perv.vhdl
+      - rel/src/vhdl/work/mmq_tlb_lrat_matchline.vhdl
+      - rel/src/vhdl/work/pcq_local_fir2.vhdl
+      - rel/src/vhdl/work/xuq_alu_ins.vhdl
+      - rel/src/vhdl/work/xuq_lsu_perf.vhdl
+      - rel/src/vhdl/work/fuq_hc16pp.vhdl
+      - rel/src/vhdl/work/xuq_cpl_spr_tspr.vhdl
+      - rel/src/vhdl/work/xuq_add_loc.vhdl
+      - rel/src/vhdl/work/xuq_cpl_fctr.vhdl
+      - rel/src/vhdl/work/mmq.vhdl
+      - rel/src/vhdl/work/pcq_dbg_event.vhdl
+      - rel/src/vhdl/work/xuq_alu_mrg.vhdl
+      - rel/src/vhdl/work/xuq_eccgen.vhdl
+      - rel/src/vhdl/work/xuq_agen_cmp.vhdl
+      - rel/src/vhdl/work/iuq_axu_fu_iss.vhdl
+      - rel/src/vhdl/work/fuq_mul_bthdcd.vhdl
+      - rel/src/vhdl/work/iuq_ib_buff_wrap.vhdl
+      - rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl
+      - rel/src/vhdl/work/fuq_alg_sh4.vhdl
+      - rel/src/vhdl/work/xuq_lsu_data_st.vhdl
+      - rel/src/vhdl/work/iuq_ic_ierat.vhdl
+      - rel/src/vhdl/work/iuq_perv.vhdl
+      - rel/src/vhdl/work/xuq_alu_mult_boothrow.vhdl
+      - rel/src/vhdl/work/xuq_perv.vhdl
+      - rel/src/vhdl/work/xuq_add_csmux.vhdl
+      - rel/src/vhdl/work/xuq_cpl_spr.vhdl
+      - rel/src/vhdl/work/fuq_mul_92.vhdl
+      - rel/src/vhdl/work/xuq_cpl_br.vhdl
+      - rel/src/vhdl/work/iuq_ic.vhdl
+      - rel/src/vhdl/work/iuq_slice_wrap.vhdl
+      - rel/src/vhdl/work/xuq_cpl_fxub.vhdl
+      - rel/src/vhdl/work/fuq_pic.vhdl
+      - rel/src/vhdl/work/fuq_alg_add.vhdl
+      - rel/src/vhdl/work/a2x_scom.vhdl
+      - rel/src/vhdl/work/xuq_byp_gpr.vhdl
+      - rel/src/vhdl/work/xuq_lsu_cmp.vhdl
+      - rel/src/vhdl/work/fuq_nrm.vhdl
+      - rel/src/vhdl/work/pcq_abist_bolton_frontend.vhdl
+      - rel/src/vhdl/work/xuq_agen.vhdl
+      - rel/src/vhdl/work/xuq_spr_cspr.vhdl
+      - rel/src/vhdl/work/fuq_lza_ej.vhdl
+      - rel/src/vhdl/work/xuq_lsu_mux41.vhdl
+      - rel/src/vhdl/work/mmq_tlb_req.vhdl
+      - rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl
+      - rel/src/vhdl/work/xuq_fxu_spr_cspr.vhdl
+      - rel/src/vhdl/work/pcq_clks_stg.vhdl
+      - rel/src/vhdl/work/fuq_mul_bthrow.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl
+      - rel/src/vhdl/work/iuq_bd.vhdl
+      - rel/src/vhdl/work/fuq_hc16pp_msb.vhdl
+      - rel/src/vhdl/work/xuq_add.vhdl
+      - rel/src/vhdl/work/fuq_alg_bypmux.vhdl
+      - rel/src/vhdl/work/xuq_alu.vhdl
+      - rel/src/vhdl/work/xuq_agen_glbloc_lsb.vhdl
+      - rel/src/vhdl/work/xuq_lsu_dc_arr.vhdl
+      - rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl
+      - rel/src/vhdl/work/mmq_spr.vhdl
+      - rel/src/vhdl/work/mmq_tlb_ctl.vhdl
+      - rel/src/vhdl/work/a2x_reset.vhdl
+      - rel/src/vhdl/work/fuq_rnd.vhdl
+    file_type : vhdlSource-2008
+
+targets:
+  default:
+    filesets : [ibm, support, clib, tri, rtl]
+
+  synth:
+    filesets : [ibm, support, clib, tri, rtl]
+    toplevel : a2x_axi
+    tools:
+      vivado:
+        pnr : none
--- a/rel/doc/A2L2.pdf
+++ b/rel/doc/A2L2.pdf
--- a/rel/doc/A2_BGQ.pdf
+++ b/rel/doc/A2_BGQ.pdf
--- a/rel/doc/HC23.18.121.BlueGene-IBM_BQC_HC23_20110818.pdf
+++ b/rel/doc/HC23.18.121.BlueGene-IBM_BQC_HC23_20110818.pdf
--- a/rel/doc/a2_1.png
+++ b/rel/doc/a2_1.png
--- a/rel/doc/a2_build_video.md
+++ b/rel/doc/a2_build_video.md
@ -0,0 +1,3 @@
+#### This is a short video showing the build process for A2I, as described in ```rel/readme.md```.
+
+[A2I Build Process](https://drive.google.com/file/d/1YsMWHYQBn1pRCGKneekjSP0c0aqyxdQR/view?usp=sharing)
--- a/rel/doc/a2_run_video.md
+++ b/rel/doc/a2_run_video.md
@ -0,0 +1,4 @@
+
+This is a short video showing a bitstream load and simple SMT4 test loop running on A2I.
+
+[A2I SMT4 Example](https://drive.google.com/file/d/1bBEbAC9SiCxjW6XiXJGRjZ7Cegs8O3eN/view?usp=sharing)
--- a/rel/doc/p_1.png
+++ b/rel/doc/p_1.png
--- a/rel/doc/w_1.png
+++ b/rel/doc/w_1.png
--- a/rel/doc/w_2.png
+++ b/rel/doc/w_2.png
--- a/rel/doc/w_3.png
+++ b/rel/doc/w_3.png
--- a/rel/doc/w_4.png
+++ b/rel/doc/w_4.png
--- a/scripts/run.py
+++ b/scripts/run.py
@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+
+"""VUnit run script."""
+
+from pathlib import Path
+from vunit import VUnit
+
+_rel = Path(__file__).parent / "rel"
+
+prj = VUnit.from_argv()
+
+for libName in ["support", "ibm", "clib", "tri"]:
+    prj.add_library(libName).add_source_files(_rel / "src" / "vhdl" / f"{libName}" / "*.vhdl")
+
+# VUnit doesn't accept libraries named work. These files are compiled to the top library
+prj.add_library("top").add_source_files(_rel / "src" / "vhdl" / "work" / "*.vhdl")
+
+# Simulation only library containing VHDL mocks for Verilog UNIMACROs
+prj.add_library("unimacro").add_source_files(_rel / "sim" / "unimacro" / "*.vhdl")
+
+prj.main()