Verilog 1 1

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue

Updated 2 days ago

A tiny Open POWER ISA softcore written in VHDL 2008

Updated 3 days ago

Updated 4 days ago

This is the main libreBMC repo that contains an overview of the project and useful links. Start here.

Updated 4 days ago

VHDL 2 1

The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers

Updated 5 days ago

Updated 6 days ago

This repo houses or points to the gateware (FPGA image code) for the librebmc project

Updated 2 weeks ago

This is the main libreBMC repo that contains an overview of the project and useful links. Start here.

Updated 2 weeks ago

Pointers to openBMC code needed to boot the AC922 using the FPGA

Updated 4 weeks ago

High-specific-bandwidth memory design

Updated 2 months ago

A tiny Open POWER ISA softcore written in VHDL 2008

Updated 2 months ago

OpenPOWER Foundation General Information & Repository Listing

Updated 2 months ago

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue

Updated 2 months ago

The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers

Updated 2 months ago

The purpose of this design is to enable the AC922 to accept a DC-SCM v1.0 hardware management module. This enables AC922 as a development platform for DC-SCM development and test.

Updated 4 months ago

OpenPOWER Foundation General Information & Repository Listing

Updated 5 months ago

Fork for Sandy Woodward to make changes prior to merging to master.

Updated 5 months ago