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93 lines
3.1 KiB
VHDL
93 lines
3.1 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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-- both resets are negative-active!
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entity a2x_reset is
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port (
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clk : in std_logic;
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reset_in : in std_logic;
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reset : out std_logic
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);
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end a2x_reset;
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architecture a2x_reset of a2x_reset is
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constant reset_period : integer := 32;
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signal reset_in_q : std_logic := '0';
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signal reset_q : std_logic := '0';
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signal counter_q : std_logic_vector(0 to 31) := x"00000000";
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function inc(a: in std_logic_vector) return std_logic_vector is
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variable res: std_logic_vector(0 to a'length-1);
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begin
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res := std_logic_vector(unsigned(a) + 1);
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return res;
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end function;
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function eq(a: in std_logic_vector; b: in integer) return boolean is
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variable res: boolean;
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begin
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res := unsigned(a) = b;
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return res;
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end function;
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function leq(a: in std_logic_vector; b: in integer) return boolean is
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variable res: boolean;
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begin
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res := unsigned(a) <= b;
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return res;
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end function;
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begin
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FF: process (clk) begin
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if (rising_edge(clk)) then
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reset_in_q <= reset_in;
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if (reset_in_q = '1' and reset_in = '0') then -- edge-trigger hi->lo
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counter_q <= (others => '0');
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elsif (leq(counter_q, reset_period)) then -- reset period
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counter_q <= inc(counter_q);
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reset_q <= '0';
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else -- normal
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counter_q <= counter_q;
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reset_q <= '1';
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end if;
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end if;
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end process;
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reset <= reset_q;
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end architecture a2x_reset;
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